]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
system: build fix, removed generated HDL wrappers
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Fri, 1 Apr 2016 08:44:59 +0000 (10:44 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Fri, 1 Apr 2016 08:44:59 +0000 (10:44 +0200)
commitdbb195f9fd8c127071e82bdea66d9e006e928f33
tree02f036ffa6097888a3b49c8a7598fe8e8952df31
parent33fc4618944d82aa8731ccc916ad758d139960ae
system: build fix, removed generated HDL wrappers
system/.gitignore
system/script/build.tcl
system/script/recreate.tcl
system/src/top/hdl/top.vhd [deleted file]
system/src/top/hdl/top_wrapper.vhd [deleted file]
system/src/top/top.bd
system/src/top/top.bxml [deleted file]