]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blob - system/.gitignore
projects / fpga / zynq / canbench-sw.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
system: build fix, removed generated HDL wrappers
[fpga/zynq/canbench-sw.git] / system / .gitignore
1 /project
2 /src/top/hdl/*
3 /src/top/ip/*
4 /src/top/hw_handoff/*
5 /src/top/top.bxml
6 /src/top/top_ooc.xdc
7
8 vivado*.jou
9 vivado*.log
10 .Xil
CAN benchmark FPGA design and software for MicroZed board