1 <?xml version="1.0" encoding="UTF-8"?>
2 <Root MajorVersion="0" MinorVersion="33">
3 <CompositeFile CompositeFileTopName="top" CanBeSetAsTop="true" CanDisplayChildGraph="true">
4 <Description>Composite Fileset</Description>
5 <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1458842019"/>
6 <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1458842019"/>
7 <Generation Name="SIMULATION" State="GENERATED" Timestamp="1458842019"/>
8 <FileCollection Name="SOURCES" Type="SOURCES">
9 <File Name="ip/top_processing_system7_0_1/top_processing_system7_0_1.xci" Type="IP">
10 <Instance HierarchyPath="processing_system7_0"/>
11 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
12 <Library Name="xil_defaultlib"/>
13 <UsedIn Val="SYNTHESIS"/>
14 <UsedIn Val="IMPLEMENTATION"/>
15 <UsedIn Val="SIMULATION"/>
17 <File Name="ip/top_processing_system7_0_axi_periph_0/top_processing_system7_0_axi_periph_0.xci" Type="IP">
18 <Instance HierarchyPath="processing_system7_0_axi_periph"/>
19 <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
20 <Library Name="xil_defaultlib"/>
21 <UsedIn Val="SYNTHESIS"/>
22 <UsedIn Val="IMPLEMENTATION"/>
23 <UsedIn Val="SIMULATION"/>
25 <File Name="ip/top_rst_processing_system7_0_100M_0/top_rst_processing_system7_0_100M_0.xci" Type="IP">
26 <Instance HierarchyPath="rst_processing_system7_0_100M"/>
27 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
28 <Library Name="xil_defaultlib"/>
29 <UsedIn Val="SYNTHESIS"/>
30 <UsedIn Val="IMPLEMENTATION"/>
31 <UsedIn Val="SIMULATION"/>
33 <File Name="ip/top_can_merge_0_1/top_can_merge_0_1.xci" Type="IP">
34 <Instance HierarchyPath="can_merge_0"/>
35 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
36 <Library Name="xil_defaultlib"/>
37 <UsedIn Val="SYNTHESIS"/>
38 <UsedIn Val="IMPLEMENTATION"/>
39 <UsedIn Val="SIMULATION"/>
41 <File Name="hdl/top.vhd" Type="VHDL">
42 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
43 <Library Name="xil_defaultlib"/>
44 <UsedIn Val="SYNTHESIS"/>
45 <UsedIn Val="SIMULATION"/>
47 <File Name="top_ooc.xdc" Type="XDC">
48 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
49 <Library Name="xil_defaultlib"/>
50 <UsedIn Val="SYNTHESIS"/>
51 <UsedIn Val="IMPLEMENTATION"/>
52 <UsedIn Val="OUT_OF_CONTEXT"/>
54 <File Name="hw_handoff/top.hwh" Type="HwHandoff">
55 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
56 <Library Name="xil_defaultlib"/>
57 <UsedIn Val="HW_HANDOFF"/>
59 <File Name="hw_handoff/top_bd.tcl">
60 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
61 <Library Name="xil_defaultlib"/>
62 <UsedIn Val="HW_HANDOFF"/>
64 <File Name="hdl/top.hwdef">
65 <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
66 <Library Name="xil_defaultlib"/>
67 <UsedIn Val="HW_HANDOFF"/>