]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blob - system/script/build.tcl
system: build fix, removed generated HDL wrappers
[fpga/zynq/canbench-sw.git] / system / script / build.tcl
1 set jobs 4
2
3 open_project ../project/canbench.xpr
4 reset_run synth_1
5 reset_run impl_1
6
7 set design_file ../src/top/top.bd
8 set obj [get_files $design_file]
9 generate_target all $obj
10 export_ip_user_files -of_objects $obj -no_script -force -quiet
11
12 #foreach ip [get_ips] {
13 #       create_ip_run $ip
14 #}
15 #launch_run -jobs 4 {top_rst_processing_system7_0_100M_0_synth_1 top_processing_system7_0_1_synth_1 top_can_merge_0_1_synth_1}
16 #launch_run -jobs 4 [get_ips]
17 #export_simulation -of_objects $obj -directory ../project/canbench.ip_user_files/sim_scripts -force -quiet
18
19 launch_runs synth_1 -jobs $jobs
20 wait_on_run synth_1
21 launch_runs impl_1 -jobs $jobs
22 wait_on_run impl_1
23 launch_runs impl_1 -jobs $jobs -to_step write_bitstream
24 wait_on_run impl_1
25 file copy -force ../project/canbench.runs/impl_1/top_wrapper.sysdef ../system.hdf