rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/history

]> rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/history - msp_motion.vhd

2011-08-03	Bast	Merge branch 'master' of rtime.felk.cvut.cz:/fpga/virte... master	blob \| commitdiff \| raw
2011-08-03	Bast	Added index capture register hardware	blob \| commitdiff \| raw
2011-05-27	Vladimir Burian	Submodule PWM and toplevel updated.	blob \| commitdiff \| raw \| diff to current
2011-05-18	Vladimir Burian	PWM output polarity inverted.	blob \| commitdiff \| raw \| diff to current
2011-05-18	Vladimir Burian	Improper top module signals initialization.	blob \| commitdiff \| raw \| diff to current
2011-05-18	Vladimir Burian	Reset changed to use Global Set Reset network.	blob \| commitdiff \| raw \| diff to current
2011-05-01	Vladimir Burian	Error in MCU external data bus multiplexer	blob \| commitdiff \| raw \| diff to current
2011-04-17	Vladimir Burian	Motor feedback IRQ generator	blob \| commitdiff \| raw \| diff to current
2011-04-17	Vladimir Burian	MCU interface to Qcount (32-bit output)	blob \| commitdiff \| raw \| diff to current
2011-04-17	Vladimir Burian	GPIO connected to MCU	blob \| commitdiff \| raw \| diff to current
2011-04-17	Vladimir Burian	MCU peripheral bus signals declared	blob \| commitdiff \| raw \| diff to current
2011-04-17	Vladimir Burian	PWM (MCC) connected to MCU	blob \| commitdiff \| raw \| diff to current
2011-04-14	Vladimir Burian	Top-level modul created.	blob \| commitdiff \| raw \| diff to current

MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board