-
+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
-entity div8 is
+entity divider is
port (
clk_in: in std_logic;
- clk_out: out std_logic
+ div12: out std_logic
);
-end div8;
+end divider;
-architecture behavioral of div8 is
+architecture behavioral of divider is
signal count : std_logic_vector (2 downto 0);
+ signal tmp : std_logic;
begin
divider : process
begin
wait until (clk_in'event and clk_in='1');
- if (count="111") then
+ if (count(2 downto 1)="11") then
count<="000";
+ tmp <= not tmp;
else
count <= std_logic_vector(unsigned(count) + 1);
end if;
- clk_out <= count(2);
+ div12<=tmp;
end process divider;
);
end component;
- component div8 is
+ --frequency division by 12
+ component divider is
port (
- --reset: in std_logic;
clk_in: in std_logic;
- clk_out: out std_logic
+ div12: out std_logic
);
end component;
signal income_data_valid: std_logic;
- signal clk_3M1: std_logic;
+ signal clk_4M17: std_logic;
end generate;
- div8_map: div8
+ div12_map: divider
port map(
--reset => income_data_valid,
clk_in => gpio_clk,
- clk_out => clk_3M1
+ div12 => clk_4M17
);
+ -- ADC needs 3.2 MHz clk when powered from +5V Vcc
+ -- 2.0 MHz clk when +2.7V Vcc
+ -- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
+ -- while we use +3.3V Vcc
adc_reader_map: adc_reader
port map(
- clk =>clk_3M1,
+ clk =>clk_4M17,
adc_reset => adc_reset,
adc_miso => adc_miso,
adc_channels => adc_channels,