Modified ADC clk frequency from 3.2 MHz to 2.08Mhz

diff --git a/pmsm-control/div8.vhdl b/pmsm-control/divider.vhdl
similarity index 58%
rename from pmsm-control/div8.vhdl
rename to pmsm-control/divider.vhdl
index f243183090361dc9c5c9580c55e4d401a37a7388..5f9a13fc49e197b95615da8d174b7b6482b3a658 100644 (file)
--- a/pmsm-control/div8.vhdl
+++ b/pmsm-control/divider.vhdl
@@ -1,33 +1,36 @@
-
+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz 

 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 

-entity div8 is
+entity divider is

 
 port (
        clk_in: in std_logic;
 
 port (
        clk_in: in std_logic;

-       clk_out: out std_logic
+       div12: out std_logic

 );
 );

-end div8;
+end divider;

 
 
 
 

-architecture behavioral of div8 is
+architecture behavioral of divider is

        signal count : std_logic_vector (2 downto 0);
        signal count : std_logic_vector (2 downto 0);

+       signal tmp : std_logic;

 begin
        
        
        divider : process 
        begin
                wait until (clk_in'event and clk_in='1');
 begin
        
        
        divider : process 
        begin
                wait until (clk_in'event and clk_in='1');

-               if (count="111") then
+               if (count(2 downto 1)="11") then

                        count<="000";
                        count<="000";

+                       tmp <= not tmp;

                else
                        count <= std_logic_vector(unsigned(count) + 1);
                end if;
                else
                        count <= std_logic_vector(unsigned(count) + 1);
                end if;

-                       clk_out <= count(2);
+                       div12<=tmp;

     end process divider;
 
        
     end process divider;
 
        

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 45ea914ac46af22bba59f04304c3b76918f55d25..4db7abf7b1104c896771e7194ef7473bbf47346c 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -133,11 +133,11 @@ architecture behavioral of rpi_mc_simple_dc is
        );
        end component;
        
        );
        end component;
        

-       component div8 is
+       --frequency division by 12
+       component divider is

        port (
        port (

-               --reset: in std_logic;

                clk_in: in std_logic;
                clk_in: in std_logic;

-               clk_out: out std_logic
+               div12: out std_logic

        );
        end component;
        
        );
        end component;
        


@@ -183,7 +183,7 @@ architecture behavioral of rpi_mc_simple_dc is
        
        signal income_data_valid: std_logic;
        
        
        signal income_data_valid: std_logic;
        

-       signal clk_3M1: std_logic;
+       signal clk_4M17: std_logic;

        
        
        
        
        
        


@@ -242,16 +242,20 @@ begin
        end generate;
        
        
        end generate;
        
        

-       div8_map: div8 
+       div12_map: divider

        port map(
                --reset => income_data_valid,
                clk_in => gpio_clk,
        port map(
                --reset => income_data_valid,
                clk_in => gpio_clk,

-               clk_out => clk_3M1
+               div12 => clk_4M17

        );
        
        );
        

+       -- ADC needs 3.2 MHz clk when powered from +5V Vcc
+       --           2.0 MHz clk when +2.7V Vcc
+       -- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
+       --        while we use +3.3V Vcc     

        adc_reader_map: adc_reader 
        port map(
        adc_reader_map: adc_reader 
        port map(

-               clk =>clk_3M1,
+               clk =>clk_4M17,

                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,
                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,

diff --git a/pmsm-control/syn.tcl b/pmsm-control/syn.tcl
index 1a3a609e68b821ada174560b4dfe1438a608672a..19ab95ad2afbfaf1413efb7e7bff395d3d853d82 100644 (file)
--- a/pmsm-control/syn.tcl
+++ b/pmsm-control/syn.tcl
@@ -8,7 +8,7 @@ add_file util.vhdl
 add_file qcounter.vhdl
 add_file dff.vhdl
 add_file mcpwm.vhdl
 add_file qcounter.vhdl
 add_file dff.vhdl
 add_file mcpwm.vhdl

-add_file div8.vhdl
+add_file divider.vhdl

 add_file adc_reader.vhdl
 
 # top-level
 add_file adc_reader.vhdl
 
 # top-level