Modified ADC clk frequency from 3.2 MHz to 2.08Mhz
authorMartin Prudek <prudemar@fel.cvut.cz>
Thu, 30 Apr 2015 16:42:12 +0000 (18:42 +0200)
committerMartin Prudek <prudemar@fel.cvut.cz>
Thu, 30 Apr 2015 16:42:12 +0000 (18:42 +0200)
commit20d2ad19b7050e37e1ebdb9f13c7027eabd151a2
tree225891fd6aa5dbfa42ebde674a5ac8885e02a24f
parent44c23daa6e0d5d35e892b79684b239c1a0e67f25
Modified ADC clk frequency from 3.2 MHz to 2.08Mhz
pmsm-control/divider.vhdl [moved from pmsm-control/div8.vhdl with 58% similarity]
pmsm-control/rpi_pmsm_control.vhdl
pmsm-control/syn.tcl