signal rx_done_cnt_r : natural range 0 to (2**rx_done_cnt_width_c - 1);
--
signal rx_crc_error_s : std_logic;
+ signal rx_crc_error_r : std_logic;
begin
master_transmitter: lxmaster_transmitter
wire_in:
process(ce_i, ce_r, reset_reg_r, bls_i, address_i, mem_trans_data_s,
mem_recv_data_s, data_i, register_trans_out_s, register_recv_out_s,
- register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r, rx_crc_error_s)
+ register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r, rx_crc_error_r)
begin
mem_trans_en_s <= '0';
state_o_s(7 downto rx_done_cnt_width_c) <= (others => '0');
state_o_s(rx_done_div_width_c + 8 - 1 downto 8) <= rx_done_ratio_r;
state_o_s(14 downto rx_done_div_width_c + 8) <= (others => '0');
- state_o_s(15) <= rx_crc_error_s;
+ state_o_s(15) <= rx_crc_error_r;
end if;
end if;
if reset_i = '1' then
rx_done_cnt_r <= 0;
+ rx_crc_error_r <= '0';
elsif rx_done_s = '1' then
rx_done_cnt_r <= rx_done_cnt_r + 1;
+ rx_crc_error_r <= rx_crc_error_s;
end if;
end process;