From: Pavel Pisa Date: Sun, 22 Feb 2015 14:35:44 +0000 (+0100) Subject: LX master: RX CRC error is updated is status register in the same clock as seq. num. X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/lx-cpu1/lx-rocon.git/commitdiff_plain/8d2755529f4c01a57c6b275469f16e5d8c7fda5a LX master: RX CRC error is updated is status register in the same clock as seq. num. If update is not at the same time then false RX done can be detected by firmware which does not mask compare result sequence number bits only. Signed-off-by: Pavel Pisa --- diff --git a/hw/bus_lxmaster.vhd b/hw/bus_lxmaster.vhd index f443027..172f0cb 100644 --- a/hw/bus_lxmaster.vhd +++ b/hw/bus_lxmaster.vhd @@ -79,6 +79,7 @@ architecture Behavioral of bus_lxmaster is signal rx_done_cnt_r : natural range 0 to (2**rx_done_cnt_width_c - 1); -- signal rx_crc_error_s : std_logic; + signal rx_crc_error_r : std_logic; begin master_transmitter: lxmaster_transmitter @@ -158,7 +159,7 @@ rx_done_divider : cnt_div wire_in: process(ce_i, ce_r, reset_reg_r, bls_i, address_i, mem_trans_data_s, mem_recv_data_s, data_i, register_trans_out_s, register_recv_out_s, - register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r, rx_crc_error_s) + register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r, rx_crc_error_r) begin mem_trans_en_s <= '0'; @@ -265,7 +266,7 @@ wire_in: state_o_s(7 downto rx_done_cnt_width_c) <= (others => '0'); state_o_s(rx_done_div_width_c + 8 - 1 downto 8) <= rx_done_ratio_r; state_o_s(14 downto rx_done_div_width_c + 8) <= (others => '0'); - state_o_s(15) <= rx_crc_error_s; + state_o_s(15) <= rx_crc_error_r; end if; end if; @@ -317,8 +318,10 @@ update: if reset_i = '1' then rx_done_cnt_r <= 0; + rx_crc_error_r <= '0'; elsif rx_done_s = '1' then rx_done_cnt_r <= rx_done_cnt_r + 1; + rx_crc_error_r <= rx_crc_error_s; end if; end process;