signal lxmaster_data_counter_r : natural range 0 to 15;
-- Receiption
signal lxmaster_frame_start_s : std_logic;
- signal lxmaster_sync_s : std_logic;
- signal lxmaster_sync_r : std_logic;
- signal lxmaster_sync_last_bit_s : std_logic;
- signal lxmaster_sync_last_bit_r : std_logic;
signal miso_s : std_logic;
signal sync_s : std_logic;
signal prev_sync_s : std_logic;
-- Defaults
lxmaster_ram_reset_s <= '0';
- lxmaster_sync_last_bit_s <= '0';
rx_done_s <= '0';
-- Defaults of state variables (no change)
ram_addr_s <= ram_addr_r;
if reset_i = '1' then
lxmaster_num_data_s <= x"00";
lxmaster_state_s <= ST_END;
- lxmaster_sync_s <= '0';
lxmaster_last_word_s <= '0';
--
ram_addr_s <= '0' & x"00";
else
-- OK, we are enabled, default values
- lxmaster_sync_s <= '0'; -- Not transferring
ram_en_s <= '0'; -- Not reading
case lxmaster_state_r is
when ST_READY =>
-- We are ready to begin transferring
- lxmaster_sync_s <= '1'; -- Transferring data next cycle
lxmaster_data_counter_s <= 0; -- Reset counter
lxmaster_state_s <= ST_XFER; --Go to transfer loop
when ST_XFER =>
- lxmaster_sync_s <= '1'; -- Transferring data next cycle
if inc_ram_addr_r = '1' then
-- Update address if second and other loop
lxmaster_crc_error_s <= lxmaster_crc_error_int_r or crc_bit_mismatch_v;
else
-- Begin transmission of next data
- lxmaster_sync_s <= '1'; -- Transferring data next cycle
lxmaster_data_counter_s <= 0; -- Reset counter
lxmaster_state_s <= ST_XFER; --Go to transfer loop
end if;
else
- -- Sync goes inactive to signalize termination if we're on last message
- if lxmaster_data_counter_r /= 6 or lxmaster_num_data_r /= x"00" then
- lxmaster_sync_s <= '1';
- else
- lxmaster_sync_last_bit_s <= '1';
- end if;
-
lxmaster_data_counter_s <= lxmaster_data_counter_r + 1; -- Increment
end if;
end if;
end if;
- lxmaster_sync_r <= lxmaster_sync_s;
- lxmaster_sync_last_bit_r <= lxmaster_sync_last_bit_s;
-
prev_sync_r <= prev_sync_s;
received_data_r <= received_data_s;