]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/history - hw/lx_crosdom_ser_fifo.vhd
Clean DAD test code a little to use symbolic names for registers and bits.
[fpga/lx-cpu1/lx-dad.git] / hw / lx_crosdom_ser_fifo.vhd
2015-02-15 Pavel PisaRemove nonstandard ieee.std_logic_arith and ieee.std_lo...
2015-02-15 Pavel PisaInclude hardware design of FPGA peripherals to external...