hw/measurement_register.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.lx_dad_pkg.all;
   5
   6 -- Transaction measurement register
   7
   8 entity measurement_register is
   9         generic
  10         (
  11                 id_g   : std_logic_vector(31 downto 0) := (others => '0')
  12         );
  13         port
  14         (
  15                 -- Clock
  16                 clk_i    : in std_logic;
  17                 -- Reset
  18                 reset_i  : in std_logic;
  19                 -- Chip enable
  20                 ce_i     : in std_logic;
  21                 -- Switch
  22                 switch_i : in std_logic;
  23                 -- Data bus
  24                 data_i   : in std_logic_vector(31 downto 0);
  25                 data_o   : out std_logic_vector(31 downto 0);
  26                 -- Bus signals
  27                 bls_i    : in std_logic_vector(3 downto 0)
  28         );
  29 end measurement_register;
  30
  31 architecture Behavioral of measurement_register is
  32         signal value_s : std_logic_vector(31 downto 0);
  33 begin
  34
  35         data_o <= value_s when switch_i = '1' else id_g;
  36
  37 -- Write waits for clock
  38 memory_bus_write:
  39         process
  40         begin
  41
  42                 wait until clk_i'event and clk_i = '1';
  43
  44                 if reset_i = '1' then
  45                         value_s <= (others => '0');
  46                 else
  47
  48                         if ce_i = '1' and bls_i /= "0000" then
  49
  50                                 if bls_i(0) = '1' then
  51                                         value_s(7 downto 0)   <= data_i(7 downto 0);
  52                                 end if;
  53                                 if bls_i(1) = '1' then
  54                                         value_s(15 downto 8)  <= data_i(15 downto 8);
  55                                 end if;
  56                                 if bls_i(2) = '1' then
  57                                         value_s(23 downto 16) <= data_i(23 downto 16);
  58                                 end if;
  59                                 if bls_i(3) = '1' then
  60                                         value_s(31 downto 24) <= data_i(31 downto 24);
  61                                 end if;
  62
  63                         end if;
  64                 end if;
  65
  66         end process;
  67
  68 end Behavioral;
  69