]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree - system/src/constrs/
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / src / constrs /
drwxr-xr-x   ..
-rw-r--r-- 9787 microzed_CAN-CC_RevA.xdc
-rw-r--r-- 12283 microzed_apo-rev1.xdc