]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
-rw-r--r-- 29 .gitignore
-rw-r--r-- 99 .gitmodules
-rw-r--r-- 786 Makefile
-rw-r--r-- 1831 README.txt
m--------- - can-benchmark
drwxr-xr-x - petalinux
drwxr-xr-x - scripts
drwxr-xr-x - system