]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blob - .gitignore
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / .gitignore
1 .Xil
2 vivado*.log
3 vivado*.jou