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fpga/virtex2/uart.git
2011-01-09 Vladimir BurianAdded TimerA instance. IRQs are unconnected. commit | commitdiff | tree | snapshot
2011-01-09 Vladimir BurianCopied all needed files. commit | commitdiff | tree | snapshot
2011-01-09 Vladimir Burian+ OpenMSP430 submodule. commit | commitdiff | tree | snapshot
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board