Toplevel UART signals renamed.

[fpga/virtex2/uart.git] / openMSP430_uart.ucf

diff --git a/openMSP430_uart.ucf b/openMSP430_uart.ucf
index 480060c38096a64541a8d1b77846b04d266e7e72..e28d6b55dcddfd0bef00ca09c9a9d6a9d12f564e 100644 (file)
--- a/openMSP430_uart.ucf
+++ b/openMSP430_uart.ucf
@@ -11,8 +11,8 @@ NET "RESET"             LOC = "B6";
 # RS-232 Port                                                                  #
 #==============================================================================#
 
-NET "RXD"               LOC = "A7";     # input to RS232 driver
-NET "TXD"               LOC = "B7";     # output from RS232 driver
+NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
+NET "RXD"               LOC = "B7";     # input to the board (to FPGA)
 
 #==============================================================================#
 # Incremental rotary encoder                                                   #