rtime.felk.cvut.cz Git - fpga/virtex2/msp

]> rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/shortlog

2011-04-17	Vladimir Burian	MCU interface to Qcount (32-bit output)	commit \| commitdiff \| tree \| snapshot
2011-04-17	Vladimir Burian	GPIO connected to MCU	commit \| commitdiff \| tree \| snapshot
2011-04-17	Vladimir Burian	MCU peripheral bus signals declared	commit \| commitdiff \| tree \| snapshot
2011-04-17	Vladimir Burian	GPIO and qcount MCU peripherals added	commit \| commitdiff \| tree \| snapshot
2011-04-17	Vladimir Burian	PWM (MCC) connected to MCU	commit \| commitdiff \| tree \| snapshot
2011-04-17	Vladimir Burian	Submodule PWM updated	commit \| commitdiff \| tree \| snapshot
2011-04-16	Vladimir Burian	Submodule Quadcount added	commit \| commitdiff \| tree \| snapshot
2011-04-16	Vladimir Burian	Submodule PWM (MCC) added	commit \| commitdiff \| tree \| snapshot
2011-04-14	Vladimir Burian	HDL Makefile added	commit \| commitdiff \| tree \| snapshot
2011-04-14	Vladimir Burian	Top-level modul created.	commit \| commitdiff \| tree \| snapshot
2011-04-14	Vladimir Burian	Submodule openMSP430 added	commit \| commitdiff \| tree \| snapshot
2011-04-14	Vladimir Burian	Initial empty commit	commit \| commitdiff \| tree \| snapshot

MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board