]> rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/commit
projects / fpga / virtex2 / msp_motion.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9461fce) | patch
Top-level modul created.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 14 Apr 2011 20:31:11 +0000 (22:31 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 14 Apr 2011 20:31:11 +0000 (22:31 +0200)
commit9d3f45834365a865c2d287967df1f4a10efed148
tree5157b61efadfd1093c497c913dba58f50228b1fdtree | snapshot
parent9461fcebf6c9a46aab50c57f10367ac675c60a8fcommit | diff
Top-level modul created.

Contains openMSP430, user constraints file and MCU memory definition file.
memory.bmm [new file with mode: 0644] blob
msp_motion.prj [new file with mode: 0644] blob
msp_motion.ucf [new file with mode: 0644] blob
msp_motion.vhd [new file with mode: 0644] blob
MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board