Top-level modul created.

Contains openMSP430, user constraints file and MCU memory definition file.

diff --git a/memory.bmm b/memory.bmm
new file mode 100644 (file)
index 0000000..77a6d45
--- /dev/null
+++ b/memory.bmm
@@ -0,0 +1,35 @@
+// ram_generic: 2x16kB, BRAM_TYPE=RAMB16_S2
+ADDRESS_SPACE blockrom RAMB16 [0x8000:0xffff]
+  BUS_BLOCK
+      openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[3].BRAM [7:6];
+      openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[2].BRAM [5:4];
+      openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[1].BRAM [3:2];
+      openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[0].BRAM [1:0];
+      openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[3].BRAM [15:14];
+      openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[2].BRAM [13:12];
+      openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[1].BRAM [11:10];
+      openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[0].BRAM [9:8];
+  END_BUS_BLOCK;
+  BUS_BLOCK
+      openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[3].BRAM [7:6];
+      openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[2].BRAM [5:4];
+      openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[1].BRAM [3:2];
+      openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[0].BRAM [1:0];
+      openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[3].BRAM [15:14];
+      openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[2].BRAM [13:12];
+      openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[1].BRAM [11:10];
+      openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[0].BRAM [9:8];
+  END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
+
+// ram_generic: 2x4kB, BRAM_TYPE=RAMB_S4
+ADDRESS_SPACE blockram RAMB16 [0x0200:0x21ff]
+  BUS_BLOCK
+      openMSP430_1/d_ram_lo/BLOCKS[0].RAMB16_S4.B[1].BRAM [7:4];
+      openMSP430_1/d_ram_lo/BLOCKS[0].RAMB16_S4.B[0].BRAM [3:0];
+      openMSP430_1/d_ram_hi/BLOCKS[0].RAMB16_S4.B[1].BRAM [15:12];
+      openMSP430_1/d_ram_hi/BLOCKS[0].RAMB16_S4.B[0].BRAM [11:8];
+  END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+

diff --git a/msp_motion.prj b/msp_motion.prj
new file mode 100644 (file)
index 0000000..cc4dec7
--- /dev/null
+++ b/msp_motion.prj
@@ -0,0 +1,41 @@
+#==============================================================================#
+# OpenMSP430 softcore MCU module                                               #
+#==============================================================================#
+
+verilog work openmsp430/core/omsp_alu.v
+verilog work openmsp430/core/omsp_clock_module.v
+verilog work openmsp430/core/omsp_dbg.v
+verilog work openmsp430/core/omsp_dbg_hwbrk.v
+verilog work openmsp430/core/omsp_dbg_uart.v
+verilog work openmsp430/core/omsp_execution_unit.v
+verilog work openmsp430/core/omsp_frontend.v
+verilog work openmsp430/core/omsp_mem_backbone.v
+verilog work openmsp430/core/omsp_multiplier.v
+verilog work openmsp430/core/omsp_register_file.v
+verilog work openmsp430/core/omsp_sfr.v
+verilog work openmsp430/core/omsp_watchdog.v
+verilog work openmsp430/core/openMSP430.v
+
+verilog work openmsp430/core/openMSP430_undefines.v
+verilog work openmsp430/core/timescale.v
+
+vhdl    work openmsp430/memory/ram_generic.vhd
+
+vhdl    work openmsp430/uart/tx_control.vhd
+vhdl    work openmsp430/uart/tx.vhd
+vhdl    work openmsp430/uart/rx_control.vhd
+vhdl    work openmsp430/uart/rx.vhd
+vhdl    work openmsp430/uart/fifo.vhd
+vhdl    work openmsp430/uart/baud_gen.vhd
+vhdl    work openmsp430/uart/uart.vhd
+
+verilog work openmsp430/top/top_8_32_mul_dbus/openMSP430_defines.v
+vhdl    work openmsp430/top/top_8_32_mul_dbus/openMSP430_8_32_mul_dbus.vhd
+
+
+#==============================================================================#
+# Top-level design file                                                        #
+#==============================================================================#
+
+vhdl    work msp_motion.vhd
+

diff --git a/msp_motion.ucf b/msp_motion.ucf
new file mode 100644 (file)
index 0000000..647d461
--- /dev/null
+++ b/msp_motion.ucf
@@ -0,0 +1,48 @@
+#==============================================================================#
+# Clock & Reset                                                                #
+#==============================================================================#
+# RESET is low active!
+
+NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;
+NET "RESET"             LOC = "B6";
+
+
+#==============================================================================#
+# RS-232 Port                                                                  #
+#==============================================================================#
+
+NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
+NET "RXD"               LOC = "B7";     # input to the board (to FPGA)
+
+
+#==============================================================================#
+# LED outputs                                                                  #
+#==============================================================================#
+# LEDs are connected to the ground
+
+NET "LED0"              LOC = "E10";    # Display2<5>
+NET "LED1"              LOC = "A8";     # Display2<1>
+NET "LED2"              LOC = "E7";     # Display2<3>
+
+
+#==============================================================================#
+# LP_MPW1 BOARD                                                                #
+#==============================================================================#
+# This board with 3-phase power outputs and converters of hall and IRC
+# signals is connected to the J4 header (LVDS TRANSMIT).
+
+NET "PWM0"              LOC = "F4" |    IOSTANDARD = "LVCMOS33";
+NET "PWM0_EN"           LOC = "F3" |    IOSTANDARD = "LVCMOS33";
+NET "PWM1"              LOC = "G4" |    IOSTANDARD = "LVCMOS33";
+NET "PWM1_EN"           LOC = "G3" |    IOSTANDARD = "LVCMOS33";
+NET "PWM2"              LOC = "H4" |    IOSTANDARD = "LVCMOS33";
+NET "PWM2_EN"           LOC = "H3" |    IOSTANDARD = "LVCMOS33";
+
+NET "IRC_INDEX"         LOC = "J4" |    IOSTANDARD = "LVCMOS33";
+NET "IRC_A"             LOC = "J3" |    IOSTANDARD = "LVCMOS33";
+NET "IRC_B"             LOC = "K4" |    IOSTANDARD = "LVCMOS33";
+
+NET "HAL0"              LOC = "J5" |    IOSTANDARD = "LVCMOS33";
+NET "HAL1"              LOC = "K5" |    IOSTANDARD = "LVCMOS33";
+NET "HAL2"              LOC = "K6" |    IOSTANDARD = "LVCMOS33";
+

diff --git a/msp_motion.vhd b/msp_motion.vhd
new file mode 100644 (file)
index 0000000..c5aef7d
--- /dev/null
+++ b/msp_motion.vhd
@@ -0,0 +1,78 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--------------------------------------------------------------------------------
+
+entity msp_motion is
+  port (
+    -- Clock & reset
+    CLK_24MHz : in  std_logic;
+    RESET     : in  std_logic;
+    -- RS232
+    RXD       : in  std_logic;
+    TXD       : out std_logic;
+    -- LED
+    LED0      : out std_logic;
+    LED1      : out std_logic;
+    LED2      : out std_logic;
+    -- PWM
+    PWM0      : out std_logic;
+    PWM0_EN   : out std_logic;
+    PWM1      : out std_logic;
+    PWM1_EN   : out std_logic;
+    PWM2      : out std_logic;
+    PWM2_EN   : out std_logic;
+    -- IRC
+    IRC_INDEX : in  std_logic;
+    IRC_A     : in  std_logic;
+    IRC_B     : in  std_logic;
+    -- HALL
+    HAL0      : in  std_logic;
+    HAL1      : in  std_logic;
+    HAL2      : in  std_logic);
+end msp_motion;
+
+--------------------------------------------------------------------------------
+
+architecture rtl of msp_motion is
+
+  -- OpenMSP430 softcore MCU module
+  signal mclk     : std_logic;
+  signal puc      : std_logic;
+  
+--------------------------------------------------------------------------------
+
+begin
+  
+  ------------------------------------------------------------------------------
+  -- OpenMSP430 softcore MCU module
+  ------------------------------------------------------------------------------
+  openMSP430_1 : entity work.openMSP430_8_32_mul_dbus
+    port map (
+      dco_clk                  => CLK_24MHz,
+      lfxt_clk                 => '0',
+      reset_n                  => RESET,
+      rxd                      => RXD,
+      txd                      => TXD,
+      per_addr                 => open,
+      per_din                  => open,
+      per_dout                 => (others => '0'),
+      per_wen                  => open,
+      per_en                   => open,
+      nmi                      => '0',
+      irq                      => (others => '0'),
+      irq_acc                  => open,
+      aclk_en                  => open,
+      smclk_en                 => open,
+      mclk                     => mclk,
+      puc                      => puc,
+      dmem_addr                => open,
+      dmem_ce                  => open,
+      dmem_we                  => open,
+      dmem_din                 => open,
+      dmem_dout                => (others => '0'));
+  
+end rtl;
+