+#==============================================================================#
+# OpenMSP430 softcore MCU module #
+#==============================================================================#
+
+verilog work openmsp430/core/omsp_alu.v
+verilog work openmsp430/core/omsp_clock_module.v
+verilog work openmsp430/core/omsp_dbg.v
+verilog work openmsp430/core/omsp_dbg_hwbrk.v
+verilog work openmsp430/core/omsp_dbg_uart.v
+verilog work openmsp430/core/omsp_execution_unit.v
+verilog work openmsp430/core/omsp_frontend.v
+verilog work openmsp430/core/omsp_mem_backbone.v
+verilog work openmsp430/core/omsp_multiplier.v
+verilog work openmsp430/core/omsp_register_file.v
+verilog work openmsp430/core/omsp_sfr.v
+verilog work openmsp430/core/omsp_watchdog.v
+verilog work openmsp430/core/openMSP430.v
+
+verilog work openmsp430/core/openMSP430_undefines.v
+verilog work openmsp430/core/timescale.v
+
+vhdl work openmsp430/memory/ram_generic.vhd
+
+vhdl work openmsp430/uart/tx_control.vhd
+vhdl work openmsp430/uart/tx.vhd
+vhdl work openmsp430/uart/rx_control.vhd
+vhdl work openmsp430/uart/rx.vhd
+vhdl work openmsp430/uart/fifo.vhd
+vhdl work openmsp430/uart/baud_gen.vhd
+vhdl work openmsp430/uart/uart.vhd
+
+verilog work openmsp430/top/top_8_32_mul_dbus/openMSP430_defines.v
+vhdl work openmsp430/top/top_8_32_mul_dbus/openMSP430_8_32_mul_dbus.vhd
+
+
+#==============================================================================#
+# Top-level design file #
+#==============================================================================#
+
+vhdl work msp_motion.vhd
+