Now it is not required to do reset after start-up.
architecture behavioral of baud_gen is
architecture behavioral of baud_gen is
- signal counter : std_logic_vector (SCALE_WIDTH-1 downto 0);
- signal clk_baud_s : std_logic;
+ signal counter : std_logic_vector (SCALE_WIDTH-1 downto 0) := (others => '0');
+ signal clk_baud_s : std_logic := '0';
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
full : out std_logic; -- fifo is full
hfull : out std_logic; -- fifo is half full
empty : out std_logic; -- fifo is empty
full : out std_logic; -- fifo is full
hfull : out std_logic; -- fifo is half full
empty : out std_logic; -- fifo is empty
- overflow : out std_logic
+ overflow : out std_logic := '0'
- signal read_addr : mem_addr_t;
- signal write_addr : mem_addr_t;
+ signal read_addr : mem_addr_t := (others => '0');
+ signal write_addr : mem_addr_t := (others => '0');
- signal length : std_logic_vector (width downto 0);
+ signal length : std_logic_vector (width downto 0) := (others => '0');
signal full_s : std_logic;
signal full_s : std_logic;
en : in std_logic;
rx : in std_logic;
ready : out std_logic;
en : in std_logic;
rx : in std_logic;
ready : out std_logic;
- bad_start_bit : out std_logic;
- bad_stop_bit : out std_logic;
+ bad_start_bit : out std_logic := '0';
+ bad_stop_bit : out std_logic := '0';
data : out std_logic_vector (7 downto 0));
end entity receiver;
data : out std_logic_vector (7 downto 0));
end entity receiver;
signal rx_shift_reg : std_logic_vector (9 downto 0);
signal rx_flag : std_logic_vector (9 downto 0);
signal rx_shift_reg : std_logic_vector (9 downto 0);
signal rx_flag : std_logic_vector (9 downto 0);
- signal rx_ready : std_logic;
- signal rx_running : std_logic;
+ signal rx_ready : std_logic := '1';
+ signal rx_running : std_logic := '0';
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--------------------------------------------------------------------------------
bad_start_bit : in std_logic;
bad_stop_bit : in std_logic;
rx_ready : in std_logic;
bad_start_bit : in std_logic;
bad_stop_bit : in std_logic;
rx_ready : in std_logic;
- rx_reset : out std_logic;
- rx_en : out std_logic;
- fifo_we : out std_logic;
- clk_en : out std_logic);
+ rx_reset : out std_logic := '0';
+ rx_en : out std_logic := '0';
+ fifo_we : out std_logic := '0';
+ clk_en : out std_logic := '0');
end entity rx_control;
--------------------------------------------------------------------------------
end entity rx_control;
--------------------------------------------------------------------------------
type state_t is (resetting, waiting, next_frame, receiving);
type state_t is (resetting, waiting, next_frame, receiving);
- signal state : state_t;
+ signal state : state_t := waiting;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behavioral of transmitter is
-- Output shift register (containing also start and stop bit).
architecture behavioral of transmitter is
-- Output shift register (containing also start and stop bit).
- signal tx_shift_reg : std_logic_vector (9 downto 0);
+ signal tx_shift_reg : std_logic_vector (9 downto 0) := "1111111111";
-- Register parallel to the output shift register where '1' shows the last
-- bit of the frame ('1' is in the place of stop bit).
-- Register parallel to the output shift register where '1' shows the last
-- bit of the frame ('1' is in the place of stop bit).
- signal tx_flag : std_logic_vector (9 downto 0);
+ signal tx_flag : std_logic_vector (9 downto 0) := "0000000000";
-- Transmitting of new frame could be started with next clk.
-- Transmitting of new frame could be started with next clk.
- signal tx_ready : std_logic;
+ signal tx_ready : std_logic := '1';
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
type state_t is (waiting, next_frame, transmitting);
type state_t is (waiting, next_frame, transmitting);
- signal state : state_t;
+ signal state : state_t := waiting;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
signal reg_re_b : boolean_vector (512 downto 0);
signal reg_re_b : boolean_vector (512 downto 0);
- signal reg_baud : std_logic_vector (15 downto 0) := "0000000000000010";
+ signal reg_baud : std_logic_vector (15 downto 0) := (others => '0');
signal reg_stat : std_logic_vector (7 downto 0);
signal reg_stat : std_logic_vector (7 downto 0);
- signal reg_ie : std_logic_vector (7 downto 0);
+ signal reg_ie : std_logic_vector (7 downto 0) := (others => '0');
signal tx_clk : std_logic;
signal tx_clk : std_logic;