2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
7 -- Output shift register
9 -- This entity can be used for generating of RS232 like output. Configuration is
10 -- hard wired as 8N1 (8 bits of data, no parity, 1 stop bit).
12 -- All operations (except for 'reset') are synchronous to 'clk' rising edges.
13 -- This clock signal also determines baud rate.
15 -- When 'ready' signal is high, next data vector can be written in by setting
17 --------------------------------------------------------------------------------
23 data : in std_logic_vector (7 downto 0);
25 ready : out std_logic;
30 --------------------------------------------------------------------------------
32 architecture behavioral of transmitter is
34 -- Output shift register (containing also start and stop bit).
35 signal tx_shift_reg : std_logic_vector (9 downto 0);
36 -- Register parallel to the output shift register where '1' shows the last
37 -- bit of the frame ('1' is in the place of stop bit).
38 signal tx_flag : std_logic_vector (9 downto 0);
39 -- Transmitting of new frame could be started with next clk.
40 signal tx_ready : std_logic;
42 --------------------------------------------------------------------------------
49 tx_shift_reg <= "1111111111";
50 tx_flag <= "0000000000";
53 elsif (rising_edge(clk)) then
55 tx_shift_reg <= '1' & data & '0';
56 tx_flag <= "1000000000";
60 tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
61 tx_flag <= '0' & tx_flag(9 downto 1);
63 if (tx_flag(1) = '1') then
71 --------------------------------------------------------------------------------
75 tx <= tx_shift_reg(0);