+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity rx_control is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ rx : in std_logic;
+ bad_start_bit : in std_logic;
+ bad_stop_bit : in std_logic;
+ rx_ready : in std_logic;
+ rx_reset : out std_logic;
+ rx_en : out std_logic;
+ fifo_we : out std_logic;
+ clk_en : out std_logic);
+end entity rx_control;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of rx_control is
+
+ type state_t is (resetting, waiting, next_frame, receiving);
+
+ signal state : state_t;
+
+--------------------------------------------------------------------------------
+
+begin
+
+ process (clk, reset) is
+ begin
+ if reset = '1' then
+ state <= waiting;
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+ elsif clk'event and clk = '1' then
+ case state is
+ when resetting =>
+ state <= waiting;
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+
+ when waiting =>
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '0';
+
+ if rx = '0' then
+ state <= next_frame;
+ rx_en <= '1';
+ clk_en <= '1';
+ end if;
+
+
+ when next_frame =>
+ rx_reset <= '0';
+ rx_en <= '1';
+ fifo_we <= '0';
+ clk_en <= '1';
+
+ if rx_ready = '0' then
+ if bad_start_bit = '1' then
+ state <= resetting;
+ rx_reset <= '1';
+ rx_en <= '0';
+ clk_en <= '0';
+
+ else
+ state <= receiving;
+ rx_en <= '0';
+ end if;
+ end if;
+
+
+ when receiving =>
+ rx_reset <= '0';
+ rx_en <= '0';
+ fifo_we <= '0';
+ clk_en <= '1';
+
+ if rx_ready = '1' then
+ state <= waiting;
+ fifo_we <= '1';
+ clk_en <= '0';
+ end if;
+
+ end case;
+ end if;
+ end process;
+
+end architecture behavioral;
+