Early initialization of all relevant signals.

[fpga/uart.git] / baud_gen.vhd

diff --git a/baud_gen.vhd b/baud_gen.vhd
index 81dfa5cab9fa14f23dbfcbd0bdac363e08888ffb..f3312f0c66cd0df1b75980ecbcc71339dc6ccc8b 100644 (file)
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -47,8 +47,8 @@ end baud_gen;
 
 architecture behavioral of baud_gen is
 
-  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0);
-  signal clk_baud_s : std_logic;
+  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0) := (others => '0');
+  signal clk_baud_s : std_logic := '0';
 
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