Early initialization of all relevant signals.

[fpga/uart.git] / rx_control.vhd

diff --git a/rx_control.vhd b/rx_control.vhd
index ad10c6dd8b074f9b546536e37d428aee3f39dea1..80904fad877aa8be22a985717cf8191dc88c375f 100644 (file)
--- a/rx_control.vhd
+++ b/rx_control.vhd
@@ -11,10 +11,10 @@ entity rx_control is
     bad_start_bit : in  std_logic;
     bad_stop_bit  : in  std_logic;
     rx_ready      : in  std_logic;
-    rx_reset      : out std_logic;
-    rx_en         : out std_logic;
-    fifo_we       : out std_logic;
-    clk_en        : out std_logic);
+    rx_reset      : out std_logic := '0';
+    rx_en         : out std_logic := '0';
+    fifo_we       : out std_logic := '0';
+    clk_en        : out std_logic := '0');
 end entity rx_control;
 
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@@ -23,7 +23,7 @@ architecture behavioral of rx_control is
 
   type state_t is (resetting, waiting, next_frame, receiving);
 
-  signal state : state_t;
+  signal state : state_t := waiting;
 
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