hw/bus_irc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_unsigned.all;
   4 use ieee.numeric_std.all;
   5 use work.lx_rocon_pkg.all;
   6
   7 -- IRC bus interconnect
   8 entity bus_irc is
   9         port
  10         (
  11                 clk_i        : in std_logic;
  12                 reset_i      : in std_logic;
  13                 -- Data bus
  14                 address_i    : in std_logic_vector(4 downto 0);
  15                 ce_i         : in std_logic;
  16                 data_i       : in std_logic_vector(31 downto 0);
  17                 data_o       : out std_logic_vector(31 downto 0);
  18                 --
  19                 bls_i        : in std_logic_vector(3 downto 0);
  20                 -- Signals for IRC
  21                 irc_i        : in IRC_INPUT_Array_Type(7 downto 0)
  22         );
  23 end bus_irc;
  24
  25 architecture Behavioral of bus_irc is
  26
  27         constant num_irc_c          : positive := 8;
  28
  29         signal irc_o_s              : IRC_OUTPUT_Array_Type(num_irc_c-1 downto 0);
  30         signal irc_count_s          : IRC_COUNT_OUTPUT_Array_Type((num_irc_c-1) downto 0);
  31
  32         signal reset_index_event_s  : std_logic_vector(num_irc_c-1 downto 0);
  33         signal reset_index_event2_s : std_logic_vector(num_irc_c-1 downto 0);
  34         signal reset_ab_error_s     : std_logic_vector(num_irc_c-1 downto 0);
  35         signal state_o_s            : std_logic_vector(3 downto 0);
  36         signal state_o_r            : std_logic_vector(3 downto 0);
  37         --
  38         signal irc_en_s             : std_logic;
  39         signal irc_bls_s            : std_logic_vector(3 downto 0);
  40         signal irc_addr_s           : std_logic_vector(3 downto 0);
  41         signal irc_data_s           : std_logic_vector(31 downto 0);
  42         signal irc_out_s            : std_logic;
  43         signal irc_out_r            : std_logic;
  44         --
  45         signal reset_reg_s          : std_logic;
  46         signal reset_reg_r          : std_logic;
  47         signal reset_reg_wr_s       : std_logic;
  48         --
  49         signal reset_s              : std_logic;
  50         signal ce_r                 : std_logic;
  51
  52 begin
  53
  54 irc_generate: for i in 0 to num_irc_c-1 generate
  55         irc : irc_reader
  56                 port map
  57                 (
  58                         clk_i                => clk_i,
  59                         reset_i              => reset_s,
  60                         irc_i                => irc_i(i),
  61                         reset_index_event_i  => reset_index_event_s(i),
  62                         reset_index_event2_i => reset_index_event2_s(i),
  63                         reset_ab_error_i     => reset_ab_error_s(i),
  64                         irc_o                => irc_o_s(i)
  65                 );
  66
  67                 irc_count_s(i) <= irc_o_s(i).count;
  68         end generate;
  69
  70 irc_proc : irc_proc_main
  71         generic map
  72         (
  73                 num_irc_g            => num_irc_c
  74         )
  75         port map
  76         (
  77                 clk_i                => clk_i,
  78                 reset_i              => reset_s,
  79                 -- IRC
  80                 irc_i                => irc_count_s,
  81                 irc_index_reset_o    => reset_index_event_s,
  82                 -- BRAM
  83                 mem_clk_i            => clk_i,
  84                 mem_en_i             => irc_en_s,
  85                 mem_we_i             => irc_bls_s,
  86                 mem_addr_i           => irc_addr_s,
  87                 mem_data_i           => data_i,
  88                 mem_data_o           => irc_data_s
  89         );
  90
  91         reset_s <= reset_reg_r or reset_i;
  92
  93 wire_in:
  94         process(ce_i, ce_r, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
  95         begin
  96
  97                 -- init values
  98                 irc_en_s             <= '0';
  99                 irc_out_s            <= '0';
 100                 irc_bls_s            <= (others => '0');
 101                 irc_addr_s           <= (others => '0');
 102                 reset_ab_error_s     <= (others => '0');
 103                 reset_index_event2_s <= (others => '0');
 104                 state_o_s            <= (others => '0');
 105                 reset_reg_s          <= '0';
 106                 reset_reg_wr_s       <= '0';
 107
 108                 -- Incoming bus request
 109                 if ce_i = '1' then
 110                         -- Mapping:
 111                         -- 0 & axis & irc / index - (all read from bram) (R/W)
 112                         -- 1 & axis & 0           - status register (R/W)
 113                         -- 1 & 000  & 1           - reset
 114                         if address_i(4) = '0' then
 115
 116                                 irc_addr_s    <= address_i(3 downto 0);
 117                                 irc_en_s      <= '1';
 118                                 irc_bls_s     <= bls_i;
 119                                 irc_out_s     <= '1';
 120
 121                         -- Maybe these would be better to latch in ce_i cycle,
 122                         -- and then just pass them
 123                         elsif address_i(0) = '0' then
 124
 125                                 state_o_s(0) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.mark;
 126                                 state_o_s(1) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.ab_error;
 127                                 state_o_s(2) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index_event;
 128                                 state_o_s(3) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index;
 129
 130                                 if bls_i(0) = '1' then
 131                                         if data_i(1) = '1' then
 132                                                 reset_ab_error_s(to_integer(unsigned(address_i(3 downto 1))))     <= '1';
 133                                         end if;
 134                                         if data_i(2) = '1' then
 135                                                 reset_index_event2_s(to_integer(unsigned(address_i(3 downto 1)))) <= '1';
 136                                         end if;
 137                                 end if;
 138                         elsif address_i = "10001" then
 139
 140                                 if bls_i(0) = '1' then
 141                                         reset_reg_s    <= data_i(0);
 142                                         reset_reg_wr_s <= '1';
 143                                 else
 144                                         -- Ugh, hack :-)
 145                                         state_o_s(0)          <= reset_reg_r;
 146                                         state_o_s(3 downto 1) <= (others => '0');
 147                                 end if;
 148
 149                         end if;
 150
 151                 end if;
 152         end process;
 153
 154 wire_out:
 155         process(ce_r, irc_data_s, irc_out_r, state_o_r)
 156         begin
 157
 158                 data_o <= (others => '0');
 159
 160                 if ce_r = '1' then
 161
 162                         if irc_out_r = '1' then
 163                                 data_o <= irc_data_s;
 164                         else
 165                                 data_o(3 downto 0) <= state_o_r;
 166                         end if;
 167
 168                 end if;
 169         end process;
 170
 171 update:
 172         process
 173         begin
 174                 wait until clk_i'event and clk_i= '1';
 175                 ce_r      <= ce_i;
 176                 irc_out_r <= irc_out_s;
 177                 state_o_r <= state_o_s;
 178
 179                 if reset_i = '1' then
 180                         reset_reg_r <= '1';
 181                 elsif reset_reg_wr_s = '1' then
 182                         reset_reg_r <= reset_reg_s;
 183                 end if;
 184
 185         end process;
 186
 187 end Behavioral;
 188