*(pbuf++) = *(ptumbl++);
pxmc_rocon_rx_data_hist_buff = pbuf;
+ } else if (!((pxmc_rocon_rx_data_hist_mode & 0xf8) ^ 0x10)) {
+ uint32_t *pbuf = (uint32_t *)pxmc_rocon_rx_data_hist_buff;
+ volatile pxmcc_data_t *mcc_data = pxmc_rocon_mcc_data();
+ volatile pxmcc_curadc_data_t *curadc;
+ pxmc_rocon_state_t *mcsrc = NULL;
+ int chan = pxmc_rocon_rx_data_hist_mode & 7;
+ if (chan < pxmc_main_list.pxml_cnt)
+ mcsrc = pxmc_state2rocon_state(pxmc_main_list.pxml_arr[chan]);
+ if (mcsrc) {
+ *(pbuf++) = pxmc_rocon_vin_act;
+ *(pbuf++) = fpga_irc[mcsrc->base.pxms_inp_info]->count;
+ *(pbuf++) = mcsrc->base.pxms_ene;
+ chan = mcsrc->base.pxms_out_info;
+ curadc = mcc_data->curadc + chan;
+ *(pbuf++) = *pxmc_rocon_pwm_chan2reg(chan++);
+ *(pbuf++) = (curadc++)->cur_val;
+ *(pbuf++) = *pxmc_rocon_pwm_chan2reg(chan++);
+ *(pbuf++) = (curadc++)->cur_val;
+ *(pbuf++) = *pxmc_rocon_pwm_chan2reg(chan++);
+ *(pbuf++) = (curadc++)->cur_val;
+ *(pbuf++) = *pxmc_rocon_pwm_chan2reg(chan++);
+ *(pbuf++) = (curadc++)->cur_val;
+ pxmc_rocon_rx_data_hist_buff = pbuf;
+ }
}
}