ADC_InitStructure.ADC_NbrOfChannel = ConfigPtr->groupConfigPtr->numberOfChannels;\r
ADC_Init(ADC1, &ADC_InitStructure);\r
\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* ADC307. */\r
ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
//VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
(void) McuMode;\r
\r
- /* NOT SUPPORTED */\r
}\r
\r
//-------------------------------------------------------------------\r
/* Clear all SRAM */\r
init_RAM:\r
LOAD_ADDR_32(11,0x40000000)\r
-#if (CFG_MPC560X)\r
- li r12,384 # loop counter to get all of SRAM;\r
- /* 48k/4 bytes/32 GPRs = 384, only 48k ram for MPC5606s */\r
-#else\r
- li r12,640 # loop counter to get all of SRAM;\r
- /* 80k/4 bytes/32 GPRs = 640 */\r
+#if !defined(SRAM_SIZE)\r
+#error SRAM_SIZE not defined. Add it to board/<board>/build_config.mk\r
#endif\r
+\r
+ LOAD_ADDR_32(r12,SRAM_SIZE/(32*4))\r
mtctr r12\r
\r
init_ram_loop:\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+\r
+/* In order to support multiple hw units we need to match group to a certain hw controller.\r
+ * We handle this in a very simple way i.e. group 0-99 -> hwUnitId 0, group 100-199 -> hwUnitId 1 etc.*\r
+ */\r
+\r
/* ----------------------------[includes]------------------------------------*/\r
\r
#include <assert.h>\r
#error Adc is configured to use Dma but the module is not enabled.\r
#endif\r
\r
-#if defined(CFG_MPC5668)\r
-#define ADC_0 ADC\r
-#endif\r
\r
#if defined(CFG_MPC5668)\r
-#define ADC_EOC_INT ADC_A_EOC\r
-#define ADC_ER_INT ADC_A_ERR\r
-#define ADC_WD_INT ADC_A_WD\r
+#define ADC0_EOC_INT ADC_A_EOC\r
+#define ADC0_ER_INT ADC_A_ERR\r
+#define ADC0_WD_INT ADC_A_WD\r
+#define ADC1_EOC_INT ADC_B_EOC\r
+#define ADC1_ER_INT ADC_B_ERR\r
+#define ADC1_WD_INT ADC_B_WD\r
#endif\r
\r
+#define GET_HW_CONTROLLER(_controller) \\r
+ ((struct ADC_tag *)(0xFFE00000 + 0x4000*(_controller)))\r
\r
+#define GET_HWUNITID_FROM_GROUP(_group) (_group / ADC_NOF_GROUP_PER_CONTROLLER)\r
\r
/* ----------------------------[private macro]-------------------------------*/\r
/* ----------------------------[private typedef]-----------------------------*/\r
\r
/* static variable declarations */\r
static Adc_StateType adcState = ADC_UNINIT;\r
-static const Adc_ConfigType *AdcConfigPtr; /* Pointer to configuration structure. */\r
+static const Adc_ConfigType *AdcGlobalConfigPtr; /* Pointer to configuration structure. */\r
\r
/* ----------------------------[private functions]---------------------------*/\r
\r
/* Function prototypes. */\r
-static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr);\r
-static void Adc_ConfigureADCInterrupts (void);\r
-void Adc_GroupConversionComplete (Adc_GroupType group);\r
+static void Adc_ConfigureADC (const Adc_ConfigType *AdcConfigPtr);\r
+static void Adc_ConfigureADCInterrupts (const Adc_ConfigType *AdcConfigPtr);\r
+void Adc_GroupConversionComplete (Adc_GroupType group, const Adc_ConfigType *AdcConfigPtr, volatile struct ADC_tag *hwPtr);\r
\r
+static const Adc_ConfigType * Adc_GetControllerConfigPtrFromHwUnitId(int unit)\r
+{\r
+ const Adc_ConfigType *AdcConfigPtr = NULL;\r
+\r
+ if(adcState == ADC_INIT){\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ if(unit == AdcGlobalConfigPtr[configId].hwConfigPtr->hwUnitId){\r
+ AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
+ break;\r
+ }\r
+ }\r
+ }\r
\r
+ return AdcConfigPtr;\r
+}\r
+\r
+static const Adc_ConfigType * Adc_GetControllerConfigPtrFromGroupId(Adc_GroupType group)\r
+{\r
+ return Adc_GetControllerConfigPtrFromHwUnitId(GET_HWUNITID_FROM_GROUP(group));\r
+}\r
/* ----------------------------[public functions]----------------------------*/\r
\r
#if (ADC_DEINIT_API == STD_ON)\r
void Adc_DeInit ()\r
{\r
- if (E_OK == Adc_CheckDeInit(adcState, AdcConfigPtr))\r
- {\r
- for(Adc_GroupType group = (Adc_GroupType)ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
- {\r
- /* Set group status to idle. */\r
- AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
- }\r
+ volatile struct ADC_tag *hwPtr;\r
+ boolean okToClear = TRUE;\r
\r
- /* Disable DMA transfer*/\r
-#ifndef CFG_MPC5604B\r
- ADC_0.DMAE.B.DMAEN = 0;\r
-#endif\r
- /* Power down ADC */\r
- ADC_0.MCR.R = 0x0001;\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ const Adc_ConfigType *AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
\r
- /* Disable all interrupt*/\r
- ADC_0.IMR.R = 0;\r
+ if (E_OK == Adc_CheckDeInit(adcState, AdcConfigPtr))\r
+ {\r
+ hwPtr = GET_HW_CONTROLLER(AdcGlobalConfigPtr[configId].hwConfigPtr->hwUnitId);\r
+ for(Adc_GroupType group = (Adc_GroupType)0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Set group status to idle. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+ }\r
\r
- /* Clean internal status. */\r
- AdcConfigPtr = (Adc_ConfigType *)NULL;\r
- adcState = ADC_UNINIT;\r
- }\r
+ /* Disable DMA transfer*/\r
+ #ifndef CFG_MPC5604B\r
+ hwPtr->DMAE.B.DMAEN = 0;\r
+ #endif\r
+ /* Power down ADC */\r
+ hwPtr->MCR.R = 0x0001;\r
+\r
+ /* Disable all interrupt*/\r
+ hwPtr->IMR.R = 0;\r
+ }\r
+ else\r
+ {\r
+ /* Not ok to change adcState if any unit is running */\r
+ okToClear = FALSE;\r
+ }\r
+ }\r
+\r
+ if(okToClear)\r
+ {\r
+ /* Clean internal status. */\r
+ AdcGlobalConfigPtr = (Adc_ConfigType *)NULL;\r
+ adcState = ADC_UNINIT;\r
+ }\r
}\r
#endif\r
\r
{\r
if (E_OK == Adc_CheckInit(adcState, ConfigPtr))\r
{\r
- /* First of all, store the location of the configuration data. */\r
- AdcConfigPtr = ConfigPtr;\r
+ /* First of all, store the location of the global configuration data. */\r
+ AdcGlobalConfigPtr = ConfigPtr;\r
\r
- /* Enable ADC. */\r
- Adc_ConfigureADC(ConfigPtr);\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++)\r
+ {\r
+ const Adc_ConfigType *AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
+\r
+ /* Enable ADC. */\r
+ Adc_ConfigureADC(AdcConfigPtr);\r
\r
- Adc_ConfigureADCInterrupts();\r
+ Adc_ConfigureADCInterrupts(AdcConfigPtr);\r
+ }\r
\r
- /* Move on to INIT state. */\r
- adcState = ADC_INIT;\r
+ /* Move on to INIT state. */\r
+ adcState = ADC_INIT;\r
}\r
}\r
\r
{\r
Std_ReturnType returnValue = E_NOT_OK;\r
\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+\r
/* Check for development errors. */\r
if (E_OK == Adc_CheckSetupResultBuffer (adcState, AdcConfigPtr, group))\r
{\r
- AdcConfigPtr->groupConfigPtr[group].status->resultBufferPtr = bufferPtr;\r
+ AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr = bufferPtr;\r
\r
returnValue = E_OK;\r
}\r
\r
Adc_StreamNumSampleType Adc_GetStreamLastPointer(Adc_GroupType group, Adc_ValueGroupType** PtrToSamplePtr)\r
{\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
Adc_StreamNumSampleType nofSample = 0;\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
\r
/** @req ADC216 */\r
/* Check for development errors. */\r
- if ( (E_OK == Adc_CheckGetStreamLastPointer (adcState, AdcConfigPtr, group)) &&\r
- (groupPtr->status->groupStatus != ADC_BUSY) )\r
+ if (E_OK == Adc_CheckGetStreamLastPointer (adcState, AdcConfigPtr, group))\r
{\r
- /* Set resultPtr to application buffer. */\r
- if(groupPtr->status->currSampleCount > 0){\r
- *PtrToSamplePtr = &groupPtr->status->resultBufferPtr[groupPtr->status->currSampleCount-1];\r
- }\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER];\r
\r
- if ((ADC_CONV_MODE_ONESHOT == groupPtr->conversionMode) &&\r
- (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
+ if (groupPtr->status->groupStatus != ADC_BUSY)\r
{\r
- /** @req ADC327. */\r
- groupPtr->status->groupStatus = ADC_IDLE;\r
- }\r
- else if ((ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
- (ADC_ACCESS_MODE_STREAMING == groupPtr->accessMode) &&\r
- (ADC_STREAM_BUFFER_LINEAR == groupPtr->streamBufferMode) &&\r
- (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
- {\r
- /** @req ADC327. */\r
- groupPtr->status->groupStatus = ADC_IDLE;\r
- }\r
- else if ( (ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
- ((ADC_STREAM_COMPLETED == groupPtr->status->groupStatus) ||\r
- (ADC_COMPLETED == groupPtr->status->groupStatus)) )\r
- {\r
- /* Restart continous mode, and reset result buffer */\r
- if ((ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
- (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
- {\r
- /* Start continous conversion again */\r
- Adc_StartGroupConversion(group);\r
- }\r
- /** @req ADC326 */\r
- /** @req ADC328 */\r
+ /* Set resultPtr to application buffer. */\r
+ if(groupPtr->status->currSampleCount > 0){\r
+ *PtrToSamplePtr = &groupPtr->status->resultBufferPtr[groupPtr->status->currSampleCount-1];\r
+ }\r
+\r
+ if ((ADC_CONV_MODE_ONESHOT == groupPtr->conversionMode) &&\r
+ (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
+ {\r
+ /** @req ADC327. */\r
+ groupPtr->status->groupStatus = ADC_IDLE;\r
+ }\r
+ else if ((ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
+ (ADC_ACCESS_MODE_STREAMING == groupPtr->accessMode) &&\r
+ (ADC_STREAM_BUFFER_LINEAR == groupPtr->streamBufferMode) &&\r
+ (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
+ {\r
+ /** @req ADC327. */\r
+ groupPtr->status->groupStatus = ADC_IDLE;\r
+ }\r
+ else if ( (ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
+ ((ADC_STREAM_COMPLETED == groupPtr->status->groupStatus) ||\r
+ (ADC_COMPLETED == groupPtr->status->groupStatus)) )\r
+ {\r
+ /* Restart continous mode, and reset result buffer */\r
+ if ((ADC_CONV_MODE_CONTINOUS == groupPtr->conversionMode) &&\r
+ (ADC_STREAM_COMPLETED == groupPtr->status->groupStatus))\r
+ {\r
+ /* Start continous conversion again */\r
+ Adc_StartGroupConversion(group);\r
+ }\r
+ /** @req ADC326 */\r
+ /** @req ADC328 */\r
+ }\r
+ else{/* Keep status. */}\r
}\r
- else{/* Keep status. */}\r
+ else\r
+ {\r
+ /* Some condition not met */\r
+ *PtrToSamplePtr = NULL;\r
+ }\r
}\r
else\r
{\r
{\r
Std_ReturnType returnValue = E_OK;\r
uint8_t channel;\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
\r
if (E_OK == Adc_CheckReadGroup (adcState, AdcConfigPtr, group))\r
{\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER];\r
+\r
/* Copy the result to application buffer. */\r
for (channel = 0; channel < groupPtr->numberOfChannels; channel++)\r
{\r
}\r
#endif\r
\r
-void Adc_GroupConversionComplete (Adc_GroupType group)\r
+void Adc_GroupConversionComplete (Adc_GroupType group, const Adc_ConfigType *AdcConfigPtr, volatile struct ADC_tag *hwPtr)\r
{\r
- Adc_GroupDefType *adcGroup = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ Adc_GroupDefType *adcGroup = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER];\r
\r
if(ADC_ACCESS_MODE_SINGLE == adcGroup->accessMode )\r
{\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
/* Call notification if enabled. */\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
Dma_ConfigureDestinationAddress((uint32_t)adcGroup->status->currResultBufPtr, adcGroup->dmaResultChannel);\r
#endif\r
\r
- ADC_0.IMR.B.MSKECH = 1;\r
- ADC_0.MCR.B.NSTART=1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
+ hwPtr->MCR.B.NSTART=1;\r
}\r
else\r
{\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
/* Call notification if enabled. */\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
#endif\r
adcGroup->status->groupStatus = ADC_COMPLETED;\r
\r
- ADC_0.IMR.B.MSKECH = 1;\r
- ADC_0.MCR.B.NSTART=1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
+ hwPtr->MCR.B.NSTART=1;\r
}\r
else\r
{\r
/* Sample completed. */\r
\r
/* Disable trigger normal conversions for ADC*/\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
/* Call notification if enabled. */\r
}\r
}\r
}\r
-void Adc_Group0ConversionComplete (void)\r
+\r
+void Adc_Group0ConversionComplete (int unit)\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(unit);\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromHwUnitId(unit);\r
+\r
/* Clear ECH Flag and disable interruput */\r
- ADC_0.ISR.B.ECH = 1;\r
- ADC_0.IMR.B.MSKECH = 0;\r
+ hwPtr->ISR.B.ECH = 1;\r
+ hwPtr->IMR.B.MSKECH = 0;\r
\r
// Check which group is busy, only one is allowed to be busy at a time in a hw unit\r
- for (int group = 0; group < ADC_NBR_OF_GROUPS; group++)\r
+ for (int group = 0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
if((AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_BUSY) ||\r
(AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_COMPLETED))\r
for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; index++)\r
{\r
#if defined(CFG_MPC5606S)\r
- AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = hwPtr->CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
#else\r
- AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = hwPtr->CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
#endif\r
}\r
#endif\r
\r
- Adc_GroupConversionComplete((Adc_GroupType)group);\r
+ Adc_GroupConversionComplete((Adc_GroupType)group, AdcConfigPtr, hwPtr);\r
break;\r
}\r
}\r
}\r
\r
+static void Adc_Group0ConversionComplete_ADC0(void){\r
+ Adc_Group0ConversionComplete(ADC_CTRL_0);\r
+}\r
+\r
+static void Adc_Group0ConversionComplete_ADC1(void){\r
+ Adc_Group0ConversionComplete(ADC_CTRL_1);\r
+}\r
+\r
void Adc_WatchdogError (void){\r
}\r
void Adc_ADCError (void){\r
}\r
\r
-static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr)\r
+static void Adc_ConfigureADC (const Adc_ConfigType *AdcConfigPtr)\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
/* Set ADC CLOCK */\r
- ADC_0.MCR.B.ADCLKSEL = ConfigPtr->hwConfigPtr->adcPrescale;\r
+ hwPtr->MCR.B.ADCLKSEL = AdcConfigPtr->hwConfigPtr->adcPrescale;\r
\r
- ADC_0.DSDR.B.DSD = 254;\r
+ hwPtr->DSDR.B.DSD = 254;\r
\r
/* Power on ADC */\r
- ADC_0.MCR.B.PWDN = 0;\r
+ hwPtr->MCR.B.PWDN = 0;\r
\r
#if defined(ADC_USES_DMA)\r
/* Enable DMA. */\r
- ADC_0.DMAE.B.DMAEN = 1;\r
+ hwPtr->DMAE.B.DMAEN = 1;\r
#endif\r
}\r
\r
-void Adc_ConfigureADCInterrupts (void)\r
+void Adc_ConfigureADCInterrupts (const Adc_ConfigType *AdcConfigPtr)\r
{\r
- ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC_ER_INT, 2, 0 );\r
- ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete, ADC_EOC_INT, 2, 0 );\r
- ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC_WD_INT, 2, 0 );\r
+ if(AdcConfigPtr->hwConfigPtr->hwUnitId == 0)\r
+ {\r
+ ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC0_ER_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete_ADC0, ADC0_EOC_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC0_WD_INT, 2, 0 );\r
+ }\r
+ else if(AdcConfigPtr->hwConfigPtr->hwUnitId == 1)\r
+ {\r
+ ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC1_ER_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete_ADC1, ADC1_EOC_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC1_WD_INT, 2, 0 );\r
+ }\r
+ else\r
+ {\r
+ assert(0);\r
+ }\r
}\r
\r
#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
void Adc_StartGroupConversion (Adc_GroupType group)\r
{\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
\r
/* Run development error check. */\r
if (E_OK == Adc_CheckStartGroupConversion (adcState, AdcConfigPtr, group))\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER];\r
+\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 0;\r
+ hwPtr->MCR.B.NSTART = 0;\r
\r
/* Set group state to BUSY. */\r
groupPtr->status->groupStatus = ADC_BUSY;\r
if( groupPtr->accessMode == ADC_ACCESS_MODE_STREAMING)\r
{\r
/* Set conversion mode. */\r
- ADC_0.MCR.B.MODE = ADC_CONV_MODE_ONESHOT;\r
+ hwPtr->MCR.B.MODE = ADC_CONV_MODE_ONESHOT;\r
}\r
else\r
{\r
/* Set conversion mode. */\r
- ADC_0.MCR.B.MODE = groupPtr->conversionMode;\r
+ hwPtr->MCR.B.MODE = groupPtr->conversionMode;\r
}\r
\r
/* Enable Overwrite*/\r
- ADC_0.MCR.B.OWREN = 1;\r
+ hwPtr->MCR.B.OWREN = 1;\r
\r
/* Set Conversion Time. */\r
#if defined(CFG_MPC5606S)\r
uint32 groupChannelIdMask = 0;\r
\r
- ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
\r
for(uint8 i =0; i < groupPtr->numberOfChannels; i++)\r
{\r
}\r
\r
#if defined(ADC_USES_DMA)\r
- ADC_0.DMAE.R = 0x01;\r
+ hwPtr->DMAE.R = 0x01;\r
/* Enable DMA Transfer */\r
- ADC_0.DMAR[1].R = groupChannelIdMask;\r
+ hwPtr->DMAR[1].R = groupChannelIdMask;\r
Dma_StartChannel(DMA_ADC_GROUP0_RESULT_CHANNEL); /* Enable EDMA channel for ADC */\r
#endif\r
\r
/* Enable Normal conversion */\r
- ADC_0.NCMR[1].R = groupChannelIdMask;\r
+ hwPtr->NCMR[1].R = groupChannelIdMask;\r
\r
/* Enable Channel Interrupt */\r
- ADC_0.CIMR[1].R = groupChannelIdMask;\r
+ hwPtr->CIMR[1].R = groupChannelIdMask;\r
\r
#else\r
uint32 groupChannelIdMask[3] = {0,0,0};\r
\r
- ADC_0.CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
- ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
- ADC_0.CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+// hwPtr->CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+// hwPtr->CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+// hwPtr->CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
\r
for(uint8 i =0; i < groupPtr->numberOfChannels; i++)\r
{\r
}\r
\r
/* Enable Normal conversion */\r
- ADC_0.NCMR[0].R = groupChannelIdMask[0];\r
- ADC_0.NCMR[1].R = groupChannelIdMask[1];\r
- ADC_0.NCMR[2].R = groupChannelIdMask[2];\r
+ hwPtr->NCMR[0].R = groupChannelIdMask[0];\r
+ hwPtr->NCMR[1].R = groupChannelIdMask[1];\r
+// hwPtr->NCMR[2].R = groupChannelIdMask[2];\r
\r
/* Enable Channel Interrupt */\r
- ADC_0.CIMR[0].R = groupChannelIdMask[0];\r
- ADC_0.CIMR[1].R = groupChannelIdMask[1];\r
- ADC_0.CIMR[2].R = groupChannelIdMask[2];\r
+ hwPtr->CIMR[0].R = groupChannelIdMask[0];\r
+ hwPtr->CIMR[1].R = groupChannelIdMask[1];\r
+// hwPtr->CIMR[2].R = groupChannelIdMask[2];\r
#endif\r
/* Clear interrupts */\r
- ADC_0.ISR.B.ECH = 1;\r
+ hwPtr->ISR.B.ECH = 1;\r
/* Enable ECH interrupt */\r
- ADC_0.IMR.B.MSKECH = 1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
\r
/* Trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 1;\r
+ hwPtr->MCR.B.NSTART = 1;\r
}\r
else\r
{\r
\r
void Adc_StopGroupConversion (Adc_GroupType group)\r
{\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+\r
if (E_OK == Adc_CheckStopGroupConversion (adcState, AdcConfigPtr, group))\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 0;\r
+ hwPtr->MCR.B.NSTART = 0;\r
\r
/* Set group state to IDLE. */\r
- AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+ AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus = ADC_IDLE;\r
\r
/* Disable group notification if enabled. */\r
- if(1 == AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable){\r
+ if(1 == AdcConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->notifictionEnable){\r
Adc_DisableGroupNotification (group);\r
}\r
}\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
void Adc_EnableGroupNotification (Adc_GroupType group)\r
{\r
- Adc_EnableInternalGroupNotification(adcState, AdcConfigPtr, group);\r
+ Adc_EnableInternalGroupNotification(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
\r
void Adc_DisableGroupNotification (Adc_GroupType group)\r
{\r
- Adc_InternalDisableGroupNotification(adcState, AdcConfigPtr, group);\r
+ Adc_InternalDisableGroupNotification(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
#endif\r
\r
Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group)\r
{\r
- return Adc_InternalGetGroupStatus(adcState, AdcConfigPtr, group);\r
+ return Adc_InternalGetGroupStatus(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
\r
}\r
\r
/* Stop all DMA channels connected to EQADC. */\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaCommandChannel);\r
Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaResultChannel);\r
AdcConfigPtr = ConfigPtr;\r
\r
/* Start configuring the eQADC queues. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Loop through all channels and make the command queue. */\r
for (channel = 0; channel < ConfigPtr->groupConfigPtr[group].numberOfChannels; channel++)\r
Adc_EQADCCalibrationSequence ();\r
\r
/* Configure DMA channels. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* ADC307. */\r
ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
}\r
\r
/* Start DMA channels. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Invalidate queues. */\r
EQADC.CFCR[group].B.CFINV = 1;\r
/* Disable time stamp timer. */\r
Adc_WriteEQADCRegister (ADC0_TSCR, 0);\r
\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Enable eDMA requests for commands and results. */\r
EQADC.IDCR[group].B.CFFS = 1;\r
{\r
Adc_GroupType group;\r
ISR_INSTALL_ISR2( "Adc_Err", Adc_EQADCError, EQADC_FISR_OVER, 2, 0);\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
/* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
EQADC.FISR[group].B.RFOF = 1;\r
{\r
Can_Isr(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_Isr( void ) {Can_Isr(CAN_CTRL_C);}\r
void Can_D_Isr( void ) {Can_Isr(CAN_CTRL_D);}\r
void Can_E_Isr( void ) {Can_Isr(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_Isr( void ) {Can_Isr(CAN_CTRL_F);}\r
#endif\r
\r
{\r
Can_Err(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_Err( void ) {Can_Err(CAN_CTRL_C);}\r
void Can_D_Err( void ) {Can_Err(CAN_CTRL_D);}\r
void Can_E_Err( void ) {Can_Err(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_Err( void ) {Can_Err(CAN_CTRL_F);}\r
#endif\r
\r
{\r
Can_BusOff(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_BusOff( void ) {Can_BusOff(CAN_CTRL_C);}\r
void Can_D_BusOff( void ) {Can_BusOff(CAN_CTRL_D);}\r
void Can_E_BusOff( void ) {Can_BusOff(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_BusOff( void ) {Can_BusOff(CAN_CTRL_F);}\r
#endif\r
//-------------------------------------------------------------------\r
ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_1_BUF_32_63, 2, 0 );\r
}\r
break;\r
- #if defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC560XB)\r
case CAN_CTRL_C:\r
if(cfgCtrlPtr->Can_Arc_Flags & CAN_CTRL_BUSOFF_PROCESSING_INTERRUPT){\r
ISR_INSTALL_ISR2( "Can", Can_C_BusOff, FLEXCAN_2_ESR_BOFF_INT, 2, 0);\r
canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;\r
}\r
\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC5604B) || defined(CFG_MPC5668)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC560XB) || defined(CFG_MPC5668)\r
canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority\r
#endif\r
\r
// ( we are reading directly from flash so it makes no sense )\r
memcpy( (void *)Fls_Global.ramAddr, (void *) Fls_Global.flashAddr,\r
Fls_Global.length);\r
+\r
Fls_Global.jobResultType = MEMIF_JOB_OK;\r
Fls_Global.status = MEMIF_IDLE;\r
Fls_Global.jobType = FLS_JOB_NONE;\r
#if !defined(CFG_MPC5604B)\r
GPT_ISR( 6 )\r
GPT_ISR( 7 )\r
+#if !defined(CFG_MPC5606B)\r
GPT_ISR( 8 )\r
#endif\r
#endif\r
+#endif\r
\r
#if defined(CFG_MPC560X)\r
#if defined(CFG_MPC5606S)\r
#define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_3\r
- #elif defined(CFG_MPC5604B)\r
- #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_5\r
+ #elif defined(CFG_MPC5604B)\r
+ #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_5\r
+ #elif defined(CFG_MPC5606B)\r
+ #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_7\r
#endif\r
#else\r
#define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_8\r
#define PIT_INT3 PIT_PITFLG_PIT3\r
#define PIT_INT4 PIT_PITFLG_PIT4\r
#define PIT_INT5 PIT_PITFLG_PIT5\r
+ #define PIT_INT6 PIT_PITFLG_PIT6\r
+ #define PIT_INT7 PIT_PITFLG_PIT7\r
#endif\r
\r
//-------------------------------------------------------------------\r
case 4: ISR_INSTALL_ISR2( "Gpt_4", Gpt_Isr_Channel4, PIT_INT4, 2, 0 ); break;\r
case 5: ISR_INSTALL_ISR2( "Gpt_5", Gpt_Isr_Channel5, PIT_INT5, 2, 0 ); break;\r
#if !defined(CFG_MPC5604B)\r
- case 6: ISR_INSTALL_ISR2( "Gpt_6", Gpt_Isr_Channel6, PIT_PITFLG_PIT6, 2, 0 ); break;\r
- case 7: ISR_INSTALL_ISR2( "Gpt_7", Gpt_Isr_Channel7, PIT_PITFLG_PIT7, 2, 0 ); break;\r
+ case 6: ISR_INSTALL_ISR2( "Gpt_6", Gpt_Isr_Channel6, PIT_INT6, 2, 0 ); break;\r
+ case 7: ISR_INSTALL_ISR2( "Gpt_7", Gpt_Isr_Channel7, PIT_INT7, 2, 0 ); break;\r
+#if !defined(CFG_MPC5606B)\r
case 8: ISR_INSTALL_ISR2( "Gpt_8", Gpt_Isr_Channel8, PIT_PITFLG_PIT8, 2, 0 );break;\r
#endif\r
+#endif\r
#endif\r
default:\r
{\r
\r
#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
\r
- void Gpt_SetMode(Gpt_ModeType mode)\r
- {\r
- int i;\r
+void Gpt_SetMode(Gpt_ModeType mode)\r
+{\r
+ int i;\r
\r
- VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
- VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
+ VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
\r
#if defined(CFG_MPC560X)\r
- if (mode == GPT_MODE_NORMAL)\r
- {\r
- PIT.PITMCR.B.MDIS = 0;\r
- // Do NOT restart channels\r
- }\r
- else if (mode == GPT_MODE_SLEEP)\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ PIT.PITMCR.B.MDIS = 0;\r
+ // Do NOT restart channels\r
+ }\r
+ else if (mode == GPT_MODE_SLEEP)\r
+ {\r
+ PIT.PITMCR.B.MDIS = 0;\r
+ // Disable all but RTI\r
+ for (i= 0; i <= GPT_CHANNEL_PIT_LAST; i++)\r
{\r
- PIT.PITMCR.B.MDIS = 0;\r
- // Disable all but RTI\r
- for (i= 0; i <= GPT_CHANNEL_PIT_LAST; i++)\r
- {\r
- Gpt_StopTimer(i);\r
- }\r
+ Gpt_StopTimer(i);\r
}\r
+ }\r
#else\r
- if (mode == GPT_MODE_NORMAL)\r
- {\r
- PIT.CTRL.B.MDIS = 0;\r
- // Do NOT restart channels\r
- }\r
- else if (mode == GPT_MODE_SLEEP)\r
- {\r
-\r
- PIT.CTRL.B.MDIS = 1;\r
- // Disable all but RTI\r
- for (i= 0; i <= GPT_CHANNEL_PIT_LAST; i++)\r
- {\r
- Gpt_StopTimer(i);\r
- }\r
- }\r
-#endif\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ PIT.CTRL.B.MDIS = 0;\r
+ // Do NOT restart channels\r
}\r
-\r
- void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+ else if (mode == GPT_MODE_SLEEP)\r
{\r
- VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
- VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
- // Only RTI have system wakeup\r
- if (channel == GPT_CHANNEL_RTI)\r
- {\r
- Gpt_Global.wakeupEnabled = STD_OFF;\r
- }\r
- else\r
+\r
+ PIT.CTRL.B.MDIS = 1;\r
+ // Disable all but RTI\r
+ for (i= 0; i <= GPT_CHANNEL_PIT_LAST; i++)\r
{\r
- // TODO:\r
- //assert(0);\r
+ Gpt_StopTimer(i);\r
}\r
}\r
+#endif\r
+}\r
\r
- void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ // Only RTI have system wakeup\r
+ if (channel == GPT_CHANNEL_RTI)\r
{\r
- VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
- VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
- if (channel == GPT_CHANNEL_RTI)\r
- {\r
- Gpt_Global.wakeupEnabled = STD_ON;\r
- }\r
- else\r
- {\r
- // TODO:\r
- //assert(0);\r
- }\r
+ Gpt_Global.wakeupEnabled = STD_OFF;\r
}\r
-\r
- void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+ else\r
{\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
\r
+void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_ON;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
}\r
+}\r
+\r
+void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+{\r
+\r
+}\r
\r
#endif\r
\r
static void LinInterruptTxB(){LinInterruptTx(LIN_CTRL_B);}\r
static void LinInterruptErrB(){LinInterruptErr(LIN_CTRL_B);}\r
\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
static void LinInterruptRxC(){LinInterruptRx(LIN_CTRL_C);}\r
static void LinInterruptTxC(){LinInterruptTx(LIN_CTRL_C);}\r
static void LinInterruptErrC(){LinInterruptErr(LIN_CTRL_C);}\r
static void LinInterruptErrD(){LinInterruptErr(LIN_CTRL_D);}\r
#endif\r
\r
+#if defined (CFG_MPC5606B)\r
+static void LinInterruptRxE(){LinInterruptRx(LIN_CTRL_E);}\r
+static void LinInterruptTxE(){LinInterruptTx(LIN_CTRL_E);}\r
+static void LinInterruptErrE(){LinInterruptErr(LIN_CTRL_E);}\r
+\r
+static void LinInterruptRxF(){LinInterruptRx(LIN_CTRL_F);}\r
+static void LinInterruptTxF(){LinInterruptTx(LIN_CTRL_F);}\r
+static void LinInterruptErrF(){LinInterruptErr(LIN_CTRL_F);}\r
+\r
+static void LinInterruptRxG(){LinInterruptRx(LIN_CTRL_G);}\r
+static void LinInterruptTxG(){LinInterruptTx(LIN_CTRL_G);}\r
+static void LinInterruptErrG(){LinInterruptErr(LIN_CTRL_G);}\r
+\r
+static void LinInterruptRxH(){LinInterruptRx(LIN_CTRL_H);}\r
+static void LinInterruptTxH(){LinInterruptTx(LIN_CTRL_H);}\r
+static void LinInterruptErrH(){LinInterruptErr(LIN_CTRL_H);}\r
+#endif\r
+\r
void Lin_Init( const Lin_ConfigType* Config )\r
{\r
(void)Config;\r
ISR_INSTALL_ISR2("LinIsrTxB", LinInterruptTxB, (IrqType)(LINFLEX_1_TXI),LIN_PRIO, 0);\r
ISR_INSTALL_ISR2("LinIsrErrB", LinInterruptErrB, (IrqType)(LINFLEX_1_ERR),LIN_PRIO, 0);\r
break;\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
case 2:\r
ISR_INSTALL_ISR2("LinIsrRxC", LinInterruptRxC, (IrqType)(LINFLEX_2_RXI),LIN_PRIO, 0);\r
ISR_INSTALL_ISR2("LinIsrTxC", LinInterruptTxC, (IrqType)(LINFLEX_2_TXI),LIN_PRIO, 0);\r
ISR_INSTALL_ISR2("LinIsrErrD", LinInterruptErrD, (IrqType)(LINFLEX_3_ERR),LIN_PRIO, 0);\r
break;\r
#endif\r
+#if defined (CFG_MPC5606B)\r
+ case 4:\r
+ ISR_INSTALL_ISR2("LinIsrRxE", LinInterruptRxE, (IrqType)(LINFLEX_4_RXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrTxE", LinInterruptTxE, (IrqType)(LINFLEX_4_TXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrErrE", LinInterruptErrE, (IrqType)(LINFLEX_4_ERR),LIN_PRIO, 0);\r
+ break;\r
+ case 5:\r
+ ISR_INSTALL_ISR2("LinIsrRxF", LinInterruptRxF, (IrqType)(LINFLEX_5_RXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrTxF", LinInterruptTxF, (IrqType)(LINFLEX_5_TXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrErrF", LinInterruptErrF, (IrqType)(LINFLEX_5_ERR),LIN_PRIO, 0);\r
+ break;\r
+ case 6:\r
+ ISR_INSTALL_ISR2("LinIsrRxG", LinInterruptRxG, (IrqType)(LINFLEX_6_RXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrTxG", LinInterruptTxG, (IrqType)(LINFLEX_6_TXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrErrG", LinInterruptErrG, (IrqType)(LINFLEX_6_ERR),LIN_PRIO, 0);\r
+ break;\r
+ case 7:\r
+ ISR_INSTALL_ISR2("LinIsrRxH", LinInterruptRxH, (IrqType)(LINFLEX_7_RXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrTxH", LinInterruptTxH, (IrqType)(LINFLEX_7_TXI),LIN_PRIO, 0);\r
+ ISR_INSTALL_ISR2("LinIsrErrH", LinInterruptErrH, (IrqType)(LINFLEX_7_ERR),LIN_PRIO, 0);\r
+ break;\r
+#endif\r
+\r
default:\r
break;\r
}\r
union {\r
vuint16_t R;\r
struct {\r
- vuint16_t SRAM_SIZE:5;\r
+ vuint16_t SRAM_SISE:5;\r
vuint16_t PRSZ:5;\r
vuint16_t PVLB:1;\r
vuint16_t DTSZ:4;\r
--- /dev/null
+/**************************************************************************** \r
+ * PROJECT : MPC5606B\r
+ * \r
+ * FILE : MPC5606BC_0.09.h\r
+ * \r
+ * DESCRIPTION : This is the header file describing the register\r
+ * set for MPC5606B\r
+ * \r
+ * COPYRIGHT :(c) 2011, Freescale \r
+ * \r
+ * VERSION : 0.09 \r
+ * DATE : 01.09.2011 \r
+ * AUTHOR : b06320\r
+ * HISTORY : Based Upon Bolero 1.5M; Version 0.06 header file\r
+ * Updated and corrected errors present on MPC5607B_2.1.h\r
+ * \r
+ * \r
+*\r
+* Example instantiation and use: \r
+* \r
+* <MODULE>.<REGISTER>.B.<BIT> = 1; \r
+* <MODULE>.<REGISTER>.R = 0x10000000;\r
+\r
+*****************************************************************************/\r
+\r
+#ifndef _JDP_H_\r
+#define _JDP_H_\r
+\r
+#include "Compiler.h"\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+//#define CUT2\r
+/****************************************************************************/\r
+/* MODULE : ADC0 */\r
+/****************************************************************************/\r
+#include "ip_adc_mpc56xx.h"\r
+\r
+#if 0\r
+struct ADC0_tag {\r
+\r
+ union { /* ADC0 Main Configuration Register (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORTCHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:4; \r
+ vuint32_t PWDN:1; \r
+ } B;\r
+ } MCR; \r
+ \r
+ union { /* ADC0 Main Status Register (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2; \r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR; \r
+ \r
+ vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+ \r
+ union { /* ADC0 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t EOC_CH31:1;\r
+ vuint32_t EOC_CH30:1;\r
+ vuint32_t EOC_CH29:1;\r
+ vuint32_t EOC_CH28:1;\r
+ vuint32_t EOC_CH27:1;\r
+ vuint32_t EOC_CH26:1;\r
+ vuint32_t EOC_CH25:1;\r
+ vuint32_t EOC_CH24:1;\r
+ vuint32_t EOC_CH23:1;\r
+ vuint32_t EOC_CH22:1;\r
+ vuint32_t EOC_CH21:1;\r
+ vuint32_t EOC_CH20:1;\r
+ vuint32_t EOC_CH19:1;\r
+ vuint32_t EOC_CH18:1;\r
+ vuint32_t EOC_CH17:1;\r
+ vuint32_t EOC_CH16:1;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CEOCFR0; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending Register 1 (Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EOC_CH63:1;\r
+ vuint32_t EOC_CH62:1;\r
+ vuint32_t EOC_CH61:1;\r
+ vuint32_t EOC_CH60:1;\r
+ vuint32_t EOC_CH59:1;\r
+ vuint32_t EOC_CH58:1;\r
+ vuint32_t EOC_CH57:1;\r
+ vuint32_t EOC_CH56:1;\r
+ vuint32_t EOC_CH55:1;\r
+ vuint32_t EOC_CH54:1;\r
+ vuint32_t EOC_CH53:1;\r
+ vuint32_t EOC_CH52:1;\r
+ vuint32_t EOC_CH51:1;\r
+ vuint32_t EOC_CH50:1;\r
+ vuint32_t EOC_CH49:1;\r
+ vuint32_t EOC_CH48:1;\r
+ vuint32_t EOC_CH47:1;\r
+ vuint32_t EOC_CH46:1;\r
+ vuint32_t EOC_CH45:1;\r
+ vuint32_t EOC_CH44:1;\r
+ vuint32_t EOC_CH43:1;\r
+ vuint32_t EOC_CH42:1;\r
+ vuint32_t EOC_CH41:1;\r
+ vuint32_t EOC_CH40:1;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CEOCFR1; \r
+ \r
+ union { /* ADC0 Channel Pending 2 (Base+0x001C) */\r
+ vuint32_t R; /* (For external mux'd Channels) */\r
+ struct {\r
+ vuint32_t EOC_CH95:1;\r
+ vuint32_t EOC_CH94:1;\r
+ vuint32_t EOC_CH93:1;\r
+ vuint32_t EOC_CH92:1;\r
+ vuint32_t EOC_CH91:1;\r
+ vuint32_t EOC_CH90:1;\r
+ vuint32_t EOC_CH89:1;\r
+ vuint32_t EOC_CH88:1;\r
+ vuint32_t EOC_CH87:1;\r
+ vuint32_t EOC_CH86:1;\r
+ vuint32_t EOC_CH85:1;\r
+ vuint32_t EOC_CH84:1;\r
+ vuint32_t EOC_CH83:1;\r
+ vuint32_t EOC_CH82:1;\r
+ vuint32_t EOC_CH81:1;\r
+ vuint32_t EOC_CH80:1;\r
+ vuint32_t EOC_CH79:1;\r
+ vuint32_t EOC_CH78:1;\r
+ vuint32_t EOC_CH77:1;\r
+ vuint32_t EOC_CH76:1;\r
+ vuint32_t EOC_CH75:1;\r
+ vuint32_t EOC_CH74:1;\r
+ vuint32_t EOC_CH73:1;\r
+ vuint32_t EOC_CH72:1;\r
+ vuint32_t EOC_CH71:1;\r
+ vuint32_t EOC_CH70:1;\r
+ vuint32_t EOC_CH69:1;\r
+ vuint32_t EOC_CH68:1;\r
+ vuint32_t EOC_CH67:1;\r
+ vuint32_t EOC_CH66:1;\r
+ vuint32_t EOC_CH65:1;\r
+ vuint32_t EOC_CH64:1;\r
+ } B;\r
+ } CE0CFR2; \r
+ \r
+\r
+ union { /* ADC0 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1; \r
+ } B;\r
+ } IMR; \r
+ \r
+\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */ \r
+ struct {\r
+ vuint32_t CIM63:1;\r
+ vuint32_t CIM62:1;\r
+ vuint32_t CIM61:1;\r
+ vuint32_t CIM60:1;\r
+ vuint32_t CIM59:1;\r
+ vuint32_t CIM58:1;\r
+ vuint32_t CIM57:1;\r
+ vuint32_t CIM56:1;\r
+ vuint32_t CIM55:1;\r
+ vuint32_t CIM54:1;\r
+ vuint32_t CIM53:1;\r
+ vuint32_t CIM52:1;\r
+ vuint32_t CIM51:1;\r
+ vuint32_t CIM50:1;\r
+ vuint32_t CIM49:1;\r
+ vuint32_t CIM48:1;\r
+ vuint32_t CIM47:1;\r
+ vuint32_t CIM46:1;\r
+ vuint32_t CIM45:1;\r
+ vuint32_t CIM44:1;\r
+ vuint32_t CIM43:1;\r
+ vuint32_t CIM42:1;\r
+ vuint32_t CIM41:1;\r
+ vuint32_t CIM40:1;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */\r
+ vuint32_t R; /* (For PExternal Mux'd Channels) */ \r
+ struct {\r
+ vuint32_t CIM95:1;\r
+ vuint32_t CIM94:1;\r
+ vuint32_t CIM93:1;\r
+ vuint32_t CIM92:1;\r
+ vuint32_t CIM91:1;\r
+ vuint32_t CIM90:1;\r
+ vuint32_t CIM89:1;\r
+ vuint32_t CIM88:1;\r
+ vuint32_t CIM87:1;\r
+ vuint32_t CIM86:1;\r
+ vuint32_t CIM85:1;\r
+ vuint32_t CIM84:1;\r
+ vuint32_t CIM83:1;\r
+ vuint32_t CIM82:1;\r
+ vuint32_t CIM81:1;\r
+ vuint32_t CIM80:1;\r
+ vuint32_t CIM79:1;\r
+ vuint32_t CIM78:1;\r
+ vuint32_t CIM77:1;\r
+ vuint32_t CIM76:1;\r
+ vuint32_t CIM75:1;\r
+ vuint32_t CIM74:1;\r
+ vuint32_t CIM73:1;\r
+ vuint32_t CIM72:1;\r
+ vuint32_t CIM71:1;\r
+ vuint32_t CIM70:1;\r
+ vuint32_t CIM69:1;\r
+ vuint32_t CIM68:1;\r
+ vuint32_t CIM67:1;\r
+ vuint32_t CIM66:1;\r
+ vuint32_t CIM65:1;\r
+ vuint32_t CIM64:1;\r
+ } B;\r
+ } CIMR2; \r
+\r
+ union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t WDG5H:1; \r
+ vuint32_t WDG5L:1; \r
+ vuint32_t WDG4H:1; \r
+ vuint32_t WDG4L:1; \r
+ vuint32_t WDG3H:1; \r
+ vuint32_t WDG3L:1; \r
+ vuint32_t WDG2H:1; \r
+ vuint32_t WDG2L:1; \r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1; \r
+ vuint32_t WDG0H:1; \r
+ vuint32_t WDG0L:1; \r
+ } B; \r
+ } WTISR; \r
+ \r
+ union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t MSKWDG5H:1; \r
+ vuint32_t MSKWDG5L:1; \r
+ vuint32_t MSKWDG4H:1; \r
+ vuint32_t MSKWDG4L:1;\r
+ vuint32_t MSKWDG3H:1; \r
+ vuint32_t MSKWDG2H:1; \r
+ vuint32_t MSKWDG1H:1; \r
+ vuint32_t MSKWDG0H:1; \r
+ vuint32_t MSKWDG3L:1; \r
+ vuint32_t MSKWDG2L:1; \r
+ vuint32_t MSKWDG1L:1; \r
+ vuint32_t MSKWDG0L:1; \r
+ } B; \r
+ } WTIMR; \r
+\r
+ vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+ \r
+ union { /* ADC0 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE; \r
+ \r
+ union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct { \r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0; \r
+ \r
+ union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */ \r
+ struct {\r
+ vuint32_t DMA63:1;\r
+ vuint32_t DMA62:1;\r
+ vuint32_t DMA61:1;\r
+ vuint32_t DMA60:1;\r
+ vuint32_t DMA59:1;\r
+ vuint32_t DMA58:1;\r
+ vuint32_t DMA57:1;\r
+ vuint32_t DMA56:1;\r
+ vuint32_t DMA55:1;\r
+ vuint32_t DMA54:1;\r
+ vuint32_t DMA53:1;\r
+ vuint32_t DMA52:1;\r
+ vuint32_t DMA51:1;\r
+ vuint32_t DMA50:1;\r
+ vuint32_t DMA49:1;\r
+ vuint32_t DMA48:1;\r
+ vuint32_t DMA47:1;\r
+ vuint32_t DMA46:1;\r
+ vuint32_t DMA45:1;\r
+ vuint32_t DMA44:1;\r
+ vuint32_t DMA43:1;\r
+ vuint32_t DMA42:1;\r
+ vuint32_t DMA41:1;\r
+ vuint32_t DMA40:1;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */\r
+ vuint32_t R; /* (for external mux'd channels) */ \r
+ struct {\r
+ vuint32_t DMA95:1;\r
+ vuint32_t DMA94:1;\r
+ vuint32_t DMA93:1;\r
+ vuint32_t DMA92:1;\r
+ vuint32_t DMA91:1;\r
+ vuint32_t DMA90:1;\r
+ vuint32_t DMA89:1;\r
+ vuint32_t DMA88:1;\r
+ vuint32_t DMA87:1;\r
+ vuint32_t DMA86:1;\r
+ vuint32_t DMA85:1;\r
+ vuint32_t DMA84:1;\r
+ vuint32_t DMA83:1;\r
+ vuint32_t DMA82:1;\r
+ vuint32_t DMA81:1;\r
+ vuint32_t DMA80:1;\r
+ vuint32_t DMA79:1;\r
+ vuint32_t DMA78:1;\r
+ vuint32_t DMA77:1;\r
+ vuint32_t DMA76:1;\r
+ vuint32_t DMA75:1;\r
+ vuint32_t DMA74:1;\r
+ vuint32_t DMA73:1;\r
+ vuint32_t DMA72:1;\r
+ vuint32_t DMA71:1;\r
+ vuint32_t DMA70:1;\r
+ vuint32_t DMA69:1;\r
+ vuint32_t DMA68:1;\r
+ vuint32_t DMA67:1;\r
+ vuint32_t DMA66:1;\r
+ vuint32_t DMA65:1;\r
+ vuint32_t DMA64:1;\r
+ } B;\r
+ } DMAR2; \r
+\r
+ vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */\r
+ \r
+\r
+ /*Note the threshold registers are split [0..3] then [4..5]. For this \r
+ reason thay are NOT implemented as an array in order to maintain \r
+ concistency through all THRHLR registers */ \r
+\r
+ union { /* ADC0 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC0 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC0 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ union { /* ADC0 Threshold 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR3; \r
+ \r
+\r
+ vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */\r
+ \r
+ union { /* ADC0 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1; \r
+ } B;\r
+ } PSCR; \r
+\r
+ \r
+ union { /* ADC0 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t PRES31:1;\r
+ vuint32_t PRES30:1;\r
+ vuint32_t PRES29:1;\r
+ vuint32_t PRES28:1;\r
+ vuint32_t PRES27:1;\r
+ vuint32_t PRES26:1;\r
+ vuint32_t PRES25:1;\r
+ vuint32_t PRES24:1;\r
+ vuint32_t PRES23:1;\r
+ vuint32_t PRES22:1;\r
+ vuint32_t PRES21:1;\r
+ vuint32_t PRES20:1;\r
+ vuint32_t PRES19:1;\r
+ vuint32_t PRES18:1;\r
+ vuint32_t PRES17:1;\r
+ vuint32_t PRES16:1;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0; \r
+ \r
+ union { /* ADC0 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t PRES63:1;\r
+ vuint32_t PRES62:1;\r
+ vuint32_t PRES61:1;\r
+ vuint32_t PRES60:1;\r
+ vuint32_t PRES59:1;\r
+ vuint32_t PRES58:1;\r
+ vuint32_t PRES57:1;\r
+ vuint32_t PRES56:1;\r
+ vuint32_t PRES55:1;\r
+ vuint32_t PRES54:1;\r
+ vuint32_t PRES53:1;\r
+ vuint32_t PRES52:1;\r
+ vuint32_t PRES51:1;\r
+ vuint32_t PRES50:1;\r
+ vuint32_t PRES49:1;\r
+ vuint32_t PRES48:1;\r
+ vuint32_t PRES47:1;\r
+ vuint32_t PRES46:1;\r
+ vuint32_t PRES45:1;\r
+ vuint32_t PRES44:1;\r
+ vuint32_t PRES43:1;\r
+ vuint32_t PRES42:1;\r
+ vuint32_t PRES41:1;\r
+ vuint32_t PRES40:1;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ union { /* ADC0 Presampling 2 (Base+0x008C) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t PRES95:1;\r
+ vuint32_t PRES94:1;\r
+ vuint32_t PRES93:1;\r
+ vuint32_t PRES92:1;\r
+ vuint32_t PRES91:1;\r
+ vuint32_t PRES90:1;\r
+ vuint32_t PRES89:1;\r
+ vuint32_t PRES88:1;\r
+ vuint32_t PRES87:1;\r
+ vuint32_t PRES86:1;\r
+ vuint32_t PRES85:1;\r
+ vuint32_t PRES84:1;\r
+ vuint32_t PRES83:1;\r
+ vuint32_t PRES82:1;\r
+ vuint32_t PRES81:1;\r
+ vuint32_t PRES80:1;\r
+ vuint32_t PRES79:1;\r
+ vuint32_t PRES78:1;\r
+ vuint32_t PRES77:1;\r
+ vuint32_t PRES76:1;\r
+ vuint32_t PRES75:1;\r
+ vuint32_t PRES74:1;\r
+ vuint32_t PRES73:1;\r
+ vuint32_t PRES72:1;\r
+ vuint32_t PRES71:1;\r
+ vuint32_t PRES70:1;\r
+ vuint32_t PRES69:1;\r
+ vuint32_t PRES68:1;\r
+ vuint32_t PRES67:1;\r
+ vuint32_t PRES66:1;\r
+ vuint32_t PRES65:1;\r
+ vuint32_t PRES64:1;\r
+ } B;\r
+ } PSR2; \r
+\r
+ vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */\r
+ \r
+ \r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC0 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC0 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ union { /* ADC0 Conversion Timing 2 (Base+0x009C) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR2; \r
+\r
+ vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */\r
+ \r
+\r
+union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */\r
+ vuint32_t R; /* (For external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } NCMR2; \r
+\r
+vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */\r
+\r
+ \r
+ union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */\r
+ vuint32_t R; /* (external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } JCMR2;\r
+ \r
+ \r
+ vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */\r
+ \r
+ union { /* ADC0 Decode Signals Delay (Base+0x00C4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t DSD:12;\r
+ } B;\r
+ } DSDR; \r
+ \r
+ union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ \r
+ vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */\r
+ \r
+ union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */\r
+ vuint32_t R; /* Note CDR[16..31] and CDR[60..63] are reserved */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:6;\r
+ vuint32_t CDATA:10;\r
+ } B;\r
+ } CDR[96]; \r
+ \r
+ union { /* ADC0 Threshold 4 (Base+0x0280) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR4;\r
+\r
+ union { /* ADC0 Threshold 5 (Base+0x0284) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR5;\r
+ \r
+ vuint8_t ADC0_reserved9[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */\r
+ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH7:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH6:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH5:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH4:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH3:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH2:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH1:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH0:3;\r
+ } B;\r
+ } CWSELR0; \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH15:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH14:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH13:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH12:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH11:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH10:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH9:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH8:3;\r
+ } B;\r
+ } CWSELR1; \r
+ \r
+ vuint8_t ADC0_reserved10[8]; /* Reserved 4 bytes (Base+0x02B8-0x02BF) */ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH39:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH38:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH37:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH36:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH35:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH34:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH33:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH32:3;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH47:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH46:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH45:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH44:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH43:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH42:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH41:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH40:3;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH55:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH54:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH53:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH52:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH51:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH50:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH49:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH48:3;\r
+ } B;\r
+ } CWSELR6;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH63:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH62:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH61:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH60:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH59:3;\r
+ vuint32_t:12;\r
+ } B;\r
+ } CWSELR7;\r
+ \r
+ union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH71:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH70:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH69:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH68:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH67:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH66:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH65:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH64:3;\r
+ } B;\r
+ } CWSELR8;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH79:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH78:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH77:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH76:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH75:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH74:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH73:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH72:3;\r
+ } B;\r
+ } CWSELR9;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH87:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH86:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH85:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH84:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH83:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH82:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH81:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH80:3;\r
+ } B;\r
+ } CWSELR10;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH95:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH94:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH93:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH92:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH91:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH90:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH89:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH88:3;\r
+ } B;\r
+ } CWSELR11;\r
+ \r
+ union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CWEN59:1;\r
+ vuint32_t CWEN58:1;\r
+ vuint32_t CWEN57:1;\r
+ vuint32_t CWEN56:1;\r
+ vuint32_t CWEN55:1;\r
+ vuint32_t CWEN54:1;\r
+ vuint32_t CWEN53:1;\r
+ vuint32_t CWEN52:1;\r
+ vuint32_t CWEN51:1;\r
+ vuint32_t CWEN50:1;\r
+ vuint32_t CWEN49:1;\r
+ vuint32_t CWEN48:1;\r
+ vuint32_t CWEN47:1;\r
+ vuint32_t CWEN46:1;\r
+ vuint32_t CWEN45:1;\r
+ vuint32_t CWEN44:1;\r
+ vuint32_t CWEN43:1;\r
+ vuint32_t CWEN42:1;\r
+ vuint32_t CWEN41:1;\r
+ vuint32_t CWEN40:1;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t CWEN95:1;\r
+ vuint32_t CWEN94:1;\r
+ vuint32_t CWEN93:1;\r
+ vuint32_t CWEN92:1;\r
+ vuint32_t CWEN91:1;\r
+ vuint32_t CWEN90:1;\r
+ vuint32_t CWEN89:1;\r
+ vuint32_t CWEN88:1;\r
+ vuint32_t CWEN87:1;\r
+ vuint32_t CWEN86:1;\r
+ vuint32_t CWEN85:1;\r
+ vuint32_t CWEN84:1;\r
+ vuint32_t CWEN83:1;\r
+ vuint32_t CWEN82:1;\r
+ vuint32_t CWEN81:1;\r
+ vuint32_t CWEN80:1;\r
+ vuint32_t CWEN79:1;\r
+ vuint32_t CWEN78:1;\r
+ vuint32_t CWEN77:1;\r
+ vuint32_t CWEN76:1;\r
+ vuint32_t CWEN75:1;\r
+ vuint32_t CWEN74:1;\r
+ vuint32_t CWEN73:1;\r
+ vuint32_t CWEN72:1;\r
+ vuint32_t CWEN71:1;\r
+ vuint32_t CWEN70:1;\r
+ vuint32_t CWEN69:1;\r
+ vuint32_t CWEN68:1;\r
+ vuint32_t CWEN67:1;\r
+ vuint32_t CWEN66:1;\r
+ vuint32_t CWEN65:1;\r
+ vuint32_t CWEN64:1;\r
+ } B;\r
+ } CWENR2;\r
+\r
+ vuint8_t ADC0_reserved11[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */\r
+ \r
+union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t AWORR_CH59:1;\r
+ vuint32_t AWORR_CH58:1;\r
+ vuint32_t AWORR_CH57:1;\r
+ vuint32_t AWORR_CH56:1;\r
+ vuint32_t AWORR_CH55:1;\r
+ vuint32_t AWORR_CH54:1;\r
+ vuint32_t AWORR_CH53:1;\r
+ vuint32_t AWORR_CH52:1;\r
+ vuint32_t AWORR_CH51:1;\r
+ vuint32_t AWORR_CH50:1;\r
+ vuint32_t AWORR_CH49:1;\r
+ vuint32_t AWORR_CH48:1;\r
+ vuint32_t AWORR_CH47:1;\r
+ vuint32_t AWORR_CH46:1;\r
+ vuint32_t AWORR_CH45:1;\r
+ vuint32_t AWORR_CH44:1;\r
+ vuint32_t AWORR_CH43:1;\r
+ vuint32_t AWORR_CH42:1;\r
+ vuint32_t AWORR_CH41:1;\r
+ vuint32_t AWORR_CH40:1;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AWORR_CH95:1;\r
+ vuint32_t AWORR_CH94:1;\r
+ vuint32_t AWORR_CH93:1;\r
+ vuint32_t AWORR_CH92:1;\r
+ vuint32_t AWORR_CH91:1;\r
+ vuint32_t AWORR_CH90:1;\r
+ vuint32_t AWORR_CH89:1;\r
+ vuint32_t AWORR_CH88:1;\r
+ vuint32_t AWORR_CH87:1;\r
+ vuint32_t AWORR_CH86:1;\r
+ vuint32_t AWORR_CH85:1;\r
+ vuint32_t AWORR_CH84:1;\r
+ vuint32_t AWORR_CH83:1;\r
+ vuint32_t AWORR_CH82:1;\r
+ vuint32_t AWORR_CH81:1;\r
+ vuint32_t AWORR_CH80:1;\r
+ vuint32_t AWORR_CH79:1;\r
+ vuint32_t AWORR_CH78:1;\r
+ vuint32_t AWORR_CH77:1;\r
+ vuint32_t AWORR_CH76:1;\r
+ vuint32_t AWORR_CH75:1;\r
+ vuint32_t AWORR_CH74:1;\r
+ vuint32_t AWORR_CH73:1;\r
+ vuint32_t AWORR_CH72:1;\r
+ vuint32_t AWORR_CH71:1;\r
+ vuint32_t AWORR_CH70:1;\r
+ vuint32_t AWORR_CH69:1;\r
+ vuint32_t AWORR_CH68:1;\r
+ vuint32_t AWORR_CH67:1;\r
+ vuint32_t AWORR_CH66:1;\r
+ vuint32_t AWORR_CH65:1;\r
+ vuint32_t AWORR_CH64:1;\r
+ } B;\r
+ } AWORR2;\r
+\r
+ //vuint8_t ADC0_reserved12[15620]; /* Reserved 15620 bytes (Base+0x02FC-0x3FFF) */ \r
+ \r
+}; /* end of ADC0_tag */ \r
+\r
+/****************************************************************************/\r
+/* MODULE : ADC1 (12 Bit) */\r
+/****************************************************************************/\r
+struct ADC1_tag {\r
+\r
+ union { /* ADC1 Main Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORT_CHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t:2;\r
+ vuint32_t PWDN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* ADC1 Main Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR;\r
+\r
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ union { /* ADC1 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CE0CFR0;\r
+\r
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */\r
+ vuint32_t R; /* (For standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CE0CFR1;\r
+\r
+ vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* ADC1 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1;\r
+ } B;\r
+ } IMR;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t WDG2H:1;\r
+ vuint32_t WDG2L:1;\r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1;\r
+ vuint32_t WDG0H:1;\r
+ vuint32_t WDG0L:1;\r
+ } B;\r
+ } WTISR;\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t MSKWDG2H:1;\r
+ vuint32_t MSKWDG2L:1;\r
+ vuint32_t MSKWDG1H:1;\r
+ vuint32_t MSKWDG1L:1;\r
+ vuint32_t MSKWDG0H:1;\r
+ vuint32_t MSKWDG0L:1;\r
+ } B;\r
+ } WTIMR;\r
+\r
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+\r
+ union { /* ADC1 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE;\r
+\r
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0;\r
+\r
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */\r
+\r
+ /* Note the threshold registers are not implemented as an array for */\r
+ /* concistency with ADC0 header section */\r
+\r
+ union { /* ADC1 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC1 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC1 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */\r
+\r
+ union { /* ADC1 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1;\r
+ } B;\r
+ } PSCR;\r
+\r
+ union { /* ADC1 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0;\r
+\r
+ union { /* ADC1 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */\r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */\r
+\r
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */\r
+\r
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ vuint8_t ADC1_reserved9[12]; /* Reserved 12 bytes (Base+0x00BC-0x00C7) */\r
+ \r
+ union { /* Power Down Exit Delay Register (base+0x00C8)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24; \r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */ \r
+\r
+ union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */\r
+ vuint32_t R; /* Note CDR[16..31] are reserved 0x0140-0x017F */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:4;\r
+ vuint32_t CDATA:12;\r
+ } B;\r
+ } CDR[40];\r
+\r
+ vuint8_t ADC1_reserved11[272]; /* Reserved 252 bytes (Base+0x01A0-0x002AF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH7:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH6:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH5:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH4:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH3:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH2:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH1:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH0:2;\r
+ } B;\r
+ } CWSELR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH15:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH14:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH13:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH12:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH11:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH10:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH9:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH8:2;\r
+ } B;\r
+ } CWSELR1;\r
+\r
+ vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH39:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH38:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH37:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH36:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH35:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH34:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH33:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH32:2;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t WSEL_CH44:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH43:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH42:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH41:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH40:2;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ vuint8_t ADC1_reserved13[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */\r
+\r
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */\r
+\r
+}; /* end of ADC1_tag */ \r
+\r
+#endif //Removed ADC\r
+\r
+/****************************************************************************/\r
+/* MODULE : CANSP */\r
+/****************************************************************************/\r
+ struct CANSP_tag {\r
+ \r
+ union { /* CANSP Control Reg (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RX_COMPLETE:1;\r
+ vuint32_t BUSY:1;\r
+ vuint32_t ACTIVE_CK:1;\r
+ vuint32_t:3;\r
+ vuint32_t MODE:1;\r
+ vuint32_t CAN_RX_SEL:3;\r
+ vuint32_t BRP:5;\r
+ vuint32_t CAN_SMPLR_EN:1;\r
+ } B;\r
+ } CR; \r
+\r
+ union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/\r
+ vuint32_t R;\r
+ } SR[12];\r
+\r
+ }; /* end of CANSP_tag */ \r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+struct ECSM_tag{\r
+\r
+ union { /* ECSM Processor Core Type (Base+0x0000) */\r
+ vuint16_t R;\r
+ } PCT;\r
+\r
+ union { /* ECSM Revision (Base+0x0002) */\r
+ vuint16_t R;\r
+ } REV;\r
+\r
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ } IMC;\r
+\r
+ vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */\r
+\r
+ union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBWCR:1;\r
+ vuint8_t :3;\r
+ vuint8_t PRILVL:4;\r
+ } B;\r
+ } MWCR;\r
+\r
+ vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */\r
+\r
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t FB0AI:1;\r
+ vuint8_t FB0SI:1;\r
+ vuint8_t FB1AI:1;\r
+ vuint8_t FB1SI:1;\r
+ vuint8_t :4;\r
+ } B;\r
+ } MIR;\r
+\r
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */\r
+\r
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/\r
+ vuint32_t R;\r
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */\r
+\r
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */\r
+\r
+ union { /* ECSM ECC Configuration (Base+0x0043) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t ER1BR:1;\r
+ vuint8_t EF1BR:1;\r
+ vuint8_t :2;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR;\r
+\r
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */\r
+\r
+ union { /* ECSM ECC Status (Base+0x0047) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t R1BC:1;\r
+ vuint8_t F1BC:1;\r
+ vuint8_t :2;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */\r
+\r
+ union { /* ECSM ECC Error Generation (Base+0x004A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :2;\r
+ vuint16_t FRC1BI:1;\r
+ vuint16_t FR11BI:1;\r
+ vuint16_t :2;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t :1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR;\r
+\r
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */\r
+\r
+ union { /* ECSM Flash ECC Address(Base+0x0050) */\r
+ vuint32_t R;\r
+ } FEAR;\r
+\r
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */\r
+\r
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR;\r
+\r
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } FEAT;\r
+\r
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */\r
+\r
+ union { /* ECSM Flash ECC Data (Base+0x005C) */\r
+ vuint32_t R;\r
+ } FEDR;\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0060) */\r
+ vuint32_t R;\r
+ } REAR;\r
+\r
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0065) */\r
+ vuint8_t R;\r
+ } RESR;\r
+\r
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR;\r
+\r
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } REAT;\r
+\r
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */\r
+\r
+ union { /* ECSM RAM ECC Data (Base+0x006C) */\r
+ vuint32_t R;\r
+ } REDR;\r
+\r
+}; /* end of ECSM_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : RTC/API */\r
+/****************************************************************************/\r
+struct RTC_tag{\r
+\r
+ union { /* RTC Supervisor Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SUPV:1;\r
+ vuint32_t :31;\r
+ } B;\r
+ } RTCSUPV ;\r
+\r
+ union { /* RTC Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNTEN:1;\r
+ vuint32_t RTCIE:1;\r
+ vuint32_t FRZEN:1;\r
+ vuint32_t ROVREN:1;\r
+ vuint32_t RTCVAL:12;\r
+ vuint32_t APIEN:1;\r
+ vuint32_t APIIE:1;\r
+ vuint32_t CLKSEL:2;\r
+ vuint32_t DIV512EN:1;\r
+ vuint32_t DIV32EN:1;\r
+ vuint32_t APIVAL:10;\r
+ } B;\r
+ } RTCC;\r
+\r
+ union { /* RTC Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t RTCF:1;\r
+ vuint32_t :15;\r
+ vuint32_t APIF:1;\r
+ vuint32_t :2;\r
+ vuint32_t ROVRF:1;\r
+ vuint32_t :10;\r
+ } B;\r
+ } RTCS;\r
+\r
+ union { /* RTC Counter (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RTCCNT:32;\r
+ } B;\r
+ } RTCCNT;\r
+\r
+}; /* end of RTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */\r
+/****************************************************************************/\r
+struct SIU_tag {\r
+\r
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */\r
+\r
+ union { /* MCU ID1 (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t CSP:1;\r
+ vuint32_t PKG:5;\r
+ vuint32_t :2;\r
+ vuint32_t MAJOR_MASK:4;\r
+ vuint32_t MINOR_MASK:4;\r
+ } B;\r
+ } MIDR;\r
+\r
+ union { /* MCU ID2 (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SF:1;\r
+ vuint32_t FLASH_SIZE_1:4;\r
+ vuint32_t FLASH_SIZE_2:4;\r
+ vuint32_t :7;\r
+ vuint32_t PARTNUM:8;\r
+ vuint32_t :3;\r
+ vuint32_t EE:1;\r
+ vuint32_t :3;\r
+ vuint32_t FR:1;\r
+ } B;\r
+ } MIDR2;\r
+\r
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */\r
+\r
+ union { /* Interrupt Status Flag (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EIF23:1;\r
+ vuint32_t EIF22:1;\r
+ vuint32_t EIF21:1;\r
+ vuint32_t EIF20:1;\r
+ vuint32_t EIF19:1;\r
+ vuint32_t EIF18:1;\r
+ vuint32_t EIF17:1;\r
+ vuint32_t EIF16:1;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IRE23:1;\r
+ vuint32_t IRE22:1;\r
+ vuint32_t IRE21:1;\r
+ vuint32_t IRE20:1;\r
+ vuint32_t IRE19:1;\r
+ vuint32_t IRE18:1;\r
+ vuint32_t IRE17:1;\r
+ vuint32_t IRE16:1;\r
+ vuint32_t IRE15:1;\r
+ vuint32_t IRE14:1;\r
+ vuint32_t IRE13:1;\r
+ vuint32_t IRE12:1;\r
+ vuint32_t IRE11:1;\r
+ vuint32_t IRE10:1;\r
+ vuint32_t IRE9:1;\r
+ vuint32_t IRE8:1;\r
+ vuint32_t IRE7:1;\r
+ vuint32_t IRE6:1;\r
+ vuint32_t IRE5:1;\r
+ vuint32_t IRE4:1;\r
+ vuint32_t IRE3:1;\r
+ vuint32_t IRE2:1;\r
+ vuint32_t IRE1:1;\r
+ vuint32_t IRE0:1;\r
+ } B;\r
+ } IRER;\r
+\r
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */\r
+\r
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IREE23:1;\r
+ vuint32_t IREE22:1;\r
+ vuint32_t IREE21:1;\r
+ vuint32_t IREE20:1;\r
+ vuint32_t IREE19:1;\r
+ vuint32_t IREE18:1;\r
+ vuint32_t IREE17:1;\r
+ vuint32_t IREE16:1;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFEE23:1;\r
+ vuint32_t IFEE22:1;\r
+ vuint32_t IFEE21:1;\r
+ vuint32_t IFEE20:1;\r
+ vuint32_t IFEE19:1;\r
+ vuint32_t IFEE18:1;\r
+ vuint32_t IFEE17:1;\r
+ vuint32_t IFEE16:1;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFE23:1;\r
+ vuint32_t IFE22:1;\r
+ vuint32_t IFE21:1;\r
+ vuint32_t IFE20:1;\r
+ vuint32_t IFE19:1;\r
+ vuint32_t IFE18:1;\r
+ vuint32_t IFE17:1;\r
+ vuint32_t IFE16:1;\r
+ vuint32_t IFE15:1;\r
+ vuint32_t IFE14:1;\r
+ vuint32_t IFE13:1;\r
+ vuint32_t IFE12:1;\r
+ vuint32_t IFE11:1;\r
+ vuint32_t IFE10:1;\r
+ vuint32_t IFE9:1;\r
+ vuint32_t IFE8:1;\r
+ vuint32_t IFE7:1;\r
+ vuint32_t IFE6:1;\r
+ vuint32_t IFE5:1;\r
+ vuint32_t IFE4:1;\r
+ vuint32_t IFE3:1;\r
+ vuint32_t IFE2:1;\r
+ vuint32_t IFE1:1;\r
+ vuint32_t IFE0:1;\r
+ } B;\r
+ } IFER;\r
+\r
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */\r
+\r
+ union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SMC:1;\r
+ vuint16_t APC:1;\r
+ vuint16_t:1;\r
+ vuint16_t PA:2;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t:2;\r
+ vuint16_t SRC:1;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[149];\r
+\r
+ vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */\r
+\r
+ union { /* Pad Selection for Mux Input (0x0500-0x53C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t PADSEL:4;\r
+ } B;\r
+ } PSMI[64];\r
+\r
+ vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */\r
+\r
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[152]; // only 152 GPD0 registers \r
+\r
+ vuint8_t SIU_reserved6[360]; /*Reserved 348 Bytes (Base+0x06A4-0x07FF) */\r
+\r
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[152]; // only 152 GPD0 registers \r
+\r
+ vuint8_t SIU_reserved7[872]; /*Reserved 860 Bytes (Base+0x08A4-0x0BFF) */\r
+\r
+ union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPD0:32;\r
+ } B;\r
+ } PGPDO[5];\r
+\r
+ vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */\r
+\r
+ union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPDI:32;\r
+ } B;\r
+ } PGPDI[5];\r
+\r
+ vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */\r
+\r
+ union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MASK:16;\r
+ vuint32_t MPPDO:16;\r
+ } B;\r
+ } MPGPDO[10];\r
+\r
+ vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/\r
+\r
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t MAXCNT:4;\r
+ } B;\r
+ } IFMC[24];\r
+\r
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/\r
+\r
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t IFCP:4;\r
+ } B;\r
+ } IFCPR;\r
+\r
+ vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/\r
+\r
+}; /* end of SIU_tag */\r
+/****************************************************************************/\r
+/* MODULE : SSCM */\r
+/****************************************************************************/\r
+struct SSCM_tag{\r
+\r
+ union { /* Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t NXEN:1;\r
+ vuint16_t:3;\r
+ vuint16_t BMODE:3;\r
+ vuint16_t :1;\r
+ vuint16_t ABD:1;\r
+ vuint16_t:3;\r
+ } B;\r
+ } STATUS;\r
+\r
+ union { /* System Memory Configuration (Base+0x002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t PRSZ:5;\r
+ vuint16_t PVLB:1;\r
+ vuint16_t DTSZ:4;\r
+ vuint16_t DVLD:1;\r
+ } B;\r
+ } MEMCONFIG;\r
+\r
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */\r
+\r
+ union { /* Error Configuration (Base+0x0006) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :14;\r
+ vuint16_t PAE:1;\r
+ vuint16_t RAE:1;\r
+ } B;\r
+ } ERROR;\r
+\r
+ union { /* Debug Status Port (Base+0x0008) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :13;\r
+ vuint16_t DEBUG_MODE:3;\r
+ } B;\r
+ } DEBUGPORT;\r
+\r
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */\r
+\r
+ union { /* Password Comparison High Word (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_HI:32;\r
+ } B;\r
+ } PWCMPH;\r
+\r
+ union { /* Password Comparison Low Word (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_LO:32;\r
+ } B;\r
+ } PWCMPL;\r
+\r
+}; /* end of SSCM_tag */\r
+/****************************************************************************/\r
+/* MODULE : STM */\r
+/****************************************************************************/\r
+ struct STM_CHANNEL_tag{\r
+\r
+ union { /* STM Channel Control 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* STM Channel Interrupt 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR;\r
+\r
+ union { /* STM Channel Compare 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CMP:32;\r
+ } B;\r
+ } CMP;\r
+\r
+ vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */\r
+\r
+ }; /* end of STM_CHANNEL_tag */\r
+\r
+\r
+struct STM_tag{\r
+\r
+ union { /* STM Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t :6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* STM Count (Base+0x0004) */\r
+ vuint32_t R;\r
+ } CNT;\r
+\r
+ vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */\r
+\r
+}; /* end of STM_tag */\r
+/****************************************************************************/\r
+/* MODULE : SWT */\r
+/****************************************************************************/\r
+struct SWT_tag{\r
+\r
+ union { /* SWT Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t :14;\r
+ vuint32_t KEY:1;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WND:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* SWT Interrupt (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR;\r
+\r
+ union { /* SWT Time-Out (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WTO:32;\r
+ } B;\r
+ } TO;\r
+\r
+ union { /* SWT Window (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WST:32;\r
+ } B;\r
+ } WN;\r
+\r
+ union { /* SWT Service (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* SWT Counter Output (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNT:32;\r
+ } B;\r
+ } CO;\r
+\r
+}; /* end of SWT_tag */ \r
+/****************************************************************************/\r
+/* MODULE : WKUP */\r
+/****************************************************************************/\r
+struct WKUP_tag{\r
+\r
+ union { /* NMI Status Flag (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NIF0:1; \r
+ vuint32_t NOVF0:1;\r
+ vuint32_t :30;\r
+ } B;\r
+ } NSR;\r
+\r
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* NMI Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NLOCK0:1;\r
+ vuint32_t NDSS0:2;\r
+ vuint32_t NWRE0:1;\r
+ vuint32_t :1;\r
+ vuint32_t NREE0:1;\r
+ vuint32_t NFEE0:1;\r
+ vuint32_t NFE0:1;\r
+ vuint32_t :24;\r
+ } B;\r
+ } NCR;\r
+\r
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */\r
+\r
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIF:29;\r
+ } B;\r
+ } WISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIRE:29; \r
+ } B;\r
+ } IRER;\r
+\r
+ union { /* Wakeup Request Enable (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t WRE:29;\r
+ } B;\r
+ } WRER;\r
+\r
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */\r
+\r
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IREE:29;\r
+ } B;\r
+ } WIREER;\r
+\r
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFEE:29;\r
+ } B;\r
+ } WIFEER;\r
+\r
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFE:29;\r
+ } B;\r
+ } WIFER;\r
+\r
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IPUE:29;\r
+ } B;\r
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */\r
+\r
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */\r
+\r
+}; /* end of WKUP_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEX */\r
+/****************************************************************************/\r
+struct LINFLEX_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SLFM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1; \r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TO:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t:3; /* for LINflexD no reseve here*/\r
+ vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ \r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ \r
+}; /* end of LINFLEX_tag */\r
+\r
+\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD0 */\r
+/****************************************************************************/\r
+struct LINFLEXD0_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TDFLTFC:3;\r
+ vuint32_t RDFLTFC:3;\r
+ vuint32_t RFBM:1;\r
+ vuint32_t TFBM:1;\r
+ vuint32_t WL1:1;\r
+ vuint32_t PC1:1;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t PC0:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL0:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TO:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ union { /* LINFLEX Global Counter (+0x008C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0090) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0094) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD0_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD1 */\r
+/****************************************************************************/\r
+struct LINFLEXD1_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TDFLTFC:3;\r
+ vuint32_t RDFLTFC:3;\r
+ vuint32_t RFBM:1;\r
+ vuint32_t TFBM:1;\r
+ vuint32_t WL1:1;\r
+ vuint32_t PC1:1;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t PC0:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL0:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+/* No IFCR registers on LinFlexD_1 */\r
+\r
+ union { /* LINFLEX Global Counter (+0x004C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0050) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x005C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD1_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : ME */\r
+/****************************************************************************/\r
+struct ME_tag{\r
+\r
+ union { /* Global Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t S_CURRENTMODE:4;\r
+ vuint32_t S_MTRANS:1;\r
+ vuint32_t S_DC:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_MVR:1;\r
+ vuint32_t S_DFLA:2;\r
+ vuint32_t S_CFLA:2;\r
+ vuint32_t :9;\r
+ vuint32_t S_FMPLL:1;\r
+ vuint32_t S_FXOSC:1;\r
+ vuint32_t S_FIRC:1;\r
+ vuint32_t S_SYSCLK:4;\r
+ } B;\r
+ } GS;\r
+\r
+ union { /* Mode Control (Base+0x004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TARGET_MODE:4;\r
+ vuint32_t :12;\r
+ vuint32_t KEY:16;\r
+ } B;\r
+ } MCTL;\r
+\r
+ union { /* Mode Enable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t :2;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } MER;\r
+\r
+ union { /* Interrupt Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t I_ICONF:1;\r
+ vuint32_t I_IMODE:1;\r
+ vuint32_t I_SAFE:1;\r
+ vuint32_t I_MTC:1;\r
+ } B;\r
+ } IS;\r
+\r
+ union { /* Interrupt Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t M_ICONF:1;\r
+ vuint32_t M_IMODE:1;\r
+ vuint32_t M_SAFE:1;\r
+ vuint32_t M_MTC:1;\r
+ } B;\r
+ } IM;\r
+\r
+ union { /* Invalid Mode Transition Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :27;\r
+ vuint32_t S_MTI:1;\r
+ vuint32_t S_MRI:1;\r
+ vuint32_t S_DMA:1;\r
+ vuint32_t S_NMA:1;\r
+ vuint32_t S_SEA:1;\r
+ } B;\r
+ } IMTS;\r
+\r
+ union { /* Debug Mode Transition Status (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t MPH_BUSY:1;\r
+ vuint32_t :2;\r
+ vuint32_t PMC_PROG:1;\r
+ vuint32_t CORE_DBG:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMR:1;\r
+ vuint32_t :1;\r
+ vuint32_t FMPLL_SC:1;\r
+ vuint32_t FXOSC_SC:1;\r
+ vuint32_t FIRC_SC:1;\r
+ vuint32_t :1;\r
+ vuint32_t SYSCLK_SW:1;\r
+ vuint32_t DFLASH_SC:1;\r
+ vuint32_t CFLASH_SC:1;\r
+ vuint32_t CDP_PRPH_0_143:1;\r
+ vuint32_t :3;\r
+ vuint32_t CDP_PRPH_96_127:1;\r
+ vuint32_t CDP_PRPH_64_95:1;\r
+ vuint32_t CDP_PRPH_32_63:1;\r
+ vuint32_t CDP_PRPH_0_31:1;\r
+ } B;\r
+ } DMTS;\r
+\r
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* Reset Mode Configuration (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RESET;\r
+\r
+ union { /* Test Mode Configuration (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } TEST;\r
+\r
+ union { /* Safe Mode Configuration (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } SAFE;\r
+\r
+ union { /* DRUN Mode Configuration (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSCON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } DRUN;\r
+\r
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RUN[4];\r
+\r
+ union { /* HALT0 Mode Configuration (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } HALT0;\r
+\r
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */\r
+\r
+ union { /* STOP0 Mode Configuration (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STOP0;\r
+\r
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */\r
+\r
+ union { /* STANDBY0 Mode Configuration (Base+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STANDBY0;\r
+\r
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct { /* Peripheral Status 0 (Base+0x0060) */\r
+ vuint32_t :8;\r
+ vuint32_t S_DMA_CH_MUX:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_FLEXCAN5:1;\r
+ vuint32_t S_FLEXCAN4:1;\r
+ vuint32_t S_FLEXCAN3:1;\r
+ vuint32_t S_FLEXCAN2:1;\r
+ vuint32_t S_FLEXCAN1:1;\r
+ vuint32_t S_FLEXCAN0:1;\r
+ vuint32_t :2;\r
+ vuint32_t :1; /* S_LINFLEX9:1; // not present on B1M */\r
+ vuint32_t :1; /* S_LINFLEX8:1; // not present on B1M */\r
+ vuint32_t :2;\r
+ vuint32_t S_DSPI5:1;\r
+ vuint32_t S_DSPI4:1;\r
+ vuint32_t S_DSPI3:1;\r
+ vuint32_t S_DSPI2:1;\r
+ vuint32_t S_DSPI1:1;\r
+ vuint32_t S_DSPI0:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS0;\r
+\r
+ union { /* Peripheral Status 1 (Base+0x0064)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_CANSAMPLER:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_CTUL:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_LINFLEX7:1;\r
+ vuint32_t S_LINFLEX6:1;\r
+ vuint32_t S_LINFLEX5:1;\r
+ vuint32_t S_LINFLEX4:1;\r
+ vuint32_t S_LINFLEX3:1;\r
+ vuint32_t S_LINFLEX2:1;\r
+ vuint32_t S_LINFLEX1:1;\r
+ vuint32_t S_LINFLEX0:1;\r
+ vuint32_t :3;\r
+ vuint32_t S_I2C0:1;\r
+ vuint32_t :10;\r
+ vuint32_t S_ADC1:1;\r
+ vuint32_t S_ADC0:1;\r
+ } B;\r
+ } PS1;\r
+\r
+ union { /* Peripheral Status 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_PIT_RTI:1;\r
+ vuint32_t S_RTC_API:1;\r
+ vuint32_t :16;\r
+ vuint32_t S_EMIOS1:1;\r
+ vuint32_t S_EMIOS0:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_WKPU:1; \r
+ vuint32_t S_SIUL:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS2;\r
+\r
+ union { /* Peripheral Status 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :23;\r
+ vuint32_t S_CMU:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } PS3;\r
+\r
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */\r
+\r
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } RUNPC[8];\r
+\r
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } LPPC[8];\r
+\r
+\r
+ /* Note on PCTL registers: There are only some PCTL implemented in */\r
+ /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */\r
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */\r
+ /* to be careful when addressing these registers in order not to */\r
+ /* access a PCTL that is not implemented. Following are available: */\r
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 51, 50, 49,48, */\r
+ /* 44, 33, 32, 23, 21-16, 13, 12, 9-4 */\r
+\r
+ union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t DBG_F:1;\r
+ vuint8_t LP_CFG:3;\r
+ vuint8_t RUN_CFG:3;\r
+ } B;\r
+ } PCTL[105];\r
+\r
+}; /* end of ME_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CGM */\r
+/****************************************************************************/\r
+struct CGM_tag{\r
+ /*\r
+ The "CGM" has fairly wide coverage and essentially includes everything in\r
+\r
+ chapter 9 of the Bolero Reference Manual:\r
+\r
+ Base Address | Clock Sources\r
+\r
+ ----------------------------- \r
+\r
+ 0xC3FE0000 | FXOSC_CTL\r
+\r
+ 0xC3FE0040 | SXOSC_CTL\r
+\r
+ 0xC3FE0060 | FIRC_CTL\r
+\r
+ 0xC3FE0080 | SIRC_CTL\r
+\r
+ 0xC3FE00A0 | FMPLL\r
+\r
+ 0xC3FE00C0 | CGM Block 1\r
+\r
+ 0xC3FE0100 | CMU \r
+\r
+ 0xC3FE0120 | CGM Block 2\r
+\r
+\r
+\r
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 \r
+\r
+ */\r
+ /* FXOSC - 0xC3FE_0000*/\r
+ union { /* Fast OSC Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } FXOSC_CTL;\r
+\r
+\r
+ /* Reserved Space between end of FXOSC and start SXOSC */\r
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */\r
+\r
+\r
+ /* SXOSC - 0xC3FE_0040*/\r
+ union { /* Slow Osc Control (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t :5;\r
+ vuint32_t S_OSC:1;\r
+ vuint32_t OSCON:1;\r
+ } B;\r
+ } SXOSC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SXOSC and start of FIRC */\r
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */\r
+\r
+\r
+ /* FIRC - 0xC3FE_0060 */\r
+ union { /* Fast IRC Control (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :10;\r
+ vuint32_t RCTRIM:6;\r
+ vuint32_t :3;\r
+ vuint32_t RCDIV:5;\r
+ vuint32_t :2;\r
+ vuint32_t FIRCON_STDBY:1;\r
+ vuint32_t :5;\r
+ } B;\r
+ } FIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of FIRC and start of SIRC */\r
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */\r
+\r
+\r
+ /* SIRC - 0xC3FE_0080 */\r
+ union { /* Slow IRC Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :11;\r
+ vuint32_t SIRCTRIM:5;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCDIV:5;\r
+ vuint32_t :3;\r
+ vuint32_t S_SIRC:1;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCON_STDBY:1;\r
+ } B;\r
+ } SIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SIRC and start of FMPLL */\r
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */\r
+\r
+\r
+ /* FMPLL - 0xC3FE_00A0 */\r
+ union { /* FMPLL Control (Base+0x00A0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t IDF:4;\r
+ vuint32_t ODF:2;\r
+ vuint32_t:1;\r
+ vuint32_t NDIV:7;\r
+ vuint32_t:7;\r
+ vuint32_t EN_PLL_SW:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t UNLOCK_ONCE:1;\r
+ vuint32_t:1;\r
+ vuint32_t I_LOCK:1;\r
+ vuint32_t S_LOCK:1;\r
+ vuint32_t PLL_FAIL_MASK:1;\r
+ vuint32_t PLL_FAIL_FLAG:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } FMPLL_CR;\r
+\r
+ union { /* FMPLL Modulation (Base+0x00A4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STRB_BYPASS:1;\r
+ vuint32_t :1;\r
+ vuint32_t SPRD_SEL:1;\r
+ vuint32_t MOD_PERIOD:13;\r
+ vuint32_t FM_EN:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } FMPLL_MR;\r
+\r
+\r
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */\r
+ vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */\r
+\r
+ /* CMU - 0xC3FE_0100 */\r
+ union { /* CMU Control Status (Base+0x0100) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t SFM:1;\r
+ vuint32_t :13;\r
+ vuint32_t CLKSEL1:2;\r
+ vuint32_t :5;\r
+ vuint32_t RCDIV:2;\r
+ vuint32_t CME_A:1;\r
+ } B;\r
+ } CMU_CSR;\r
+\r
+ union { /* CMU Frequency Display (Base+0x0104) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t FD:20;\r
+ } B;\r
+ } CMU_FDR;\r
+\r
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t HFREF:12;\r
+ } B;\r
+ } CMU_HFREFR;\r
+\r
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t LFREF:12;\r
+ } B;\r
+ } CMU_LFREFR;\r
+\r
+ union { /* CMU Interrupt Status (Base+0x0110) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :29;\r
+ vuint32_t FHHI:1; // *_A not present in RM\r
+ vuint32_t FLLI:1; // *_A not present in RM\r
+ vuint32_t OLRI:1;\r
+ } B;\r
+ } CMU_ISR;\r
+\r
+ /* Reserved space where IMR was previously positioned */\r
+ vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */\r
+\r
+ union { /* CMU Measurement Duration (Base+0x0118) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t MD:20;\r
+ } B;\r
+ } CMU_MDR;\r
+\r
+\r
+ /* Reserved space between end of CMU and start of CGM Block 2 */\r
+ vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */\r
+\r
+ union { /* GCM Output Clock Enable (Base+0x0370) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t EN:1;\r
+ } B;\r
+ } OC_EN;\r
+\r
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t SELDIV:2;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } OCDS_SC;\r
+\r
+ union { /* CGM System Clock Select Status (Base+0x0378) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELSTAT:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } SC_SS;\r
+\r
+ union { /* CGM Sys Clk Div Config 0.2 (0x037C-0x037E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DE:1;\r
+ vuint8_t :3;\r
+ vuint8_t DIV:4;\r
+ } B;\r
+ } SC_DC[3];\r
+ \r
+ union { /* CGM Aux clock select control register (Base+0x0380) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } AC0_SC;\r
+\r
+ // vuint8_t CGM_reserved7[15489]; /*Reserved 1 byte (Base+0x037F - 0x3FFF) */\r
+\r
+}; /* end of CGM_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : RGM base address - 0xC3FE_4000 */\r
+/****************************************************************************/\r
+struct RGM_tag{\r
+\r
+ union { /* Functional Event Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t F_FLASH:1;\r
+ vuint16_t F_LVD45:1;\r
+ vuint16_t F_CMU_FHL:1;\r
+ vuint16_t F_CMU_OLR:1;\r
+ vuint16_t F_FMPLL:1;\r
+ vuint16_t F_CHKSTOP:1;\r
+ vuint16_t F_SOFT:1;\r
+ vuint16_t F_CORE:1;\r
+ vuint16_t F_JTAG:1;\r
+ } B;\r
+ } FES;\r
+\r
+ union { /* Destructive Event Status (Base+0x0002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_POR:1;\r
+ vuint16_t :10;\r
+ vuint16_t F_LVD27_VREG:1;\r
+ vuint16_t F_LVD27:1;\r
+ vuint16_t F_SWT:1;\r
+ vuint16_t F_LVD12_PD1:1;\r
+ vuint16_t F_LVD12_PD0:1;\r
+ } B;\r
+ } DES;\r
+\r
+ union { /* Functional Event Reset Disable (+0x0004) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t D_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t D_FLASH:1;\r
+ vuint16_t D_LVD45:1;\r
+ vuint16_t D_CMU_FHL:1;\r
+ vuint16_t D_CMU_OLR:1;\r
+ vuint16_t D_FMPLL:1;\r
+ vuint16_t D_CHKSTOP:1;\r
+ vuint16_t D_SOFT:1;\r
+ vuint16_t D_CORE:1;\r
+ vuint16_t D_JTAG:1;\r
+ } B;\r
+ } FERD;\r
+\r
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :11;\r
+ vuint16_t D_LVD27_VREG:1;\r
+ vuint16_t D_LVD27:1;\r
+ vuint16_t D_SWT:1;\r
+ vuint16_t D_LVD12_PD1:1;\r
+ vuint16_t D_LVD12_PD0:1;\r
+ } B;\r
+ } DERD;\r
+\r
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */\r
+\r
+ union { /* Functional Event Alt Request (Base+0x0010) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t AR_EXR:1;\r
+ vuint16_t:6;\r
+ vuint16_t AR_FLASH:1;\r
+ vuint16_t AR_LVD45:1;\r
+ vuint16_t AR_CMU_FHL:1;\r
+ vuint16_t AR_CMU_OLR:1;\r
+ vuint16_t AR_FMPLL:1;\r
+ vuint16_t AR_CHKSTOP:1;\r
+ vuint16_t AR_SOFT:1;\r
+ vuint16_t AR_CORE:1;\r
+ vuint16_t AR_JTAG:1;\r
+ } B;\r
+ } FEAR;\r
+ \r
+ union { /* Destructive Event Alt Request (Base+0x0012) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:11;\r
+ vuint16_t AR_LVD27_VREG:1;\r
+ vuint16_t AR_LVD27:1;\r
+ vuint16_t AR_SWT:1;\r
+ vuint16_t AR_LVD12_PD1:1;\r
+ vuint16_t AR_LVD12_PD0:1;\r
+ } B;\r
+ } DEAR; /* Destructive Event Alternate Request */\r
+\r
+ vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */\r
+\r
+ union { /* Functional Event Short Sequence (+0x0018) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SS_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t SS_FLASH:1;\r
+ vuint16_t SS_LVD45:1;\r
+ vuint16_t SS_CMU_FHL:1;\r
+ vuint16_t SS_CMU_OLR:1;\r
+ vuint16_t SS_FMPLL:1;\r
+ vuint16_t SS_CHKSTOP:1;\r
+ vuint16_t SS_SOFT:1;\r
+ vuint16_t SS_CORE:1;\r
+ vuint16_t SS_JTAG:1;\r
+ } B;\r
+ } FESS;\r
+\r
+ union { /* STANDBY reset sequence (Base+0x001A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :8;\r
+ vuint16_t BOOT_FROM_BKP_RAM:1;\r
+ vuint16_t :7;\r
+ } B;\r
+ } STDBY;\r
+\r
+ union { /* Functional Bidirectional Reset En (+0x001C) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t BE_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t BE_FLASH:1;\r
+ vuint16_t BE_LVD45:1;\r
+ vuint16_t BE_CMU_FHL:1;\r
+ vuint16_t BE_CMU_OLR:1;\r
+ vuint16_t BE_FMPLL:1;\r
+ vuint16_t BE_CHKSTOP:1;\r
+ vuint16_t BE_SOFT:1;\r
+ vuint16_t BE_CORE:1;\r
+ vuint16_t BE_JTAG:1;\r
+ } B;\r
+ } FBRE;\r
+\r
+}; /* end of RGM_tag */\r
+/****************************************************************************/\r
+/* MODULE : PCU (base address 0xC3FE_8000) */\r
+/****************************************************************************/\r
+struct PCU_tag{\r
+\r
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RST:1;\r
+ } B;\r
+ } PCONF[4];\r
+\r
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */\r
+\r
+ union { /* PCU Power Domain Status (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t PD3:1;\r
+ vuint32_t PD2:1;\r
+ vuint32_t PD1:1;\r
+ vuint32_t PD0:1;\r
+ } B;\r
+ } PSTAT;\r
+\r
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */\r
+\r
+\r
+ /* Following register is from Voltage Regulators chapter of RM */\r
+\r
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t MASK_LVDHV5:1;\r
+ } B;\r
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */\r
+\r
+ }; /* end of PCU_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CTU Lite(base address - 0xFFE6_4000) */\r
+/****************************************************************************/\r
+struct CTUL_tag{\r
+\r
+ // union { /* CTU Control Status Register (Base+0x0000)NOT PRESENT WITHIN RM*/\r
+ // vuint32_t R;\r
+ // struct {\r
+ // vuint32_t :24;\r
+ // vuint32_t TRGIEN:1;\r
+ // vuint32_t TRGI:1;\r
+ // vuint32_t :6;\r
+ // } B;\r
+ // } CSR;\r
+\r
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */\r
+\r
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TM:1;\r
+ vuint32_t CLR_FLAG:1;\r
+ vuint32_t :5;\r
+ vuint32_t ADC_SEL:1;\r
+ vuint32_t :1;\r
+ vuint32_t CHANNEL_VALUE:7;\r
+ } B;\r
+ } EVTCFGR[64];\r
+\r
+\r
+}; /* end of CTUL_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */\r
+/****************************************************************************/\r
+\r
+struct EMIOS_CHANNEL_tag{\r
+\r
+ union { /* Channel A Data (UCn Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t A:16;\r
+ } B;\r
+ } CADR;\r
+\r
+ union { /* Channel B Data (UCn Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t B:16;\r
+ } B;\r
+ } CBDR;\r
+\r
+ union { /* Channel Counter (UCn Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t C:16;\r
+ } B;\r
+ } CCNTR;\r
+\r
+ union { /* Channel Control (UCn Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPEN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t :1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t :3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t :1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* Channel Status (UCn Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t :15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t :12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR;\r
+\r
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ALTA:16;\r
+ } B;\r
+ } ALTCADR;\r
+\r
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */\r
+\r
+}; /* end of EMIOS_CHANNEL_tag */\r
+\r
+\r
+struct EMIOS_tag{\r
+\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t :1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t :10;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t :8;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Global Flag (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t F31:1;\r
+ vuint32_t F30:1;\r
+ vuint32_t F29:1;\r
+ vuint32_t F28:1;\r
+ vuint32_t F27:1;\r
+ vuint32_t F26:1;\r
+ vuint32_t F25:1;\r
+ vuint32_t F24:1;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR;\r
+\r
+ union { /* Output Update Disable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OU31:1;\r
+ vuint32_t OU30:1;\r
+ vuint32_t OU29:1;\r
+ vuint32_t OU28:1;\r
+ vuint32_t OU27:1;\r
+ vuint32_t OU26:1;\r
+ vuint32_t OU25:1;\r
+ vuint32_t OU24:1;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR;\r
+\r
+ union { /* Disable Channel (Base+0x000F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CHDIS31:1;\r
+ vuint32_t CHDIS30:1;\r
+ vuint32_t CHDIS29:1;\r
+ vuint32_t CHDIS28:1;\r
+ vuint32_t CHDIS27:1;\r
+ vuint32_t CHDIS26:1;\r
+ vuint32_t CHDIS25:1;\r
+ vuint32_t CHDIS24:1;\r
+ vuint32_t CHDIS23:1;\r
+ vuint32_t CHDIS22:1;\r
+ vuint32_t CHDIS21:1;\r
+ vuint32_t CHDIS20:1;\r
+ vuint32_t CHDIS19:1;\r
+ vuint32_t CHDIS18:1;\r
+ vuint32_t CHDIS17:1;\r
+ vuint32_t CHDIS16:1;\r
+ vuint32_t CHDIS15:1;\r
+ vuint32_t CHDIS14:1;\r
+ vuint32_t CHDIS13:1;\r
+ vuint32_t CHDIS12:1;\r
+ vuint32_t CHDIS11:1;\r
+ vuint32_t CHDIS10:1;\r
+ vuint32_t CHDIS9:1;\r
+ vuint32_t CHDIS8:1;\r
+ vuint32_t CHDIS7:1;\r
+ vuint32_t CHDIS6:1;\r
+ vuint32_t CHDIS5:1;\r
+ vuint32_t CHDIS4:1;\r
+ vuint32_t CHDIS3:1;\r
+ vuint32_t CHDIS2:1;\r
+ vuint32_t CHDIS1:1;\r
+ vuint32_t CHDIS0:1;\r
+ } B;\r
+ } UCDIS;\r
+\r
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */\r
+\r
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */\r
+\r
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */\r
+\r
+}; /* end of EMIOS_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : PIT (base address - 0xC3FF_FFFF) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+\r
+ union { /* PIT Module Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */\r
+\r
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */\r
+ struct {\r
+\r
+ union { /* PIT Timer Load Value (Offset+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } LDVAL;\r
+\r
+ union { /* PIT Current Timer Value (Offset+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } CVAL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG;\r
+\r
+ }CH[8]; /* End of PIT Timer Channels */\r
+\r
+}; /* end of PIT_tag */\r
+/****************************************************************************/\r
+/* MODULE : I2C (base address - 0xFFE3_0000) */\r
+/****************************************************************************/\r
+struct I2C_tag{\r
+\r
+ union { /* I2C Bus Address (Base+0x0000) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ADR:7;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBAD;\r
+\r
+ union { /* I2C Bus Frequency Divider (Base+0x0001) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t IBC:8;\r
+ } B;\r
+ } IBFD;\r
+\r
+ union { /* I2C Bus Control (Base+0x0002) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t MDIS:1;\r
+ vuint8_t IBIE:1;\r
+ vuint8_t MS:1; /*different from RM for backward compatiblity MSSL in RM*/ \r
+ vuint8_t TX:1;\r
+ vuint8_t NOACK:1;\r
+ vuint8_t RSTA:1;\r
+ vuint8_t DMAEN:1;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBCR;\r
+\r
+ union { /* I2C Bus Status (Base+0x0003) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t TCF:1;\r
+ vuint8_t IAAS:1;\r
+ vuint8_t IBB:1;\r
+ vuint8_t IBAL:1;\r
+ vuint8_t :1;\r
+ vuint8_t SRW:1;\r
+ vuint8_t IBIF:1;\r
+ vuint8_t RXAK:1;\r
+ } B;\r
+ } IBSR;\r
+\r
+ union { /* I2C Bus Data I/O (Base+0x0004) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DATA:8;\r
+ } B;\r
+ } IBDR;\r
+\r
+ union { /* I2C Interrupt Configuration (Base+0x0005) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t BIIE:1;\r
+ vuint8_t :7;\r
+ } B;\r
+ } IBIC;\r
+\r
+ vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */\r
+\r
+}; /* end of i2c_tag */\r
+/****************************************************************************/\r
+/* MODULE : MPU (base address - 0xFFF1_0000) */\r
+/****************************************************************************/\r
+ struct MPU_tag {\r
+\r
+ union { /* Control/Error Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t SPERR:3;\r
+ vuint32_t:4;\r
+ vuint32_t HRL:4;\r
+ vuint32_t NSP:4;\r
+ vuint32_t NGRD:4;\r
+ vuint32_t :7;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } CESR;\r
+\r
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */\r
+\r
+\r
+ union { /* Error Address Slave Port0 (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR0;\r
+\r
+ union { /* Error Detail Slave Port0 (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR0;\r
+\r
+\r
+ union { /* Error Address Slave Port1 (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR1;\r
+\r
+ union { /* Error Detail Slave Port1 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR1;\r
+\r
+\r
+ union { /* Error Address Slave Port2 (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR2;\r
+\r
+ union { /* Error Detail Slave Port2 (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR2;\r
+\r
+ vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */\r
+\r
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */\r
+\r
+ union { /* - Word 0 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SRTADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD0;\r
+\r
+ union { /* - Word 1 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENDADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD1;\r
+\r
+ union { /* - Word 2 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } WORD2;\r
+\r
+ union { /* - Word 3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PID:8;\r
+ vuint32_t PIDMASK:8;\r
+ vuint32_t :15;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } WORD3;\r
+\r
+ }RGD[8]; /* End of Region Descriptor Structure) */\r
+\r
+ vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */\r
+\r
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } RGDAAC[8];\r
+\r
+ vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */\r
+\r
+}; /* end of MPU_tag */\r
+/****************************************************************************/\r
+/* MODULE : eDMA (base address - 0xFFF4_4000) */\r
+/****************************************************************************/\r
+\r
+ /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */\r
+ struct EDMA_TCD_STD_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_STD_tag */\r
+\r
+ /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/\r
+ struct EDMA_TCD_CHLINK_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (?major?) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_CHLINK_tag */\r
+\r
+\r
+\r
+struct EDMA_tag {\r
+\r
+ union { /* Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t CX:1;\r
+ vuint32_t ECX:1;\r
+ vuint32_t :6; \r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t EMLM:1;\r
+ vuint32_t CLM:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t HOE:1;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* Error Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t :16;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/\r
+\r
+ union { /* Enable Request Low Ch15..0 (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL;\r
+\r
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/\r
+\r
+ union { /* Enable Error Interrupt Low (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL;\r
+\r
+ union { /* DMA Set Enable Request (Base+0x0018) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SERQ:7;\r
+ } B;\r
+ } SERQR;\r
+\r
+ union { /* DMA Clear Enable Request (Base+0x0019) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERQ:7;\r
+ } B;\r
+ } CERQR;\r
+\r
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SEEI:7;\r
+ } B;\r
+ } SEEIR;\r
+\r
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:1;\r
+ vuint8_t CEEI:7;\r
+ } B;\r
+ } CEEIR;\r
+\r
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CINT:7;\r
+ } B;\r
+ } CIRQR;\r
+\r
+ union { /* DMA Clear error (Base+0x001D) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERR:7;\r
+ } B;\r
+ } CER;\r
+\r
+ union { /* DMA Set Start Bit (Base+0x001E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t NOP:1;\r
+ vuint8_t SSB:7;\r
+ } B;\r
+ } SSBR;\r
+\r
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CDSB:7;\r
+ } B;\r
+ } CDSBR;\r
+\r
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/\r
+\r
+ union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL;\r
+\r
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/\r
+\r
+ union { /* DMA Error Low Ch15..0 (Base+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL;\r
+\r
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/\r
+\r
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t HRS15:1;\r
+ vuint32_t HRS14:1;\r
+ vuint32_t HRS13:1;\r
+ vuint32_t HRS12:1;\r
+ vuint32_t HRS11:1;\r
+ vuint32_t HRS10:1;\r
+ vuint32_t HRS09:1;\r
+ vuint32_t HRS08:1;\r
+ vuint32_t HRS07:1;\r
+ vuint32_t HRS06:1;\r
+ vuint32_t HRS05:1;\r
+ vuint32_t HRS04:1;\r
+ vuint32_t HRS03:1;\r
+ vuint32_t HRS02:1;\r
+ vuint32_t HRS01:1;\r
+ vuint32_t HRS00:1;\r
+ } B;\r
+ } HRSL;\r
+\r
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/\r
+\r
+ union { /* Channel n Priority (Base+0x0100-0x010F)*/\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+ vuint8_t DPA:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+ } B;\r
+ } CPR[16];\r
+\r
+ vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */\r
+\r
+ /* Transfer Control Descriptors 0..16 (Base+0x1000-0x11E0) */\r
+ struct EDMA_TCD_STD_tag TCD[16];\r
+ \r
+ /* or change to following if using channel linking */\r
+ /* Struct EDMA_TCD_CHLINK_tag TCD[16]; */\r
+ \r
+ vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */\r
+\r
+}; /* end of EDMA_tag */\r
+/*************************************************************************/\r
+/* MODULE : INTC (base address - 0xFFF4_8000) */\r
+/*************************************************************************/\r
+struct INTC_tag {\r
+\r
+ union { /* INTC Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* INTC Current Priority (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR;\r
+ \r
+ vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* INTC Interrupt Acknowledge (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC0:21;\r
+ vuint32_t INTVEC_PRC0:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR;\r
+\r
+ vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */\r
+ \r
+ union { /* INTC End Of Interrupt (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR;\r
+\r
+ vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */\r
+ \r
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8];\r
+\r
+ vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */\r
+\r
+ union { /* INTC Priority Select (Base+0x0040-0x0128) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[234]; \r
+\r
+}; /* end of INTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+#include "ip_dspi.h"\r
+\r
+#if 0\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/* Base Addresses: */\r
+/* DSPI_0 - 0xFFF9_0000 */\r
+/* DSPI_1 - 0xFFF9_4000 */\r
+/* DSPI_2 - 0xFFF9_8000 */\r
+/* DSPI_3 - 0xFFF9_C000 */\r
+/* DSPI_4 - 0xFFFA_0000 */\r
+/* DSPI_5 - 0xFFFA_4000 */\r
+/****************************************************************************/\r
+struct DSPI_tag{\r
+\r
+ union { /* DSPI Module Configuraiton (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t :2; \r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1; \r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t :7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* DSPI Transfer Count (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[6];\r
+\r
+ vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */\r
+\r
+ union { /* DSPI Status (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t :1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t :5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t :2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t :4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t :16;\r
+ } B;\r
+ } RSER;\r
+\r
+ union { /* DSPI Push TX FIFO (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t :4; \r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR;\r
+\r
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } POPR;\r
+\r
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t TXCMD:16; \r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4];\r
+\r
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */\r
+\r
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } RXFR[4];\r
+ }; /* end of DSPI_tag */\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+#include "ip_flexcan.h"\r
+\r
+#if 0\r
+ /****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/* Base Addresses: */\r
+/* FlexCAN_0 - 0xFFFC_0000 */\r
+/* FlexCAN_1 - 0xFFFC_4000 */\r
+/* FlexCAN_2 - 0xFFFC_8000 */\r
+/* FlexCAN_3 - 0xFFFC_C000 */\r
+/* FlexCAN_4 - 0xFFFD_0000 */\r
+/* FlexCAN_5 - 0xFFFD_4000 */\r
+/****************************************************************************/\r
+struct FLEXCAN_BUF_t{\r
+\r
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t :1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRIO:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+}; /* end of FLEXCAN_BUF_t */\r
+\r
+\r
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */\r
+\r
+ union { /* RxFIFO Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :9;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* RxFIFO Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/\r
+\r
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */\r
+ vuint32_t R;\r
+ } IDTABLE[8];\r
+\r
+}; /* end of FLEXCAN_RXFIFO_t */\r
+\r
+\r
+struct FLEXCAN_tag{\r
+\r
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t WAKMSK:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t SUPV:1;\r
+ vuint32_t SLFWAK:1; /*not present in RM*/\r
+ vuint32_t WRNEN:1;\r
+ vuint32_t LPMACK:1;\r
+ vuint32_t WAKSRC:1;\r
+ vuint32_t DOZE:1; /*not present in RM*/\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t BCC:1;\r
+ vuint32_t:2;\r
+ vuint32_t LPRIO_EN:1;\r
+ vuint32_t AEN:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDAM:2;\r
+ vuint32_t:2;\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* FLEXCAN Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TIMER:16;\r
+ } B;\r
+ } TIMER;\r
+\r
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXGMASK;\r
+\r
+ /* --- Following 2 registers are included for legacy purposes only --- */\r
+\r
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX14MASK;\r
+\r
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX15MASK;\r
+\r
+ /* --- */\r
+\r
+ union { /* FLEXCAN Error Counter (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR;\r
+\r
+ union { /* FLEXCAN Error & Status (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t :1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t :1;\r
+ } B;\r
+ } ESR;\r
+\r
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH;\r
+\r
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL;\r
+\r
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH;\r
+\r
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/\r
+\r
+/****************************************************************************/\r
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */\r
+/****************************************************************************/\r
+ /* Standard Buffer Structure */\r
+ struct FLEXCAN_BUF_t BUF[64];\r
+\r
+ /* RX FIFO and Buffer Structure */\r
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */\r
+ /*struct FLEXCAN_BUF_t BUF[56]; */\r
+/****************************************************************************/\r
+\r
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/\r
+\r
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXIMR[64];\r
+\r
+}; /* end of FLEXCAN_tag */\r
+\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : DMAMUX (base address - 0xFFFD_C000) */\r
+/****************************************************************************/\r
+ struct DMAMUX_tag {\r
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBL:1;\r
+ vuint8_t TRIG:1;\r
+ vuint8_t SOURCE:6;\r
+ } B;\r
+ } CHCONFIG[16]; \r
+\r
+ }; /* end of DMAMUX_tag */\r
+/****************************************************************************/\r
+/* MODULE : DFLASH (base address - 0x0080_0000) */\r
+/****************************************************************************/\r
+ struct DFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address block locking (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :25;\r
+ vuint32_t HBLOCK:6;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address space block sel (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t HSL:6;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ vuint8_t DFLASH_reserved0[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+\r
+ }; /* end of Dflash_tag */\r
+/****************************************************************************/\r
+/* MODULE : CFLASH (base address - 0xC3F8_8000) */\r
+/****************************************************************************/\r
+ struct CFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address space block locking (Base+0x0008)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :19;\r
+ vuint32_t HBLOCK:12;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address Space block select (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t HSL:12;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */\r
+ /* the code flash configuraiton PFCR[0..2] registers */\r
+ /* To make it easier to code, the BIU registers have been */\r
+ /* replaced with the PFCR registers in this header file! */\r
+ /* A commented out BIU register is shown for reference! */\r
+\r
+\r
+ union { /* CFLASH Configuration 0 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK0_APC:5;\r
+ vuint32_t BK0_WWSC:5;\r
+ vuint32_t BK0_RWSC:5;\r
+ vuint32_t BK0_RWWC2:1;\r
+ vuint32_t BK0_RWWC1:1;\r
+ /* vuint32_t B0_P1_BCFG:2; // only has one port to the cross bar i.e. port 0 \r
+ vuint32_t B0_P1_DPFE:1;\r
+ vuint32_t B0_P1_IPFE:1;\r
+ vuint32_t B0_P1_PFLM:2;\r
+ vuint32_t B0_P1_BFE:1; */\r
+ vuint32_t :7;\r
+ vuint32_t BK0_RWWC0:1;\r
+ vuint32_t B0_P0_BCFG:2;\r
+ vuint32_t B0_P0_DPFE:1;\r
+ vuint32_t B0_P0_IPFE:1;\r
+ vuint32_t B0_P0_PFLM:2;\r
+ vuint32_t B0_P0_BFE:1;\r
+ } B;\r
+ } PFCR0;\r
+ \r
+/* Commented out Bus Interface Unit 0 (Base+0x001C) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI0:32;\r
+ } B;\r
+ } BIU0; */\r
+\r
+ union { /* CFLASH Configuration Register 1 (Base+0x0020)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK1_APC:5;\r
+ vuint32_t BK1_WWSC:5;\r
+ vuint32_t BK1_RWSC:5;\r
+ vuint32_t BK1_RWWC2:1;\r
+ vuint32_t BK1_RWWC1:1;\r
+ vuint32_t:7; /* changed to 7 to suit comment below */\r
+ //vuint32_t B1_P1_BFE:1; /* should have no effect, there is only one XBAR port (no P1) to P-flash controller */ \r
+ vuint32_t BK1_RWWC0:1;\r
+ vuint32_t:6;\r
+ vuint32_t B1_P0_BFE:1;\r
+ } B;\r
+ } PFCR1;\r
+ \r
+/* Commented out Bus Interface Unit 1 (Base+0x0020) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI1:32;\r
+ } B;\r
+ } BIU1; */\r
+\r
+ union { /* CFLASH Access Protection (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6; /*incorrect - B1M/B1.5M does not have this many masters TBD*/ \r
+ vuint32_t ARBM:2;\r
+ vuint32_t M7PFD:1;\r
+ vuint32_t M6PFD:1;\r
+ vuint32_t M5PFD:1;\r
+ vuint32_t M4PFD:1;\r
+ vuint32_t M3PFD:1;\r
+ vuint32_t M2PFD:1;\r
+ vuint32_t M1PFD:1;\r
+ vuint32_t M0PFD:1;\r
+ vuint32_t M7AP:2;\r
+ vuint32_t M6AP:2;\r
+ vuint32_t M5AP:2;\r
+ vuint32_t M4AP:2;\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } PFAPR;\r
+ \r
+/* Commented out Bus Interface Unit 2 (Base+0x0024) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI2:32;\r
+ } B;\r
+ } BIU2; */\r
+\r
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+ \r
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/\r
+\r
+ }; /* end of CFLASH_tag */\r
+/****************************************************************** \r
+| defines and macros (scope: module-local) \r
+|-----------------------------------------------------------------*/\r
+/* Define instances of modules */\r
+\r
+#define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL)\r
+#define ADC_1 (*(volatile struct ADC_tag *) 0xFFE04000UL)\r
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)\r
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)\r
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)\r
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)\r
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)\r
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)\r
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)\r
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)\r
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)\r
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)\r
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)\r
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)\r
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)\r
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)\r
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)\r
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)\r
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)\r
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)\r
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) \r
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)\r
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)\r
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)\r
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)\r
+#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)\r
+#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)\r
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)\r
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)\r
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)\r
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)\r
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)\r
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)\r
+//#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)\r
+//#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)\r
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)\r
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)\r
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)\r
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)\r
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)\r
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)\r
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)\r
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)\r
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)\r
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)\r
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)\r
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif \r
+/* End of file */\r
--- /dev/null
+/**************************************************************************** \r
+ * PROJECT : MPC5607B\r
+ * \r
+ * FILE : MPC5607B_2.01.h\r
+ * \r
+ * DESCRIPTION : This is the header file describing the register\r
+ * set for MPC5607B\r
+ * \r
+ * COPYRIGHT :(c) 2011, Freescale \r
+ * \r
+ * VERSION : 2.01 \r
+ * DATE : 3.30.2011 \r
+ * AUTHOR : r23668\r
+ * HISTORY : Based Upon Bolero 1M; Version 0.03 header file\r
+ * Updated and corrected errors present on B1.5M 01.04.1 \r
+ * and have brought up to date and format with B3M. Corrected\r
+ * LinFlex error.\r
+ * \r
+*\r
+* Example instantiation and use: \r
+* \r
+* <MODULE>.<REGISTER>.B.<BIT> = 1; \r
+* <MODULE>.<REGISTER>.R = 0x10000000;\r
+\r
+*****************************************************************************/\r
+\r
+#ifndef _JDP_H_\r
+#define _JDP_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+//#define CUT2\r
+/****************************************************************************/\r
+/* MODULE : ADC0 */\r
+/****************************************************************************/\r
+ struct ADC0_tag {\r
+\r
+ union { /* ADC0 Main Configuration Register (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORTCHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:4; \r
+ vuint32_t PWDN:1; \r
+ } B;\r
+ } MCR; \r
+ \r
+ union { /* ADC0 Main Status Register (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2; \r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR; \r
+ \r
+ vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+ \r
+ union { /* ADC0 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t EOC_CH31:1;\r
+ vuint32_t EOC_CH30:1;\r
+ vuint32_t EOC_CH29:1;\r
+ vuint32_t EOC_CH28:1;\r
+ vuint32_t EOC_CH27:1;\r
+ vuint32_t EOC_CH26:1;\r
+ vuint32_t EOC_CH25:1;\r
+ vuint32_t EOC_CH24:1;\r
+ vuint32_t EOC_CH23:1;\r
+ vuint32_t EOC_CH22:1;\r
+ vuint32_t EOC_CH21:1;\r
+ vuint32_t EOC_CH20:1;\r
+ vuint32_t EOC_CH19:1;\r
+ vuint32_t EOC_CH18:1;\r
+ vuint32_t EOC_CH17:1;\r
+ vuint32_t EOC_CH16:1;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CEOCFR0; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending Register 1 (Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EOC_CH63:1;\r
+ vuint32_t EOC_CH62:1;\r
+ vuint32_t EOC_CH61:1;\r
+ vuint32_t EOC_CH60:1;\r
+ vuint32_t EOC_CH59:1;\r
+ vuint32_t EOC_CH58:1;\r
+ vuint32_t EOC_CH57:1;\r
+ vuint32_t EOC_CH56:1;\r
+ vuint32_t EOC_CH55:1;\r
+ vuint32_t EOC_CH54:1;\r
+ vuint32_t EOC_CH53:1;\r
+ vuint32_t EOC_CH52:1;\r
+ vuint32_t EOC_CH51:1;\r
+ vuint32_t EOC_CH50:1;\r
+ vuint32_t EOC_CH49:1;\r
+ vuint32_t EOC_CH48:1;\r
+ vuint32_t EOC_CH47:1;\r
+ vuint32_t EOC_CH46:1;\r
+ vuint32_t EOC_CH45:1;\r
+ vuint32_t EOC_CH44:1;\r
+ vuint32_t EOC_CH43:1;\r
+ vuint32_t EOC_CH42:1;\r
+ vuint32_t EOC_CH41:1;\r
+ vuint32_t EOC_CH40:1;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CEOCFR1; \r
+ \r
+ union { /* ADC0 Channel Pending 2 (Base+0x001C) */\r
+ vuint32_t R; /* (For external mux'd Channels) */\r
+ struct {\r
+ vuint32_t EOC_CH95:1;\r
+ vuint32_t EOC_CH94:1;\r
+ vuint32_t EOC_CH93:1;\r
+ vuint32_t EOC_CH92:1;\r
+ vuint32_t EOC_CH91:1;\r
+ vuint32_t EOC_CH90:1;\r
+ vuint32_t EOC_CH89:1;\r
+ vuint32_t EOC_CH88:1;\r
+ vuint32_t EOC_CH87:1;\r
+ vuint32_t EOC_CH86:1;\r
+ vuint32_t EOC_CH85:1;\r
+ vuint32_t EOC_CH84:1;\r
+ vuint32_t EOC_CH83:1;\r
+ vuint32_t EOC_CH82:1;\r
+ vuint32_t EOC_CH81:1;\r
+ vuint32_t EOC_CH80:1;\r
+ vuint32_t EOC_CH79:1;\r
+ vuint32_t EOC_CH78:1;\r
+ vuint32_t EOC_CH77:1;\r
+ vuint32_t EOC_CH76:1;\r
+ vuint32_t EOC_CH75:1;\r
+ vuint32_t EOC_CH74:1;\r
+ vuint32_t EOC_CH73:1;\r
+ vuint32_t EOC_CH72:1;\r
+ vuint32_t EOC_CH71:1;\r
+ vuint32_t EOC_CH70:1;\r
+ vuint32_t EOC_CH69:1;\r
+ vuint32_t EOC_CH68:1;\r
+ vuint32_t EOC_CH67:1;\r
+ vuint32_t EOC_CH66:1;\r
+ vuint32_t EOC_CH65:1;\r
+ vuint32_t EOC_CH64:1;\r
+ } B;\r
+ } CE0CFR2; \r
+ \r
+\r
+ union { /* ADC0 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1; \r
+ } B;\r
+ } IMR; \r
+ \r
+\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */ \r
+ struct {\r
+ vuint32_t CIM63:1;\r
+ vuint32_t CIM62:1;\r
+ vuint32_t CIM61:1;\r
+ vuint32_t CIM60:1;\r
+ vuint32_t CIM59:1;\r
+ vuint32_t CIM58:1;\r
+ vuint32_t CIM57:1;\r
+ vuint32_t CIM56:1;\r
+ vuint32_t CIM55:1;\r
+ vuint32_t CIM54:1;\r
+ vuint32_t CIM53:1;\r
+ vuint32_t CIM52:1;\r
+ vuint32_t CIM51:1;\r
+ vuint32_t CIM50:1;\r
+ vuint32_t CIM49:1;\r
+ vuint32_t CIM48:1;\r
+ vuint32_t CIM47:1;\r
+ vuint32_t CIM46:1;\r
+ vuint32_t CIM45:1;\r
+ vuint32_t CIM44:1;\r
+ vuint32_t CIM43:1;\r
+ vuint32_t CIM42:1;\r
+ vuint32_t CIM41:1;\r
+ vuint32_t CIM40:1;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */\r
+ vuint32_t R; /* (For PExternal Mux'd Channels) */ \r
+ struct {\r
+ vuint32_t CIM95:1;\r
+ vuint32_t CIM94:1;\r
+ vuint32_t CIM93:1;\r
+ vuint32_t CIM92:1;\r
+ vuint32_t CIM91:1;\r
+ vuint32_t CIM90:1;\r
+ vuint32_t CIM89:1;\r
+ vuint32_t CIM88:1;\r
+ vuint32_t CIM87:1;\r
+ vuint32_t CIM86:1;\r
+ vuint32_t CIM85:1;\r
+ vuint32_t CIM84:1;\r
+ vuint32_t CIM83:1;\r
+ vuint32_t CIM82:1;\r
+ vuint32_t CIM81:1;\r
+ vuint32_t CIM80:1;\r
+ vuint32_t CIM79:1;\r
+ vuint32_t CIM78:1;\r
+ vuint32_t CIM77:1;\r
+ vuint32_t CIM76:1;\r
+ vuint32_t CIM75:1;\r
+ vuint32_t CIM74:1;\r
+ vuint32_t CIM73:1;\r
+ vuint32_t CIM72:1;\r
+ vuint32_t CIM71:1;\r
+ vuint32_t CIM70:1;\r
+ vuint32_t CIM69:1;\r
+ vuint32_t CIM68:1;\r
+ vuint32_t CIM67:1;\r
+ vuint32_t CIM66:1;\r
+ vuint32_t CIM65:1;\r
+ vuint32_t CIM64:1;\r
+ } B;\r
+ } CIMR2; \r
+\r
+ union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t WDG5H:1; \r
+ vuint32_t WDG5L:1; \r
+ vuint32_t WDG4H:1; \r
+ vuint32_t WDG4L:1; \r
+ vuint32_t WDG3H:1; \r
+ vuint32_t WDG3L:1; \r
+ vuint32_t WDG2H:1; \r
+ vuint32_t WDG2L:1; \r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1; \r
+ vuint32_t WDG0H:1; \r
+ vuint32_t WDG0L:1; \r
+ } B; \r
+ } WTISR; \r
+ \r
+ union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t MSKWDG5H:1; \r
+ vuint32_t MSKWDG5L:1; \r
+ vuint32_t MSKWDG4H:1; \r
+ vuint32_t MSKWDG4L:1;\r
+ vuint32_t MSKWDG3H:1; \r
+ vuint32_t MSKWDG2H:1; \r
+ vuint32_t MSKWDG1H:1; \r
+ vuint32_t MSKWDG0H:1; \r
+ vuint32_t MSKWDG3L:1; \r
+ vuint32_t MSKWDG2L:1; \r
+ vuint32_t MSKWDG1L:1; \r
+ vuint32_t MSKWDG0L:1; \r
+ } B; \r
+ } WTIMR; \r
+\r
+ vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+ \r
+ union { /* ADC0 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE; \r
+ \r
+ union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct { \r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0; \r
+ \r
+ union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */ \r
+ struct {\r
+ vuint32_t DMA63:1;\r
+ vuint32_t DMA62:1;\r
+ vuint32_t DMA61:1;\r
+ vuint32_t DMA60:1;\r
+ vuint32_t DMA59:1;\r
+ vuint32_t DMA58:1;\r
+ vuint32_t DMA57:1;\r
+ vuint32_t DMA56:1;\r
+ vuint32_t DMA55:1;\r
+ vuint32_t DMA54:1;\r
+ vuint32_t DMA53:1;\r
+ vuint32_t DMA52:1;\r
+ vuint32_t DMA51:1;\r
+ vuint32_t DMA50:1;\r
+ vuint32_t DMA49:1;\r
+ vuint32_t DMA48:1;\r
+ vuint32_t DMA47:1;\r
+ vuint32_t DMA46:1;\r
+ vuint32_t DMA45:1;\r
+ vuint32_t DMA44:1;\r
+ vuint32_t DMA43:1;\r
+ vuint32_t DMA42:1;\r
+ vuint32_t DMA41:1;\r
+ vuint32_t DMA40:1;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */\r
+ vuint32_t R; /* (for external mux'd channels) */ \r
+ struct {\r
+ vuint32_t DMA95:1;\r
+ vuint32_t DMA94:1;\r
+ vuint32_t DMA93:1;\r
+ vuint32_t DMA92:1;\r
+ vuint32_t DMA91:1;\r
+ vuint32_t DMA90:1;\r
+ vuint32_t DMA89:1;\r
+ vuint32_t DMA88:1;\r
+ vuint32_t DMA87:1;\r
+ vuint32_t DMA86:1;\r
+ vuint32_t DMA85:1;\r
+ vuint32_t DMA84:1;\r
+ vuint32_t DMA83:1;\r
+ vuint32_t DMA82:1;\r
+ vuint32_t DMA81:1;\r
+ vuint32_t DMA80:1;\r
+ vuint32_t DMA79:1;\r
+ vuint32_t DMA78:1;\r
+ vuint32_t DMA77:1;\r
+ vuint32_t DMA76:1;\r
+ vuint32_t DMA75:1;\r
+ vuint32_t DMA74:1;\r
+ vuint32_t DMA73:1;\r
+ vuint32_t DMA72:1;\r
+ vuint32_t DMA71:1;\r
+ vuint32_t DMA70:1;\r
+ vuint32_t DMA69:1;\r
+ vuint32_t DMA68:1;\r
+ vuint32_t DMA67:1;\r
+ vuint32_t DMA66:1;\r
+ vuint32_t DMA65:1;\r
+ vuint32_t DMA64:1;\r
+ } B;\r
+ } DMAR2; \r
+\r
+ vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */\r
+ \r
+\r
+ /*Note the threshold registers are split [0..3] then [4..5]. For this \r
+ reason thay are NOT implemented as an array in order to maintain \r
+ concistency through all THRHLR registers */ \r
+\r
+ union { /* ADC0 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC0 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC0 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ union { /* ADC0 Threshold 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR3; \r
+ \r
+\r
+ vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */\r
+ \r
+ union { /* ADC0 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1; \r
+ } B;\r
+ } PSCR; \r
+\r
+ \r
+ union { /* ADC0 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t PRES31:1;\r
+ vuint32_t PRES30:1;\r
+ vuint32_t PRES29:1;\r
+ vuint32_t PRES28:1;\r
+ vuint32_t PRES27:1;\r
+ vuint32_t PRES26:1;\r
+ vuint32_t PRES25:1;\r
+ vuint32_t PRES24:1;\r
+ vuint32_t PRES23:1;\r
+ vuint32_t PRES22:1;\r
+ vuint32_t PRES21:1;\r
+ vuint32_t PRES20:1;\r
+ vuint32_t PRES19:1;\r
+ vuint32_t PRES18:1;\r
+ vuint32_t PRES17:1;\r
+ vuint32_t PRES16:1;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0; \r
+ \r
+ union { /* ADC0 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t PRES63:1;\r
+ vuint32_t PRES62:1;\r
+ vuint32_t PRES61:1;\r
+ vuint32_t PRES60:1;\r
+ vuint32_t PRES59:1;\r
+ vuint32_t PRES58:1;\r
+ vuint32_t PRES57:1;\r
+ vuint32_t PRES56:1;\r
+ vuint32_t PRES55:1;\r
+ vuint32_t PRES54:1;\r
+ vuint32_t PRES53:1;\r
+ vuint32_t PRES52:1;\r
+ vuint32_t PRES51:1;\r
+ vuint32_t PRES50:1;\r
+ vuint32_t PRES49:1;\r
+ vuint32_t PRES48:1;\r
+ vuint32_t PRES47:1;\r
+ vuint32_t PRES46:1;\r
+ vuint32_t PRES45:1;\r
+ vuint32_t PRES44:1;\r
+ vuint32_t PRES43:1;\r
+ vuint32_t PRES42:1;\r
+ vuint32_t PRES41:1;\r
+ vuint32_t PRES40:1;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ union { /* ADC0 Presampling 2 (Base+0x008C) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t PRES95:1;\r
+ vuint32_t PRES94:1;\r
+ vuint32_t PRES93:1;\r
+ vuint32_t PRES92:1;\r
+ vuint32_t PRES91:1;\r
+ vuint32_t PRES90:1;\r
+ vuint32_t PRES89:1;\r
+ vuint32_t PRES88:1;\r
+ vuint32_t PRES87:1;\r
+ vuint32_t PRES86:1;\r
+ vuint32_t PRES85:1;\r
+ vuint32_t PRES84:1;\r
+ vuint32_t PRES83:1;\r
+ vuint32_t PRES82:1;\r
+ vuint32_t PRES81:1;\r
+ vuint32_t PRES80:1;\r
+ vuint32_t PRES79:1;\r
+ vuint32_t PRES78:1;\r
+ vuint32_t PRES77:1;\r
+ vuint32_t PRES76:1;\r
+ vuint32_t PRES75:1;\r
+ vuint32_t PRES74:1;\r
+ vuint32_t PRES73:1;\r
+ vuint32_t PRES72:1;\r
+ vuint32_t PRES71:1;\r
+ vuint32_t PRES70:1;\r
+ vuint32_t PRES69:1;\r
+ vuint32_t PRES68:1;\r
+ vuint32_t PRES67:1;\r
+ vuint32_t PRES66:1;\r
+ vuint32_t PRES65:1;\r
+ vuint32_t PRES64:1;\r
+ } B;\r
+ } PSR2; \r
+\r
+ vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */\r
+ \r
+ \r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC0 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC0 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ union { /* ADC0 Conversion Timing 2 (Base+0x009C) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR2; \r
+\r
+ vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */\r
+ \r
+\r
+union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */\r
+ vuint32_t R; /* (For external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } NCMR2; \r
+\r
+vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */\r
+\r
+ \r
+ union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */\r
+ vuint32_t R; /* (external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } JCMR2;\r
+ \r
+ \r
+ vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */\r
+ \r
+ union { /* ADC0 Decode Signals Delay (Base+0x00C4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t DSD:12;\r
+ } B;\r
+ } DSDR; \r
+ \r
+ union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ \r
+ vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */\r
+ \r
+ union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */\r
+ vuint32_t R; /* Note CDR[16..31] and CDR[60..63] are reserved */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:6;\r
+ vuint32_t CDATA:10;\r
+ } B;\r
+ } CDR[96]; \r
+ \r
+ union { /* ADC0 Threshold 4 (Base+0x0280) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR4;\r
+\r
+ union { /* ADC0 Threshold 5 (Base+0x0284) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR5;\r
+ \r
+ vuint8_t ADC0_reserved9[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */\r
+ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH7:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH6:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH5:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH4:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH3:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH2:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH1:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH0:3;\r
+ } B;\r
+ } CWSELR0; \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH15:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH14:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH13:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH12:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH11:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH10:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH9:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH8:3;\r
+ } B;\r
+ } CWSELR1; \r
+ \r
+ vuint8_t ADC0_reserved10[8]; /* Reserved 4 bytes (Base+0x02B8-0x02BF) */ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH39:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH38:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH37:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH36:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH35:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH34:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH33:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH32:3;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH47:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH46:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH45:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH44:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH43:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH42:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH41:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH40:3;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH55:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH54:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH53:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH52:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH51:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH50:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH49:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH48:3;\r
+ } B;\r
+ } CWSELR6;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH63:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH62:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH61:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH60:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH59:3;\r
+ vuint32_t:12;\r
+ } B;\r
+ } CWSELR7;\r
+ \r
+ union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH71:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH70:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH69:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH68:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH67:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH66:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH65:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH64:3;\r
+ } B;\r
+ } CWSELR8;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH79:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH78:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH77:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH76:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH75:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH74:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH73:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH72:3;\r
+ } B;\r
+ } CWSELR9;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH87:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH86:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH85:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH84:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH83:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH82:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH81:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH80:3;\r
+ } B;\r
+ } CWSELR10;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH95:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH94:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH93:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH92:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH91:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH90:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH89:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH88:3;\r
+ } B;\r
+ } CWSELR11;\r
+ \r
+ union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CWEN59:1;\r
+ vuint32_t CWEN58:1;\r
+ vuint32_t CWEN57:1;\r
+ vuint32_t CWEN56:1;\r
+ vuint32_t CWEN55:1;\r
+ vuint32_t CWEN54:1;\r
+ vuint32_t CWEN53:1;\r
+ vuint32_t CWEN52:1;\r
+ vuint32_t CWEN51:1;\r
+ vuint32_t CWEN50:1;\r
+ vuint32_t CWEN49:1;\r
+ vuint32_t CWEN48:1;\r
+ vuint32_t CWEN47:1;\r
+ vuint32_t CWEN46:1;\r
+ vuint32_t CWEN45:1;\r
+ vuint32_t CWEN44:1;\r
+ vuint32_t CWEN43:1;\r
+ vuint32_t CWEN42:1;\r
+ vuint32_t CWEN41:1;\r
+ vuint32_t CWEN40:1;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t CWEN95:1;\r
+ vuint32_t CWEN94:1;\r
+ vuint32_t CWEN93:1;\r
+ vuint32_t CWEN92:1;\r
+ vuint32_t CWEN91:1;\r
+ vuint32_t CWEN90:1;\r
+ vuint32_t CWEN89:1;\r
+ vuint32_t CWEN88:1;\r
+ vuint32_t CWEN87:1;\r
+ vuint32_t CWEN86:1;\r
+ vuint32_t CWEN85:1;\r
+ vuint32_t CWEN84:1;\r
+ vuint32_t CWEN83:1;\r
+ vuint32_t CWEN82:1;\r
+ vuint32_t CWEN81:1;\r
+ vuint32_t CWEN80:1;\r
+ vuint32_t CWEN79:1;\r
+ vuint32_t CWEN78:1;\r
+ vuint32_t CWEN77:1;\r
+ vuint32_t CWEN76:1;\r
+ vuint32_t CWEN75:1;\r
+ vuint32_t CWEN74:1;\r
+ vuint32_t CWEN73:1;\r
+ vuint32_t CWEN72:1;\r
+ vuint32_t CWEN71:1;\r
+ vuint32_t CWEN70:1;\r
+ vuint32_t CWEN69:1;\r
+ vuint32_t CWEN68:1;\r
+ vuint32_t CWEN67:1;\r
+ vuint32_t CWEN66:1;\r
+ vuint32_t CWEN65:1;\r
+ vuint32_t CWEN64:1;\r
+ } B;\r
+ } CWENR2;\r
+\r
+ vuint8_t ADC0_reserved11[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */\r
+ \r
+union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t AWORR_CH59:1;\r
+ vuint32_t AWORR_CH58:1;\r
+ vuint32_t AWORR_CH57:1;\r
+ vuint32_t AWORR_CH56:1;\r
+ vuint32_t AWORR_CH55:1;\r
+ vuint32_t AWORR_CH54:1;\r
+ vuint32_t AWORR_CH53:1;\r
+ vuint32_t AWORR_CH52:1;\r
+ vuint32_t AWORR_CH51:1;\r
+ vuint32_t AWORR_CH50:1;\r
+ vuint32_t AWORR_CH49:1;\r
+ vuint32_t AWORR_CH48:1;\r
+ vuint32_t AWORR_CH47:1;\r
+ vuint32_t AWORR_CH46:1;\r
+ vuint32_t AWORR_CH45:1;\r
+ vuint32_t AWORR_CH44:1;\r
+ vuint32_t AWORR_CH43:1;\r
+ vuint32_t AWORR_CH42:1;\r
+ vuint32_t AWORR_CH41:1;\r
+ vuint32_t AWORR_CH40:1;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AWORR_CH95:1;\r
+ vuint32_t AWORR_CH94:1;\r
+ vuint32_t AWORR_CH93:1;\r
+ vuint32_t AWORR_CH92:1;\r
+ vuint32_t AWORR_CH91:1;\r
+ vuint32_t AWORR_CH90:1;\r
+ vuint32_t AWORR_CH89:1;\r
+ vuint32_t AWORR_CH88:1;\r
+ vuint32_t AWORR_CH87:1;\r
+ vuint32_t AWORR_CH86:1;\r
+ vuint32_t AWORR_CH85:1;\r
+ vuint32_t AWORR_CH84:1;\r
+ vuint32_t AWORR_CH83:1;\r
+ vuint32_t AWORR_CH82:1;\r
+ vuint32_t AWORR_CH81:1;\r
+ vuint32_t AWORR_CH80:1;\r
+ vuint32_t AWORR_CH79:1;\r
+ vuint32_t AWORR_CH78:1;\r
+ vuint32_t AWORR_CH77:1;\r
+ vuint32_t AWORR_CH76:1;\r
+ vuint32_t AWORR_CH75:1;\r
+ vuint32_t AWORR_CH74:1;\r
+ vuint32_t AWORR_CH73:1;\r
+ vuint32_t AWORR_CH72:1;\r
+ vuint32_t AWORR_CH71:1;\r
+ vuint32_t AWORR_CH70:1;\r
+ vuint32_t AWORR_CH69:1;\r
+ vuint32_t AWORR_CH68:1;\r
+ vuint32_t AWORR_CH67:1;\r
+ vuint32_t AWORR_CH66:1;\r
+ vuint32_t AWORR_CH65:1;\r
+ vuint32_t AWORR_CH64:1;\r
+ } B;\r
+ } AWORR2;\r
+\r
+ //vuint8_t ADC0_reserved12[15620]; /* Reserved 15620 bytes (Base+0x02FC-0x3FFF) */ \r
+ \r
+}; /* end of ADC0_tag */ \r
+\r
+/****************************************************************************/\r
+/* MODULE : ADC1 (12 Bit) */\r
+/****************************************************************************/\r
+struct ADC1_tag {\r
+\r
+ union { /* ADC1 Main Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORT_CHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t:2;\r
+ vuint32_t PWDN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* ADC1 Main Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR;\r
+\r
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ union { /* ADC1 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CE0CFR0;\r
+\r
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */\r
+ vuint32_t R; /* (For standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CE0CFR1;\r
+\r
+ vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* ADC1 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1;\r
+ } B;\r
+ } IMR;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t WDG2H:1;\r
+ vuint32_t WDG2L:1;\r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1;\r
+ vuint32_t WDG0H:1;\r
+ vuint32_t WDG0L:1;\r
+ } B;\r
+ } WTISR;\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t MSKWDG2H:1;\r
+ vuint32_t MSKWDG2L:1;\r
+ vuint32_t MSKWDG1H:1;\r
+ vuint32_t MSKWDG1L:1;\r
+ vuint32_t MSKWDG0H:1;\r
+ vuint32_t MSKWDG0L:1;\r
+ } B;\r
+ } WTIMR;\r
+\r
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+\r
+ union { /* ADC1 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE;\r
+\r
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0;\r
+\r
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */\r
+\r
+ /* Note the threshold registers are not implemented as an array for */\r
+ /* concistency with ADC0 header section */\r
+\r
+ union { /* ADC1 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC1 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC1 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */\r
+\r
+ union { /* ADC1 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1;\r
+ } B;\r
+ } PSCR;\r
+\r
+ union { /* ADC1 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0;\r
+\r
+ union { /* ADC1 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */\r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */\r
+\r
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */\r
+\r
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ vuint8_t ADC1_reserved9[12]; /* Reserved 12 bytes (Base+0x00BC-0x00C7) */\r
+ \r
+ union { /* Power Down Exit Delay Register (base+0x00C8)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24; \r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */ \r
+\r
+ union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */\r
+ vuint32_t R; /* Note CDR[16..31] are reserved 0x0140-0x017F */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:4;\r
+ vuint32_t CDATA:12;\r
+ } B;\r
+ } CDR[40];\r
+\r
+ vuint8_t ADC1_reserved11[272]; /* Reserved 252 bytes (Base+0x01A0-0x002AF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH7:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH6:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH5:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH4:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH3:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH2:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH1:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH0:2;\r
+ } B;\r
+ } CWSELR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH15:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH14:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH13:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH12:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH11:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH10:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH9:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH8:2;\r
+ } B;\r
+ } CWSELR1;\r
+\r
+ vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH39:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH38:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH37:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH36:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH35:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH34:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH33:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH32:2;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t WSEL_CH44:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH43:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH42:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH41:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH40:2;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ vuint8_t ADC1_reserved13[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */\r
+\r
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */\r
+\r
+}; /* end of ADC1_tag */ \r
+/****************************************************************************/\r
+/* MODULE : CANSP */\r
+/****************************************************************************/\r
+ struct CANSP_tag {\r
+ \r
+ union { /* CANSP Control Reg (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RX_COMPLETE:1;\r
+ vuint32_t BUSY:1;\r
+ vuint32_t ACTIVE_CK:1;\r
+ vuint32_t:3;\r
+ vuint32_t MODE:1;\r
+ vuint32_t CAN_RX_SEL:3;\r
+ vuint32_t BRP:5;\r
+ vuint32_t CAN_SMPLR_EN:1;\r
+ } B;\r
+ } CR; \r
+\r
+ union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/\r
+ vuint32_t R;\r
+ } SR[12];\r
+\r
+ }; /* end of CANSP_tag */ \r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+struct ECSM_tag{\r
+\r
+ union { /* ECSM Processor Core Type (Base+0x0000) */\r
+ vuint16_t R;\r
+ } PCT;\r
+\r
+ union { /* ECSM Revision (Base+0x0002) */\r
+ vuint16_t R;\r
+ } REV;\r
+\r
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ } IMC;\r
+\r
+ vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */\r
+\r
+ union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBWCR:1;\r
+ vuint8_t :3;\r
+ vuint8_t PRILVL:4;\r
+ } B;\r
+ } MWCR;\r
+\r
+ vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */\r
+\r
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t FB0AI:1;\r
+ vuint8_t FB0SI:1;\r
+ vuint8_t FB1AI:1;\r
+ vuint8_t FB1SI:1;\r
+ vuint8_t :4;\r
+ } B;\r
+ } MIR;\r
+\r
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */\r
+\r
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/\r
+ vuint32_t R;\r
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */\r
+\r
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */\r
+\r
+ union { /* ECSM ECC Configuration (Base+0x0043) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t ER1BR:1;\r
+ vuint8_t EF1BR:1;\r
+ vuint8_t :2;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR;\r
+\r
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */\r
+\r
+ union { /* ECSM ECC Status (Base+0x0047) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t R1BC:1;\r
+ vuint8_t F1BC:1;\r
+ vuint8_t :2;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */\r
+\r
+ union { /* ECSM ECC Error Generation (Base+0x004A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :2;\r
+ vuint16_t FRC1BI:1;\r
+ vuint16_t FR11BI:1;\r
+ vuint16_t :2;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t :1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR;\r
+\r
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */\r
+\r
+ union { /* ECSM Flash ECC Address(Base+0x0050) */\r
+ vuint32_t R;\r
+ } FEAR;\r
+\r
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */\r
+\r
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR;\r
+\r
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } FEAT;\r
+\r
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */\r
+\r
+ union { /* ECSM Flash ECC Data (Base+0x005C) */\r
+ vuint32_t R;\r
+ } FEDR;\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0060) */\r
+ vuint32_t R;\r
+ } REAR;\r
+\r
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0065) */\r
+ vuint8_t R;\r
+ } RESR;\r
+\r
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR;\r
+\r
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } REAT;\r
+\r
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */\r
+\r
+ union { /* ECSM RAM ECC Data (Base+0x006C) */\r
+ vuint32_t R;\r
+ } REDR;\r
+\r
+}; /* end of ECSM_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : RTC/API */\r
+/****************************************************************************/\r
+struct RTC_tag{\r
+\r
+ union { /* RTC Supervisor Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SUPV:1;\r
+ vuint32_t :31;\r
+ } B;\r
+ } RTCSUPV ;\r
+\r
+ union { /* RTC Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNTEN:1;\r
+ vuint32_t RTCIE:1;\r
+ vuint32_t FRZEN:1;\r
+ vuint32_t ROVREN:1;\r
+ vuint32_t RTCVAL:12;\r
+ vuint32_t APIEN:1;\r
+ vuint32_t APIIE:1;\r
+ vuint32_t CLKSEL:2;\r
+ vuint32_t DIV512EN:1;\r
+ vuint32_t DIV32EN:1;\r
+ vuint32_t APIVAL:10;\r
+ } B;\r
+ } RTCC;\r
+\r
+ union { /* RTC Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t RTCF:1;\r
+ vuint32_t :15;\r
+ vuint32_t APIF:1;\r
+ vuint32_t :2;\r
+ vuint32_t ROVRF:1;\r
+ vuint32_t :10;\r
+ } B;\r
+ } RTCS;\r
+\r
+ union { /* RTC Counter (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RTCCNT:32;\r
+ } B;\r
+ } RTCCNT;\r
+\r
+}; /* end of RTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */\r
+/****************************************************************************/\r
+struct SIU_tag {\r
+\r
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */\r
+\r
+ union { /* MCU ID1 (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t CSP:1;\r
+ vuint32_t PKG:5;\r
+ vuint32_t :2;\r
+ vuint32_t MAJOR_MASK:4;\r
+ vuint32_t MINOR_MASK:4;\r
+ } B;\r
+ } MIDR1;\r
+\r
+ union { /* MCU ID2 (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SF:1;\r
+ vuint32_t FLASH_SIZE_1:4;\r
+ vuint32_t FLASH_SIZE_2:4;\r
+ vuint32_t :7;\r
+ vuint32_t PARTNUM:8;\r
+ vuint32_t :3;\r
+ vuint32_t EE:1;\r
+ vuint32_t :3;\r
+ vuint32_t FR:1;\r
+ } B;\r
+ } MIDR2;\r
+\r
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */\r
+\r
+ union { /* Interrupt Status Flag (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EIF23:1;\r
+ vuint32_t EIF22:1;\r
+ vuint32_t EIF21:1;\r
+ vuint32_t EIF20:1;\r
+ vuint32_t EIF19:1;\r
+ vuint32_t EIF18:1;\r
+ vuint32_t EIF17:1;\r
+ vuint32_t EIF16:1;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IRE23:1;\r
+ vuint32_t IRE22:1;\r
+ vuint32_t IRE21:1;\r
+ vuint32_t IRE20:1;\r
+ vuint32_t IRE19:1;\r
+ vuint32_t IRE18:1;\r
+ vuint32_t IRE17:1;\r
+ vuint32_t IRE16:1;\r
+ vuint32_t IRE15:1;\r
+ vuint32_t IRE14:1;\r
+ vuint32_t IRE13:1;\r
+ vuint32_t IRE12:1;\r
+ vuint32_t IRE11:1;\r
+ vuint32_t IRE10:1;\r
+ vuint32_t IRE9:1;\r
+ vuint32_t IRE8:1;\r
+ vuint32_t IRE7:1;\r
+ vuint32_t IRE6:1;\r
+ vuint32_t IRE5:1;\r
+ vuint32_t IRE4:1;\r
+ vuint32_t IRE3:1;\r
+ vuint32_t IRE2:1;\r
+ vuint32_t IRE1:1;\r
+ vuint32_t IRE0:1;\r
+ } B;\r
+ } IRER;\r
+\r
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */\r
+\r
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IREE23:1;\r
+ vuint32_t IREE22:1;\r
+ vuint32_t IREE21:1;\r
+ vuint32_t IREE20:1;\r
+ vuint32_t IREE19:1;\r
+ vuint32_t IREE18:1;\r
+ vuint32_t IREE17:1;\r
+ vuint32_t IREE16:1;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFEE23:1;\r
+ vuint32_t IFEE22:1;\r
+ vuint32_t IFEE21:1;\r
+ vuint32_t IFEE20:1;\r
+ vuint32_t IFEE19:1;\r
+ vuint32_t IFEE18:1;\r
+ vuint32_t IFEE17:1;\r
+ vuint32_t IFEE16:1;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFE23:1;\r
+ vuint32_t IFE22:1;\r
+ vuint32_t IFE21:1;\r
+ vuint32_t IFE20:1;\r
+ vuint32_t IFE19:1;\r
+ vuint32_t IFE18:1;\r
+ vuint32_t IFE17:1;\r
+ vuint32_t IFE16:1;\r
+ vuint32_t IFE15:1;\r
+ vuint32_t IFE14:1;\r
+ vuint32_t IFE13:1;\r
+ vuint32_t IFE12:1;\r
+ vuint32_t IFE11:1;\r
+ vuint32_t IFE10:1;\r
+ vuint32_t IFE9:1;\r
+ vuint32_t IFE8:1;\r
+ vuint32_t IFE7:1;\r
+ vuint32_t IFE6:1;\r
+ vuint32_t IFE5:1;\r
+ vuint32_t IFE4:1;\r
+ vuint32_t IFE3:1;\r
+ vuint32_t IFE2:1;\r
+ vuint32_t IFE1:1;\r
+ vuint32_t IFE0:1;\r
+ } B;\r
+ } IFER;\r
+\r
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */\r
+\r
+ union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SMC:1;\r
+ vuint16_t APC:1;\r
+ vuint16_t:1;\r
+ vuint16_t PA:2;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t:2;\r
+ vuint16_t SRC:1;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[149];\r
+\r
+ vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */\r
+\r
+ union { /* Pad Selection for Mux Input (0x0500-0x53C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t PADSEL:4;\r
+ } B;\r
+ } PSMI[64];\r
+\r
+ vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */\r
+\r
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[152];\r
+\r
+ vuint8_t SIU_reserved6[348]; /*Reserved 348 Bytes (Base+0x06A4-0x07FF) */\r
+\r
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[152];\r
+\r
+ vuint8_t SIU_reserved7[860]; /*Reserved 860 Bytes (Base+0x08A4-0x0BFF) */\r
+\r
+ union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPD0:32;\r
+ } B;\r
+ } PGPDO[5];\r
+\r
+ vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */\r
+\r
+ union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPDI:32;\r
+ } B;\r
+ } PGPDI[5];\r
+\r
+ vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */\r
+\r
+ union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MASK:16;\r
+ vuint32_t MPPDO:16;\r
+ } B;\r
+ } MPGPDO[9];\r
+\r
+ vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/\r
+\r
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t MAXCNT:4;\r
+ } B;\r
+ } IFMC[24];\r
+\r
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/\r
+\r
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t IFCP:4;\r
+ } B;\r
+ } IFCPR;\r
+\r
+ vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/\r
+\r
+}; /* end of SIU_tag */\r
+/****************************************************************************/\r
+/* MODULE : SSCM */\r
+/****************************************************************************/\r
+struct SSCM_tag{\r
+\r
+ union { /* Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t NXEN:1;\r
+ vuint16_t:3;\r
+ vuint16_t BMODE:3;\r
+ vuint16_t :1;\r
+ vuint16_t ABD:1;\r
+ vuint16_t:3;\r
+ } B;\r
+ } STATUS;\r
+\r
+ union { /* System Memory Configuration (Base+0x002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t PRSZ:5;\r
+ vuint16_t PVLB:1;\r
+ vuint16_t DTSZ:4;\r
+ vuint16_t DVLD:1;\r
+ } B;\r
+ } MEMCONFIG;\r
+\r
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */\r
+\r
+ union { /* Error Configuration (Base+0x0006) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :14;\r
+ vuint16_t PAE:1;\r
+ vuint16_t RAE:1;\r
+ } B;\r
+ } ERROR;\r
+\r
+ union { /* Debug Status Port (Base+0x0008) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :13;\r
+ vuint16_t DEBUG_MODE:3;\r
+ } B;\r
+ } DEBUGPORT;\r
+\r
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */\r
+\r
+ union { /* Password Comparison High Word (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_HI:32;\r
+ } B;\r
+ } PWCMPH;\r
+\r
+ union { /* Password Comparison Low Word (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_LO:32;\r
+ } B;\r
+ } PWCMPL;\r
+\r
+}; /* end of SSCM_tag */\r
+/****************************************************************************/\r
+/* MODULE : STM */\r
+/****************************************************************************/\r
+ struct STM_CHANNEL_tag{\r
+\r
+ union { /* STM Channel Control 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* STM Channel Interrupt 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR;\r
+\r
+ union { /* STM Channel Compare 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CMP:32;\r
+ } B;\r
+ } CMP;\r
+\r
+ vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */\r
+\r
+ }; /* end of STM_CHANNEL_tag */\r
+\r
+\r
+struct STM_tag{\r
+\r
+ union { /* STM Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t :6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* STM Count (Base+0x0004) */\r
+ vuint32_t R;\r
+ } CNT;\r
+\r
+ vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */\r
+\r
+}; /* end of STM_tag */\r
+/****************************************************************************/\r
+/* MODULE : SWT */\r
+/****************************************************************************/\r
+struct SWT_tag{\r
+\r
+ union { /* SWT Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t :14;\r
+ vuint32_t KEY:1;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WND:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* SWT Interrupt (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR;\r
+\r
+ union { /* SWT Time-Out (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WTO:32;\r
+ } B;\r
+ } TO;\r
+\r
+ union { /* SWT Window (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WST:32;\r
+ } B;\r
+ } WN;\r
+\r
+ union { /* SWT Service (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* SWT Counter Output (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNT:32;\r
+ } B;\r
+ } CO;\r
+\r
+}; /* end of SWT_tag */ \r
+/****************************************************************************/\r
+/* MODULE : WKUP */\r
+/****************************************************************************/\r
+struct WKUP_tag{\r
+\r
+ union { /* NMI Status Flag (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NIF0:1; \r
+ vuint32_t NOVF0:1;\r
+ vuint32_t :30;\r
+ } B;\r
+ } NSR;\r
+\r
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* NMI Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NLOCK0:1;\r
+ vuint32_t NDSS0:2;\r
+ vuint32_t NWRE0:1;\r
+ vuint32_t :1;\r
+ vuint32_t NREE0:1;\r
+ vuint32_t NFEE0:1;\r
+ vuint32_t NFE0:1;\r
+ vuint32_t :24;\r
+ } B;\r
+ } NCR;\r
+\r
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */\r
+\r
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIF:29;\r
+ } B;\r
+ } WISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIRE:29; \r
+ } B;\r
+ } IRER;\r
+\r
+ union { /* Wakeup Request Enable (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t WRE:29;\r
+ } B;\r
+ } WRER;\r
+\r
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */\r
+\r
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IREE:29;\r
+ } B;\r
+ } WIREER;\r
+\r
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFEE:29;\r
+ } B;\r
+ } WIFEER;\r
+\r
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFE:29;\r
+ } B;\r
+ } WIFER;\r
+\r
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IPUE:29;\r
+ } B;\r
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */\r
+\r
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */\r
+\r
+}; /* end of WKUP_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEX */\r
+/****************************************************************************/\r
+struct LINFLEX_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t:3; /* for LINflexD no reseve here*/\r
+ vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ \r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ \r
+}; /* end of LINFLEX_tag */\r
+\r
+\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD0 */\r
+/****************************************************************************/\r
+struct LINFLEXD0_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ union { /* LINFLEX Global Counter (+0x008C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0090) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0094) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD0_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD1 */\r
+/****************************************************************************/\r
+struct LINFLEXD1_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+/* No IFCR registers on LinFlexD_1 */\r
+\r
+ union { /* LINFLEX Global Counter (+0x004C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0050) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x005C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD1_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : ME */\r
+/****************************************************************************/\r
+struct ME_tag{\r
+\r
+ union { /* Global Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t S_CURRENTMODE:4;\r
+ vuint32_t S_MTRANS:1;\r
+ vuint32_t S_DC:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_MVR:1;\r
+ vuint32_t S_DFLA:2;\r
+ vuint32_t S_CFLA:2;\r
+ vuint32_t :9;\r
+ vuint32_t S_FMPLL:1;\r
+ vuint32_t S_FXOSC:1;\r
+ vuint32_t S_FIRC:1;\r
+ vuint32_t S_SYSCLK:4;\r
+ } B;\r
+ } GS;\r
+\r
+ union { /* Mode Control (Base+0x004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TARGET_MODE:4;\r
+ vuint32_t :12;\r
+ vuint32_t KEY:16;\r
+ } B;\r
+ } MCTL;\r
+\r
+ union { /* Mode Enable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t :2;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } MER;\r
+\r
+ union { /* Interrupt Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t I_ICONF:1;\r
+ vuint32_t I_IMODE:1;\r
+ vuint32_t I_SAFE:1;\r
+ vuint32_t I_MTC:1;\r
+ } B;\r
+ } IS;\r
+\r
+ union { /* Interrupt Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t M_ICONF:1;\r
+ vuint32_t M_IMODE:1;\r
+ vuint32_t M_SAFE:1;\r
+ vuint32_t M_MTC:1;\r
+ } B;\r
+ } IM;\r
+\r
+ union { /* Invalid Mode Transition Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :27;\r
+ vuint32_t S_MTI:1;\r
+ vuint32_t S_MRI:1;\r
+ vuint32_t S_DMA:1;\r
+ vuint32_t S_NMA:1;\r
+ vuint32_t S_SEA:1;\r
+ } B;\r
+ } IMTS;\r
+\r
+ union { /* Debug Mode Transition Status (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t MPH_BUSY:1;\r
+ vuint32_t :2;\r
+ vuint32_t PMC_PROG:1;\r
+ vuint32_t CORE_DBG:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMR:1;\r
+ vuint32_t :1;\r
+ vuint32_t FMPLL_SC:1;\r
+ vuint32_t FXOSC_SC:1;\r
+ vuint32_t FIRC_SC:1;\r
+ vuint32_t :1;\r
+ vuint32_t SYSCLK_SW:1;\r
+ vuint32_t DFLASH_SC:1;\r
+ vuint32_t CFLASH_SC:1;\r
+ vuint32_t CDP_PRPH_0_143:1;\r
+ vuint32_t :3;\r
+ vuint32_t CDP_PRPH_96_127:1;\r
+ vuint32_t CDP_PRPH_64_95:1;\r
+ vuint32_t CDP_PRPH_32_63:1;\r
+ vuint32_t CDP_PRPH_0_31:1;\r
+ } B;\r
+ } DMTS;\r
+\r
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* Reset Mode Configuration (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RESET;\r
+\r
+ union { /* Test Mode Configuration (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } TEST;\r
+\r
+ union { /* Safe Mode Configuration (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } SAFE;\r
+\r
+ union { /* DRUN Mode Configuration (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSCON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } DRUN;\r
+\r
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RUN[4];\r
+\r
+ union { /* HALT0 Mode Configuration (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } HALT0;\r
+\r
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */\r
+\r
+ union { /* STOP0 Mode Configuration (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STOP0;\r
+\r
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */\r
+\r
+ union { /* STANDBY0 Mode Configuration (Base+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STANDBY0;\r
+\r
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct { /* Peripheral Status 0 (Base+0x0060) */\r
+ vuint32_t :8;\r
+ vuint32_t S_DMA_CH_MUX:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_FLEXCAN5:1;\r
+ vuint32_t S_FLEXCAN4:1;\r
+ vuint32_t S_FLEXCAN3:1;\r
+ vuint32_t S_FLEXCAN2:1;\r
+ vuint32_t S_FLEXCAN1:1;\r
+ vuint32_t S_FLEXCAN0:1;\r
+ vuint32_t :2;\r
+ vuint32_t :1; /* S_LINFLEX9:1; // not present on B1M */\r
+ vuint32_t :1; /* S_LINFLEX8:1; // not present on B1M */\r
+ vuint32_t :2;\r
+ vuint32_t S_DSPI5:1;\r
+ vuint32_t S_DSPI4:1;\r
+ vuint32_t S_DSPI3:1;\r
+ vuint32_t S_DSPI2:1;\r
+ vuint32_t S_DSPI1:1;\r
+ vuint32_t S_DSPI0:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS0;\r
+\r
+ union { /* Peripheral Status 1 (Base+0x0064)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_CANSAMPLER:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_CTUL:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_LINFLEX7:1;\r
+ vuint32_t S_LINFLEX6:1;\r
+ vuint32_t S_LINFLEX5:1;\r
+ vuint32_t S_LINFLEX4:1;\r
+ vuint32_t S_LINFLEX3:1;\r
+ vuint32_t S_LINFLEX2:1;\r
+ vuint32_t S_LINFLEX1:1;\r
+ vuint32_t S_LINFLEX0:1;\r
+ vuint32_t :3;\r
+ vuint32_t S_I2C0:1;\r
+ vuint32_t :10;\r
+ vuint32_t S_ADC1:1;\r
+ vuint32_t S_ADC0:1;\r
+ } B;\r
+ } PS1;\r
+\r
+ union { /* Peripheral Status 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_PIT_RTI:1;\r
+ vuint32_t S_RTC_API:1;\r
+ vuint32_t :16;\r
+ vuint32_t S_EMIOS1:1;\r
+ vuint32_t S_EMIOS0:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_WKPU:1; \r
+ vuint32_t S_SIUL:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS2;\r
+\r
+ union { /* Peripheral Status 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :23;\r
+ vuint32_t S_CMU:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } PS3;\r
+\r
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */\r
+\r
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } RUNPC[8];\r
+\r
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } LPPC[8];\r
+\r
+\r
+ /* Note on PCTL registers: There are only some PCTL implemented in */\r
+ /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */\r
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */\r
+ /* to be careful when addressing these registers in order not to */\r
+ /* access a PCTL that is not implemented. Following are available: */\r
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 51, 50, 49,48, */\r
+ /* 44, 33, 32, 23, 21-16, 13, 12, 9-4 */\r
+\r
+ union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t DBG_F:1;\r
+ vuint8_t LP_CFG:3;\r
+ vuint8_t RUN_CFG:3;\r
+ } B;\r
+ } PCTL[105];\r
+\r
+}; /* end of ME_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CGM */\r
+/****************************************************************************/\r
+struct CGM_tag{\r
+ /*\r
+ The "CGM" has fairly wide coverage and essentially includes everything in\r
+\r
+ chapter 9 of the Bolero Reference Manual:\r
+\r
+ Base Address | Clock Sources\r
+\r
+ ----------------------------- \r
+\r
+ 0xC3FE0000 | FXOSC_CTL\r
+\r
+ 0xC3FE0040 | SXOSC_CTL\r
+\r
+ 0xC3FE0060 | FIRC_CTL\r
+\r
+ 0xC3FE0080 | SIRC_CTL\r
+\r
+ 0xC3FE00A0 | FMPLL\r
+\r
+ 0xC3FE00C0 | CGM Block 1\r
+\r
+ 0xC3FE0100 | CMU \r
+\r
+ 0xC3FE0120 | CGM Block 2\r
+\r
+\r
+\r
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 \r
+\r
+ */\r
+ /* FXOSC - 0xC3FE_0000*/\r
+ union { /* Fast OSC Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } FXOSC_CTL;\r
+\r
+\r
+ /* Reserved Space between end of FXOSC and start SXOSC */\r
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */\r
+\r
+\r
+ /* SXOSC - 0xC3FE_0040*/\r
+ union { /* Slow Osc Control (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t :5;\r
+ vuint32_t S_OSC:1;\r
+ vuint32_t OSCON:1;\r
+ } B;\r
+ } SXOSC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SXOSC and start of FIRC */\r
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */\r
+\r
+\r
+ /* FIRC - 0xC3FE_0060 */\r
+ union { /* Fast IRC Control (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :10;\r
+ vuint32_t RCTRIM:6;\r
+ vuint32_t :3;\r
+ vuint32_t RCDIV:5;\r
+ vuint32_t :2;\r
+ vuint32_t FIRCON_STDBY:1;\r
+ vuint32_t :5;\r
+ } B;\r
+ } FIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of FIRC and start of SIRC */\r
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */\r
+\r
+\r
+ /* SIRC - 0xC3FE_0080 */\r
+ union { /* Slow IRC Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :11;\r
+ vuint32_t SIRCTRIM:5;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCDIV:5;\r
+ vuint32_t :3;\r
+ vuint32_t S_SIRC:1;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCON_STDBY:1;\r
+ } B;\r
+ } SIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SIRC and start of FMPLL */\r
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */\r
+\r
+\r
+ /* FMPLL - 0xC3FE_00A0 */\r
+ union { /* FMPLL Control (Base+0x00A0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t IDF:4;\r
+ vuint32_t ODF:2;\r
+ vuint32_t:1;\r
+ vuint32_t NDIV:7;\r
+ vuint32_t:7;\r
+ vuint32_t EN_PLL_SW:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t UNLOCK_ONCE:1;\r
+ vuint32_t:1;\r
+ vuint32_t I_LOCK:1;\r
+ vuint32_t S_LOCK:1;\r
+ vuint32_t PLL_FAIL_MASK:1;\r
+ vuint32_t PLL_FAIL_FLAG:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } FMPLL_CR;\r
+\r
+ union { /* FMPLL Modulation (Base+0x00A4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STRB_BYPASS:1;\r
+ vuint32_t :1;\r
+ vuint32_t SPRD_SEL:1;\r
+ vuint32_t MOD_PERIOD:13;\r
+ vuint32_t FM_EN:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } FMPLL_MR;\r
+\r
+\r
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */\r
+ vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */\r
+\r
+ /* CMU - 0xC3FE_0100 */\r
+ union { /* CMU Control Status (Base+0x0100) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t SFM:1;\r
+ vuint32_t :13;\r
+ vuint32_t CLKSEL1:2;\r
+ vuint32_t :5;\r
+ vuint32_t RCDIV:2;\r
+ vuint32_t CME_A:1;\r
+ } B;\r
+ } CMU_CSR;\r
+\r
+ union { /* CMU Frequency Display (Base+0x0104) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t FD:20;\r
+ } B;\r
+ } CMU_FDR;\r
+\r
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t HFREF:12;\r
+ } B;\r
+ } CMU_HFREFR;\r
+\r
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t LFREF:12;\r
+ } B;\r
+ } CMU_LFREFR;\r
+\r
+ union { /* CMU Interrupt Status (Base+0x0110) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :29;\r
+ vuint32_t FHHI:1; // *_A not present in RM\r
+ vuint32_t FLLI:1; // *_A not present in RM\r
+ vuint32_t OLRI:1;\r
+ } B;\r
+ } CMU_ISR;\r
+\r
+ /* Reserved space where IMR was previously positioned */\r
+ vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */\r
+\r
+ union { /* CMU Measurement Duration (Base+0x0118) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t MD:20;\r
+ } B;\r
+ } CMU_MDR;\r
+\r
+\r
+ /* Reserved space between end of CMU and start of CGM Block 2 */\r
+ vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */\r
+\r
+ union { /* GCM Output Clock Enable (Base+0x0370) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t EN:1;\r
+ } B;\r
+ } OC_EN;\r
+\r
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t SELDIV:2;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } OCDS_SC;\r
+\r
+ union { /* CGM System Clock Select Status (Base+0x0378) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELSTAT:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } SC_SS;\r
+\r
+ union { /* CGM Sys Clk Div Config 0.2 (0x037C-0x037E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DE:1;\r
+ vuint8_t :3;\r
+ vuint8_t DIV:4;\r
+ } B;\r
+ } SC_DC[3];\r
+\r
+ // vuint8_t CGM_reserved7[15489]; /*Reserved 1 byte (Base+0x037F - 0x3FFF) */\r
+\r
+}; /* end of CGM_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : RGM base address - 0xC3FE_4000 */\r
+/****************************************************************************/\r
+struct RGM_tag{\r
+\r
+ union { /* Functional Event Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t F_FLASH:1;\r
+ vuint16_t F_LVD45:1;\r
+ vuint16_t F_CMU_FHL:1;\r
+ vuint16_t F_CMU_OLR:1;\r
+ vuint16_t F_FMPLL:1;\r
+ vuint16_t F_CHKSTOP:1;\r
+ vuint16_t F_SOFT:1;\r
+ vuint16_t F_CORE:1;\r
+ vuint16_t F_JTAG:1;\r
+ } B;\r
+ } FES;\r
+\r
+ union { /* Destructive Event Status (Base+0x0002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_POR:1;\r
+ vuint16_t :10;\r
+ vuint16_t F_LVD27_VREG:1;\r
+ vuint16_t F_LVD27:1;\r
+ vuint16_t F_SWT:1;\r
+ vuint16_t F_LVD12_PD1:1;\r
+ vuint16_t F_LVD12_PD0:1;\r
+ } B;\r
+ } DES;\r
+\r
+ union { /* Functional Event Reset Disable (+0x0004) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t D_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t D_FLASH:1;\r
+ vuint16_t D_LVD45:1;\r
+ vuint16_t D_CMU_FHL:1;\r
+ vuint16_t D_CMU_OLR:1;\r
+ vuint16_t D_FMPLL:1;\r
+ vuint16_t D_CHKSTOP:1;\r
+ vuint16_t D_SOFT:1;\r
+ vuint16_t D_CORE:1;\r
+ vuint16_t D_JTAG:1;\r
+ } B;\r
+ } FERD;\r
+\r
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :11;\r
+ vuint16_t D_LVD27_VREG:1;\r
+ vuint16_t D_LVD27:1;\r
+ vuint16_t D_SWT:1;\r
+ vuint16_t D_LVD12_PD1:1;\r
+ vuint16_t D_LVD12_PD0:1;\r
+ } B;\r
+ } DERD;\r
+\r
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */\r
+\r
+ union { /* Functional Event Alt Request (Base+0x0010) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t AR_EXR:1;\r
+ vuint16_t:6;\r
+ vuint16_t AR_FLASH:1;\r
+ vuint16_t AR_LVD45:1;\r
+ vuint16_t AR_CMU_FHL:1;\r
+ vuint16_t AR_CMU_OLR:1;\r
+ vuint16_t AR_FMPLL:1;\r
+ vuint16_t AR_CHKSTOP:1;\r
+ vuint16_t AR_SOFT:1;\r
+ vuint16_t AR_CORE:1;\r
+ vuint16_t AR_JTAG:1;\r
+ } B;\r
+ } FEAR;\r
+ \r
+ union { /* Destructive Event Alt Request (Base+0x0012) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:11;\r
+ vuint16_t AR_LVD27_VREG:1;\r
+ vuint16_t AR_LVD27:1;\r
+ vuint16_t AR_SWT:1;\r
+ vuint16_t AR_LVD12_PD1:1;\r
+ vuint16_t AR_LVD12_PD0:1;\r
+ } B;\r
+ } DEAR; /* Destructive Event Alternate Request */\r
+\r
+ vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */\r
+\r
+ union { /* Functional Event Short Sequence (+0x0018) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SS_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t SS_FLASH:1;\r
+ vuint16_t SS_LVD45:1;\r
+ vuint16_t SS_CMU_FHL:1;\r
+ vuint16_t SS_CMU_OLR:1;\r
+ vuint16_t SS_FMPLL:1;\r
+ vuint16_t SS_CHKSTOP:1;\r
+ vuint16_t SS_SOFT:1;\r
+ vuint16_t SS_CORE:1;\r
+ vuint16_t SS_JTAG:1;\r
+ } B;\r
+ } FESS;\r
+\r
+ union { /* STANDBY reset sequence (Base+0x001A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :8;\r
+ vuint16_t BOOT_FROM_BKP_RAM:1;\r
+ vuint16_t :7;\r
+ } B;\r
+ } STDBY;\r
+\r
+ union { /* Functional Bidirectional Reset En (+0x001C) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t BE_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t BE_FLASH:1;\r
+ vuint16_t BE_LVD45:1;\r
+ vuint16_t BE_CMU_FHL:1;\r
+ vuint16_t BE_CMU_OLR:1;\r
+ vuint16_t BE_FMPLL:1;\r
+ vuint16_t BE_CHKSTOP:1;\r
+ vuint16_t BE_SOFT:1;\r
+ vuint16_t BE_CORE:1;\r
+ vuint16_t BE_JTAG:1;\r
+ } B;\r
+ } FBRE;\r
+\r
+}; /* end of RGM_tag */\r
+/****************************************************************************/\r
+/* MODULE : PCU (base address 0xC3FE_8000) */\r
+/****************************************************************************/\r
+struct PCU_tag{\r
+\r
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RST:1;\r
+ } B;\r
+ } PCONF[4];\r
+\r
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */\r
+\r
+ union { /* PCU Power Domain Status (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t PD3:1;\r
+ vuint32_t PD2:1;\r
+ vuint32_t PD1:1;\r
+ vuint32_t PD0:1;\r
+ } B;\r
+ } PSTAT;\r
+\r
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */\r
+\r
+\r
+ /* Following register is from Voltage Regulators chapter of RM */\r
+\r
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t MASK_LVDHV5:1;\r
+ } B;\r
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */\r
+\r
+ }; /* end of PCU_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CTU Lite(base address - 0xFFE6_4000) */\r
+/****************************************************************************/\r
+struct CTUL_tag{\r
+\r
+ // union { /* CTU Control Status Register (Base+0x0000)NOT PRESENT WITHIN RM*/\r
+ // vuint32_t R;\r
+ // struct {\r
+ // vuint32_t :24;\r
+ // vuint32_t TRGIEN:1;\r
+ // vuint32_t TRGI:1;\r
+ // vuint32_t :6;\r
+ // } B;\r
+ // } CSR;\r
+\r
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */\r
+\r
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TM:1;\r
+ vuint32_t CLR_FLAG:1;\r
+ vuint32_t :5;\r
+ vuint32_t ADC_SEL:1;\r
+ vuint32_t :1;\r
+ vuint32_t CHANNEL_VALUE:7;\r
+ } B;\r
+ } EVTCFGR[64];\r
+\r
+\r
+}; /* end of CTUL_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */\r
+/****************************************************************************/\r
+\r
+struct EMIOS_CHANNEL_tag{\r
+\r
+ union { /* Channel A Data (UCn Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t A:16;\r
+ } B;\r
+ } CADR;\r
+\r
+ union { /* Channel B Data (UCn Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t B:16;\r
+ } B;\r
+ } CBDR;\r
+\r
+ union { /* Channel Counter (UCn Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t C:16;\r
+ } B;\r
+ } CCNTR;\r
+\r
+ union { /* Channel Control (UCn Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t :3;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPEN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t :1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t :3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t :1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* Channel Status (UCn Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t :15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t :12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR;\r
+\r
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ALTA:16;\r
+ } B;\r
+ } ALTCADR;\r
+\r
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */\r
+\r
+}; /* end of EMIOS_CHANNEL_tag */\r
+\r
+\r
+struct EMIOS_tag{\r
+\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t :1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t :10;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t :8;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Global Flag (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t F31:1;\r
+ vuint32_t F30:1;\r
+ vuint32_t F29:1;\r
+ vuint32_t F28:1;\r
+ vuint32_t F27:1;\r
+ vuint32_t F26:1;\r
+ vuint32_t F25:1;\r
+ vuint32_t F24:1;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR;\r
+\r
+ union { /* Output Update Disable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OU31:1;\r
+ vuint32_t OU30:1;\r
+ vuint32_t OU29:1;\r
+ vuint32_t OU28:1;\r
+ vuint32_t OU27:1;\r
+ vuint32_t OU26:1;\r
+ vuint32_t OU25:1;\r
+ vuint32_t OU24:1;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR;\r
+\r
+ union { /* Disable Channel (Base+0x000F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CHDIS31:1;\r
+ vuint32_t CHDIS30:1;\r
+ vuint32_t CHDIS29:1;\r
+ vuint32_t CHDIS28:1;\r
+ vuint32_t CHDIS27:1;\r
+ vuint32_t CHDIS26:1;\r
+ vuint32_t CHDIS25:1;\r
+ vuint32_t CHDIS24:1;\r
+ vuint32_t CHDIS23:1;\r
+ vuint32_t CHDIS22:1;\r
+ vuint32_t CHDIS21:1;\r
+ vuint32_t CHDIS20:1;\r
+ vuint32_t CHDIS19:1;\r
+ vuint32_t CHDIS18:1;\r
+ vuint32_t CHDIS17:1;\r
+ vuint32_t CHDIS16:1;\r
+ vuint32_t CHDIS15:1;\r
+ vuint32_t CHDIS14:1;\r
+ vuint32_t CHDIS13:1;\r
+ vuint32_t CHDIS12:1;\r
+ vuint32_t CHDIS11:1;\r
+ vuint32_t CHDIS10:1;\r
+ vuint32_t CHDIS9:1;\r
+ vuint32_t CHDIS8:1;\r
+ vuint32_t CHDIS7:1;\r
+ vuint32_t CHDIS6:1;\r
+ vuint32_t CHDIS5:1;\r
+ vuint32_t CHDIS4:1;\r
+ vuint32_t CHDIS3:1;\r
+ vuint32_t CHDIS2:1;\r
+ vuint32_t CHDIS1:1;\r
+ vuint32_t CHDIS0:1;\r
+ } B;\r
+ } UCDIS;\r
+\r
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */\r
+\r
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */\r
+\r
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */\r
+\r
+}; /* end of EMIOS_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : PIT (base address - 0xC3FF_FFFF) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+\r
+ union { /* PIT Module Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } PITMCR;\r
+\r
+ vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */\r
+\r
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */\r
+ struct {\r
+\r
+ union { /* PIT Timer Load Value (Offset+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } LDVAL;\r
+\r
+ union { /* PIT Current Timer Value (Offset+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } CVAL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG;\r
+\r
+ }CH[8]; /* End of PIT Timer Channels */\r
+\r
+}; /* end of PIT_tag */\r
+/****************************************************************************/\r
+/* MODULE : I2C (base address - 0xFFE3_0000) */\r
+/****************************************************************************/\r
+struct I2C_tag{\r
+\r
+ union { /* I2C Bus Address (Base+0x0000) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ADR:7;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBAD;\r
+\r
+ union { /* I2C Bus Frequency Divider (Base+0x0001) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t IBC:8;\r
+ } B;\r
+ } IBFD;\r
+\r
+ union { /* I2C Bus Control (Base+0x0002) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t MDIS:1;\r
+ vuint8_t IBIE:1;\r
+ vuint8_t MS:1; /*different from RM for backward compatiblity MSSL in RM*/ \r
+ vuint8_t TX:1;\r
+ vuint8_t NOACK:1;\r
+ vuint8_t RSTA:1;\r
+ vuint8_t DMAEN:1;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBCR;\r
+\r
+ union { /* I2C Bus Status (Base+0x0003) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t TCF:1;\r
+ vuint8_t IAAS:1;\r
+ vuint8_t IBB:1;\r
+ vuint8_t IBAL:1;\r
+ vuint8_t :1;\r
+ vuint8_t SRW:1;\r
+ vuint8_t IBIF:1;\r
+ vuint8_t RXAK:1;\r
+ } B;\r
+ } IBSR;\r
+\r
+ union { /* I2C Bus Data I/O (Base+0x0004) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DATA:8;\r
+ } B;\r
+ } IBDR;\r
+\r
+ union { /* I2C Interrupt Configuration (Base+0x0005) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t BIIE:1;\r
+ vuint8_t :7;\r
+ } B;\r
+ } IBIC;\r
+\r
+ vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */\r
+\r
+}; /* end of i2c_tag */\r
+/****************************************************************************/\r
+/* MODULE : MPU (base address - 0xFFF1_0000) */\r
+/****************************************************************************/\r
+ struct MPU_tag {\r
+\r
+ union { /* Control/Error Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t SPERR:3;\r
+ vuint32_t:4;\r
+ vuint32_t HRL:4;\r
+ vuint32_t NSP:4;\r
+ vuint32_t NGRD:4;\r
+ vuint32_t :7;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } CESR;\r
+\r
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */\r
+\r
+\r
+ union { /* Error Address Slave Port0 (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR0;\r
+\r
+ union { /* Error Detail Slave Port0 (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR0;\r
+\r
+\r
+ union { /* Error Address Slave Port1 (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR1;\r
+\r
+ union { /* Error Detail Slave Port1 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR1;\r
+\r
+\r
+ union { /* Error Address Slave Port2 (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR2;\r
+\r
+ union { /* Error Detail Slave Port2 (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR2;\r
+\r
+ vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */\r
+\r
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */\r
+\r
+ union { /* - Word 0 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SRTADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD0;\r
+\r
+ union { /* - Word 1 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENDADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD1;\r
+\r
+ union { /* - Word 2 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } WORD2;\r
+\r
+ union { /* - Word 3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PID:8;\r
+ vuint32_t PIDMASK:8;\r
+ vuint32_t :15;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } WORD3;\r
+\r
+ }RGD[8]; /* End of Region Descriptor Structure) */\r
+\r
+ vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */\r
+\r
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } RGDAAC[8];\r
+\r
+ vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */\r
+\r
+}; /* end of MPU_tag */\r
+/****************************************************************************/\r
+/* MODULE : eDMA (base address - 0xFFF4_4000) */\r
+/****************************************************************************/\r
+\r
+ /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */\r
+ struct EDMA_TCD_STD_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_STD_tag */\r
+\r
+ /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/\r
+ struct EDMA_TCD_CHLINK_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (?major?) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_CHLINK_tag */\r
+\r
+\r
+\r
+struct EDMA_tag {\r
+\r
+ union { /* Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t CX:1;\r
+ vuint32_t ECX:1;\r
+ vuint32_t :6; \r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t EMLM:1;\r
+ vuint32_t CLM:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t HOE:1;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* Error Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t :16;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/\r
+\r
+ union { /* Enable Request Low Ch15..0 (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL;\r
+\r
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/\r
+\r
+ union { /* Enable Error Interrupt Low (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL;\r
+\r
+ union { /* DMA Set Enable Request (Base+0x0018) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SERQ:7;\r
+ } B;\r
+ } SERQR;\r
+\r
+ union { /* DMA Clear Enable Request (Base+0x0019) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERQ:7;\r
+ } B;\r
+ } CERQR;\r
+\r
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SEEI:7;\r
+ } B;\r
+ } SEEIR;\r
+\r
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:1;\r
+ vuint8_t CEEI:7;\r
+ } B;\r
+ } CEEIR;\r
+\r
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CINT:7;\r
+ } B;\r
+ } CIRQR;\r
+\r
+ union { /* DMA Clear error (Base+0x001D) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERR:7;\r
+ } B;\r
+ } CER;\r
+\r
+ union { /* DMA Set Start Bit (Base+0x001E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t NOP:1;\r
+ vuint8_t SSB:7;\r
+ } B;\r
+ } SSBR;\r
+\r
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CDSB:7;\r
+ } B;\r
+ } CDSBR;\r
+\r
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/\r
+\r
+ union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL;\r
+\r
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/\r
+\r
+ union { /* DMA Error Low Ch15..0 (Base+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL;\r
+\r
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/\r
+\r
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t HRS15:1;\r
+ vuint32_t HRS14:1;\r
+ vuint32_t HRS13:1;\r
+ vuint32_t HRS12:1;\r
+ vuint32_t HRS11:1;\r
+ vuint32_t HRS10:1;\r
+ vuint32_t HRS09:1;\r
+ vuint32_t HRS08:1;\r
+ vuint32_t HRS07:1;\r
+ vuint32_t HRS06:1;\r
+ vuint32_t HRS05:1;\r
+ vuint32_t HRS04:1;\r
+ vuint32_t HRS03:1;\r
+ vuint32_t HRS02:1;\r
+ vuint32_t HRS01:1;\r
+ vuint32_t HRS00:1;\r
+ } B;\r
+ } HRSL;\r
+\r
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/\r
+\r
+ union { /* Channel n Priority (Base+0x0100-0x010F)*/\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+ vuint8_t DPA:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+ } B;\r
+ } CPR[16];\r
+\r
+ vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */\r
+\r
+ /* Transfer Control Descriptors 0..16 (Base+0x1000-0x11E0) */\r
+ struct EDMA_TCD_STD_tag TCD[16];\r
+ \r
+ /* or change to following if using channel linking */\r
+ /* Struct EDMA_TCD_CHLINK_tag TCD[16]; */\r
+ \r
+ vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */\r
+\r
+}; /* end of EDMA_tag */\r
+/*************************************************************************/\r
+/* MODULE : INTC (base address - 0xFFF4_8000) */\r
+/*************************************************************************/\r
+struct INTC_tag {\r
+\r
+ union { /* INTC Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* INTC Current Priority (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR;\r
+ \r
+ vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* INTC Interrupt Acknowledge (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC0:21;\r
+ vuint32_t INTVEC_PRC0:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR;\r
+\r
+ vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */\r
+ \r
+ union { /* INTC End Of Interrupt (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR;\r
+\r
+ vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */\r
+ \r
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8];\r
+\r
+ vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */\r
+\r
+ union { /* INTC Priority Select (Base+0x0040-0x0128) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[234]; \r
+\r
+}; /* end of INTC_tag */\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/* Base Addresses: */\r
+/* DSPI_0 - 0xFFF9_0000 */\r
+/* DSPI_1 - 0xFFF9_4000 */\r
+/* DSPI_2 - 0xFFF9_8000 */\r
+/* DSPI_3 - 0xFFF9_C000 */\r
+/* DSPI_4 - 0xFFFA_0000 */\r
+/* DSPI_5 - 0xFFFA_4000 */\r
+/****************************************************************************/\r
+struct DSPI_tag{\r
+\r
+ union { /* DSPI Module Configuraiton (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t :2; \r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1; \r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t :7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* DSPI Transfer Count (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[6];\r
+\r
+ vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */\r
+\r
+ union { /* DSPI Status (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t :1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t :5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t :2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t :4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t :16;\r
+ } B;\r
+ } RSER;\r
+\r
+ union { /* DSPI Push TX FIFO (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t :4; \r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR;\r
+\r
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } POPR;\r
+\r
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t TXCMD:16; \r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4];\r
+\r
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */\r
+\r
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } RXFR[4];\r
+ }; /* end of DSPI_tag */\r
+ /****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/* Base Addresses: */\r
+/* FlexCAN_0 - 0xFFFC_0000 */\r
+/* FlexCAN_1 - 0xFFFC_4000 */\r
+/* FlexCAN_2 - 0xFFFC_8000 */\r
+/* FlexCAN_3 - 0xFFFC_C000 */\r
+/* FlexCAN_4 - 0xFFFD_0000 */\r
+/* FlexCAN_5 - 0xFFFD_4000 */\r
+/****************************************************************************/\r
+struct FLEXCAN_BUF_t{\r
+\r
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t :1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRIO:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+}; /* end of FLEXCAN_BUF_t */\r
+\r
+\r
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */\r
+\r
+ union { /* RxFIFO Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :9;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* RxFIFO Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/\r
+\r
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */\r
+ vuint32_t R;\r
+ } IDTABLE[8];\r
+\r
+}; /* end of FLEXCAN_RXFIFO_t */\r
+\r
+\r
+struct FLEXCAN_tag{\r
+\r
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t WAKMSK:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t SUPV:1;\r
+ vuint32_t SLFWAK:1; /*not present in RM*/\r
+ vuint32_t WRNEN:1;\r
+ vuint32_t LPMACK:1;\r
+ vuint32_t WAKSRC:1;\r
+ vuint32_t DOZE:1; /*not present in RM*/\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t BCC:1;\r
+ vuint32_t:2;\r
+ vuint32_t LPRIO_EN:1;\r
+ vuint32_t AEN:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDAM:2;\r
+ vuint32_t:2;\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* FLEXCAN Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TIMER:16;\r
+ } B;\r
+ } TIMER;\r
+\r
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXGMASK;\r
+\r
+ /* --- Following 2 registers are included for legacy purposes only --- */\r
+\r
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX14MASK;\r
+\r
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX15MASK;\r
+\r
+ /* --- */\r
+\r
+ union { /* FLEXCAN Error Counter (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR;\r
+\r
+ union { /* FLEXCAN Error & Status (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t :1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t :1;\r
+ } B;\r
+ } ESR;\r
+\r
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH;\r
+\r
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL;\r
+\r
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH;\r
+\r
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/\r
+\r
+/****************************************************************************/\r
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */\r
+/****************************************************************************/\r
+ /* Standard Buffer Structure */\r
+ struct FLEXCAN_BUF_t BUF[64];\r
+\r
+ /* RX FIFO and Buffer Structure */\r
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */\r
+ /*struct FLEXCAN_BUF_t BUF[56]; */\r
+/****************************************************************************/\r
+\r
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/\r
+\r
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXIMR[64];\r
+\r
+}; /* end of FLEXCAN_tag */\r
+/****************************************************************************/\r
+/* MODULE : DMAMUX (base address - 0xFFFD_C000) */\r
+/****************************************************************************/\r
+ struct DMAMUX_tag {\r
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBL:1;\r
+ vuint8_t TRIG:1;\r
+ vuint8_t SOURCE:6;\r
+ } B;\r
+ } CHCONFIG[16]; \r
+\r
+ }; /* end of DMAMUX_tag */\r
+/****************************************************************************/\r
+/* MODULE : DFLASH (base address - 0x0080_0000) */\r
+/****************************************************************************/\r
+ struct DFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address block locking (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :25;\r
+ vuint32_t HBLOCK:6;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address space block sel (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t HSL:6;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ vuint8_t DFLASH_reserved0[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+\r
+ }; /* end of Dflash_tag */\r
+/****************************************************************************/\r
+/* MODULE : CFLASH (base address - 0xC3F8_8000) */\r
+/****************************************************************************/\r
+ struct CFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address space block locking (Base+0x0008)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :19;\r
+ vuint32_t HBLOCK:12;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address Space block select (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t HSL:12;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */\r
+ /* the code flash configuraiton PFCR[0..2] registers */\r
+ /* To make it easier to code, the BIU registers have been */\r
+ /* replaced with the PFCR registers in this header file! */\r
+ /* A commented out BIU register is shown for reference! */\r
+\r
+\r
+ union { /* CFLASH Configuration 0 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK0_APC:5;\r
+ vuint32_t BK0_WWSC:5;\r
+ vuint32_t BK0_RWSC:5;\r
+ vuint32_t BK0_RWWC2:1;\r
+ vuint32_t BK0_RWWC1:1;\r
+ /* vuint32_t B0_P1_BCFG:2; // only has one port to the cross bar i.e. port 0 \r
+ vuint32_t B0_P1_DPFE:1;\r
+ vuint32_t B0_P1_IPFE:1;\r
+ vuint32_t B0_P1_PFLM:2;\r
+ vuint32_t B0_P1_BFE:1; */\r
+ vuint32_t :7;\r
+ vuint32_t BK0_RWWC0:1;\r
+ vuint32_t B0_P0_BCFG:2;\r
+ vuint32_t B0_P0_DPFE:1;\r
+ vuint32_t B0_P0_IPFE:1;\r
+ vuint32_t B0_P0_PFLM:2;\r
+ vuint32_t B0_P0_BFE:1;\r
+ } B;\r
+ } PFCR0;\r
+ \r
+/* Commented out Bus Interface Unit 0 (Base+0x001C) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI0:32;\r
+ } B;\r
+ } BIU0; */\r
+\r
+ union { /* CFLASH Configuration Register 1 (Base+0x0020)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK1_APC:5;\r
+ vuint32_t BK1_WWSC:5;\r
+ vuint32_t BK1_RWSC:5;\r
+ vuint32_t BK1_RWWC2:1;\r
+ vuint32_t BK1_RWWC1:1;\r
+ vuint32_t:7; /* changed to 7 to suit comment below */\r
+ //vuint32_t B1_P1_BFE:1; /* should have no effect, there is only one XBAR port (no P1) to P-flash controller */ \r
+ vuint32_t BK1_RWWC0:1;\r
+ vuint32_t:6;\r
+ vuint32_t B1_P0_BFE:1;\r
+ } B;\r
+ } PFCR1;\r
+ \r
+/* Commented out Bus Interface Unit 1 (Base+0x0020) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI1:32;\r
+ } B;\r
+ } BIU1; */\r
+\r
+ union { /* CFLASH Access Protection (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6; /*incorrect - B1M/B1.5M does not have this many masters TBD*/ \r
+ vuint32_t ARBM:2;\r
+ vuint32_t M7PFD:1;\r
+ vuint32_t M6PFD:1;\r
+ vuint32_t M5PFD:1;\r
+ vuint32_t M4PFD:1;\r
+ vuint32_t M3PFD:1;\r
+ vuint32_t M2PFD:1;\r
+ vuint32_t M1PFD:1;\r
+ vuint32_t M0PFD:1;\r
+ vuint32_t M7AP:2;\r
+ vuint32_t M6AP:2;\r
+ vuint32_t M5AP:2;\r
+ vuint32_t M4AP:2;\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } PFAPR;\r
+ \r
+/* Commented out Bus Interface Unit 2 (Base+0x0024) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI2:32;\r
+ } B;\r
+ } BIU2; */\r
+\r
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+ \r
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/\r
+\r
+ }; /* end of CFLASH_tag */\r
+/****************************************************************** \r
+| defines and macros (scope: module-local) \r
+|-----------------------------------------------------------------*/\r
+/* Define instances of modules */\r
+\r
+#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)\r
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)\r
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)\r
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)\r
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)\r
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)\r
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)\r
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)\r
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)\r
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)\r
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)\r
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)\r
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)\r
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)\r
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)\r
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)\r
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)\r
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)\r
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)\r
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)\r
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) \r
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)\r
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)\r
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)\r
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)\r
+#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)\r
+#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)\r
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)\r
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)\r
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)\r
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)\r
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)\r
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)\r
+#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)\r
+#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)\r
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)\r
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)\r
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)\r
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)\r
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)\r
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)\r
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)\r
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)\r
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)\r
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)\r
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)\r
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif \r
+/* End of file */\r
.name = "MPC5604B",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
.name = "MPC5604B",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;\r
// Connect SYSCLK to FMPLL\r
SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;\r
-#elif defined(CFG_MPC5604B)\r
+#elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)\r
// Write pll parameters.\r
CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;\r
CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;\r
ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */\r
ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */\r
ME.PCTL[32].R = 0x01; //ADC0 control\r
+#if defined(CFG_MPC5606B)\r
+ ME.PCTL[33].R = 0x01; //ADC1 control\r
+#endif\r
ME.PCTL[23].R = 0x01; //DMAMUX control\r
ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
while(ME.GS.B.S_CURRENTMODE != 4) {}\r
\r
CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
\r
SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */\r
SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */\r
while(ME.GS.B.S_CURRENTMODE != 4) {}\r
\r
CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
// Partially following the steps in MPC5567 RM..\r
void Mcu_DistributePllClock(void)\r
{\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
#elif defined(CFG_MPC5606S)\r
VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
\r
if( !SIMULATOR() )\r
{\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if ( !CGM.FMPLL_CR.B.S_LOCK )\r
{\r
rv = MCU_PLL_UNLOCKED;\r
\r
//-------------------------------------------------------------------\r
\r
-void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+/**\r
+ *\r
+ * Application Notes!\r
+ * - AN3584, "MPC5510 Family Low Power Features"\r
+ * Since it's not complete also check MPC5668\r
+ * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code\r
+ *\r
+ *\r
+ * @param LPM\r
+ */\r
+static void enterLowPower (Mcu_ModeType mcuMode )\r
+{\r
+ uint32 timeout;\r
+ /* Set the sleep bit; following a WAIT instruction, the device will go to sleep */\r
+ CRP.PSCR.B.SLEEP = 1;\r
+ /* enable the 1.2V internal regulator when in sleep mode only */\r
+ CRP.PSCR.B.STOP12EN = 1;\r
+ /* 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power */\r
+ CRP.PSCR.B.RAMSEL = 0x7; // Keep all 80K\r
+\r
+ CRP.Z1VEC.R = (uint32)&McuE_LowPowerRecoverFlash;\r
+#if defined(CFG_VLE)\r
+ CRP.VLE = 1;\r
+#endif\r
+\r
+ /* If we "Mcu_Wakeup()" is located in RAM, set FASTREC */\r
+ CRP.RECPRTR.B.FASTREC = 0;\r
+\r
+ /* Halt everything */\r
+ SIU.HLT.R = 0x3FFFFFFF;\r
+ while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout<3000)) {}\r
+\r
+ /* put Z0 in reset if not used for wakeup */\r
+ CRP.Z0VEC.B.Z0RST = 1;\r
+\r
+ // TODO: Enable_all_internal_pull_devices (PULL_DOWN);\r
+\r
+ /* Save context and execute wait instruction.\r
+ *\r
+ * Things that matter here are\r
+ * - Z1VEC, determines where TLB0 will point. TLB0 is written with a\r
+ * value at startup that 4K aligned to this address.\r
+ * - LowPower_Sleep() will save a interrupt context so we will return\r
+ * intact.\r
+ * - For devices with little RAM we don't want to impose the alignment\r
+ * requirements there. Almost as we have to occupy a 4K block for this..\r
+ * although the code does not take that much space.\r
+ * */\r
+ McuE_EnterLowPower(mcuMode);\r
+\r
+ /* Clear sleep flags to allow pads to operate */\r
+ CRP.PSCR.B.SLEEPF = 0x1;\r
+\r
+\r
+}\r
+\r
+\r
+void Mcu_SetMode( Mcu_ModeType mcuMode)\r
{\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
// VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
- (void) McuMode;\r
\r
+\r
+#if defined(CFG_MPC5516)\r
+ if( MCU_MODE_RUN == mcuMode ) {\r
+\r
+ } else if( MCU_MODE_SLEEP == mcuMode ) {\r
+ /*\r
+ * Follows the AN3548 from Freescale\r
+ *\r
+ */\r
+#if defined(USE_DMA)\r
+ Dma_StopAll();\r
+#endif\r
+\r
+\r
+ /* Set system clock to 16Mhz IRC */\r
+ SIU.SYSCLK.B.SYSCLKSEL = 0;\r
+\r
+ /* Put flash in low-power mode */\r
+ // TODO\r
+\r
+ /* Put QQADC in low-power mode */\r
+ // TODO\r
+\r
+ /* Set us in SLEEP mode */\r
+ CRP.PSCR.B.SLEEP = 1;\r
+\r
+\r
+ enterLowPower(mcuMode);\r
+ }\r
+#else\r
/* NOT SUPPORTED */\r
+ (void) McuMode;\r
+#endif\r
}\r
\r
//-------------------------------------------------------------------\r
uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
-#elif defined(CFG_MPC5604B)\r
+#elif defined(CFG_MPC560XB)\r
uint32_t eprediv = CGM.FMPLL_CR.B.IDF;\r
uint32_t emfd = CGM.FMPLL_CR.B.NDIV;\r
uint32_t erfd = CGM.FMPLL_CR.B.ODF;\r
case PERIPHERAL_CLOCK_DSPI_B:\r
case PERIPHERAL_CLOCK_DSPI_C:\r
case PERIPHERAL_CLOCK_DSPI_D:\r
+ case PERIPHERAL_CLOCK_DSPI_E:\r
+ case PERIPHERAL_CLOCK_DSPI_F:\r
#if defined(CFG_MPC5516)\r
prescaler = SIU.SYSCLK.B.LPCLKDIV3;\r
break;\r
#if defined(CFG_MPC560X)\r
case PERIPHERAL_CLOCK_LIN_A:\r
case PERIPHERAL_CLOCK_LIN_B:\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
case PERIPHERAL_CLOCK_LIN_C:\r
case PERIPHERAL_CLOCK_LIN_D:\r
#endif\r
--- /dev/null
+#define _ASSEMBLER_\r
+#include "asm_ppc.h"\r
+\r
+\r
+#if defined(__CWCC__) && defined(CFG_VLE)\r
+.section .text_vle,text_vle\r
+#elif defined(__DCC__)\r
+ // Must be indented (diab)\r
+ .section .text_vle,x\r
+#elif defined(__GNUC__)\r
+.section .text\r
+#endif\r
+\r
+\r
+#define CRP_RECPTR 0xfffec058\r
+\r
+ .global McuE_EnterLowPower\r
+ \r
+McuE_EnterLowPower:\r
+ subi r1, r1, 0x94 // Allocate space on stack 0x94 = 148 r2--r31 + 7 SPRs\r
+ stmw r2, 0(r1) // Save registers r2-r31 to stack\r
+ mfSRR1 r25\r
+ mfSRR0 r26\r
+ mfLR r27\r
+ mfmsr r28\r
+ mfCR r29\r
+ mfXER r30\r
+ mfCTR r31\r
+ stmw r25, 0x78(r1) // Store SPR data to stack\r
+ \r
+ LOAD_ADDR_32(r4,CRP_RECPTR)\r
+ stw r1,0x0(r4) // Save stack pointer to CRP to be preserved during LPM\r
+ \r
+/* Note! You cannot step over the wait instruction with the debugger */ \r
+ \r
+ .long 0x7C00007C // Wait instruction\r
+ \r
+ \r
+ blr\r
+\r
+\r
+/*\r
+ * Low Power Vector...needs to be on 4K + 0xffc\r
+ * We only have 1 instruction before we are outside TLB0 so just jump\r
+ */\r
+#if defined(__GNUC__) \r
+.section ".lowpower_vector","ax"\r
+#elif defined(__CWCC__)\r
+#if defined(CFG_VLE)\r
+.section .lowpower_vector,text_vle\r
+#else\r
+.section .lowpower_vector,4,"rw"\r
+#endif\r
+#elif defined(__DCC__)\r
+ .section .text_vle,x\r
+#endif\r
+\r
+ .global McuE_LowPowerVector\r
+\r
+McuE_LowPowerVector:\r
+ b McuE_LowPowerRecoverFlash\r
+ \r
+\r
+#if defined(__GNUC__) \r
+.section ".lowpower_text","ax"\r
+#elif defined(__CWCC__)\r
+#if defined(CFG_VLE)\r
+.section .lowpower_text,text_vle\r
+#else\r
+.section .lowpower_text,4,"rw"\r
+#endif\r
+#elif defined(__DCC__)\r
+ .section .text_vle,x\r
+#endif\r
+\r
+ .extern EcuM_CheckWakeup\r
+ .global McuE_LowPowerRecoverFlash\r
+\r
+/*\r
+ * When we come back here only TLB0 is setup for flash and then only 4K.\r
+ *\r
+ * Debuggers:\r
+ * - WinIDEA : Hardware->Emulation Options->CPU Setup->MPC55xx->Low Power Debug\r
+ * This will make the debugger stop on the function below.\r
+ * - UDE: No support for this yet. It just runs through the "wait" instruction. \r
+ */ \r
+McuE_LowPowerRecoverFlash:\r
+ \r
+ bl cfg_MMU\r
+ \r
+/* Recover the stack */\r
+ LOAD_ADDR_32(r4,CRP_RECPTR)\r
+ lwz r1,0x0(r4) // Restore stack pointer from CRP\r
+ lmw r25,0x78(r1) // Load SPR values back into GPRs\r
+ mtSRR1 r25\r
+ mtSRR0 r26\r
+ mtLR r27\r
+ mtmsr r28\r
+ mtCR r29\r
+ mtXER r30\r
+ mtCTR r31 // Load SPRs with GPR values\r
+ lmw r2, 0(r1) // Restore GPRs from stack\r
+ addi r1,r1,0x94 // Deallocate space on stack\r
+\r
+#if defined(USE_ECUM)\r
+\r
+ /* We have no idea what made us wakeup, pass all */\r
+ LOAD_ADDR_32(r3,0x3fffffff); // EcuM_WakeupSourceType\r
+ bl EcuM_CheckWakeup\r
+\r
+#endif\r
+\r
+\r
+\r
+ /* branch back to Mcu_SetMode().. */\r
+ blr\r
+ \r
+ \r
+ #if defined(CFG_VLE)\r
+ #define VLE_VAL MAS2_VLE\r
+ #else\r
+ #define VLE_VAL 0\r
+ #endif\r
+\r
+#if defined(CFG_MPC5516)\r
+#define SRAM_START 0x40000000\r
+#define FLASH_START 0x00000000\r
+#define PERIPHERAL_START 0xfff00000\r
+#else\r
+#error No support for this MCU\r
+#endif\r
+\r
+ \r
+ cfg_MMU:\r
+\r
+#***************************************************/\r
+# setup MMU */\r
+#***************************************************/\r
+\r
+#TLB Entry 0 = 1M Internal flash \r
+ LOAD_ADDR_32(5, 0x10000000 + (0<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_4M )\r
+ mtspr SPR_MAS1,r5 \r
+ LOAD_ADDR_32(5, FLASH_START + VLE_VAL )\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, FLASH_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+\r
+\r
+#TLB Entry 1 = Peripheral bridge and BAM\r
+ LOAD_ADDR_32(5, 0x10000000 + (1<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_1M)\r
+ mtspr SPR_MAS1,r5\r
+ LOAD_ADDR_32(5, PERIPHERAL_START + VLE_VAL + MAS2_I)\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, PERIPHERAL_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+\r
+\r
+#TLB Entry 2 = External RAM. Skip this. \r
+\r
+#TLB Entry 3 = Internal SRAM\r
+ LOAD_ADDR_32(5, 0x10000000+(3<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_256K )\r
+ mtspr SPR_MAS1,r5 \r
+ LOAD_ADDR_32(5, SRAM_START + VLE_VAL )\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, SRAM_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+ blr\r
+ \r
+ \r
+\r
+\r
SIU.PCR[i].R = configType->padConfig[i];\r
++i;\r
\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if(32 == i || 33 == i) i=34;\r
if(121 == i || 122 == i) i=123;\r
#elif defined(CFG_MPC5606S)\r
Irq_Restore(state); // Restore interrupts\r
pcrPtr++;\r
padCfgPtr++;\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if(32 == i)\r
{\r
i=34;\r
#if defined(CFG_MPC5604B)\r
#define PWM_RUNTIME_CHANNEL_COUNT 56\r
#define CHANNELS_OK (Channel <= PWM_MAX_CHANNEL-1)\r
+#elif defined(CFG_MPC5606B)\r
+ #define PWM_RUNTIME_CHANNEL_COUNT 64\r
+ #define CHANNELS_OK (Channel <= PWM_MAX_CHANNEL-1)\r
#elif defined(CFG_MPC5606S)\r
#define PWM_RUNTIME_CHANNEL_COUNT 48\r
#define CHANNELS_OK (((Channel <= PWM_MAX_CHANNEL-1) && (Channel >= 40)) || ((Channel <= 23) && (Channel >= 16)))\r
return;\r
}\r
\r
- #if defined(CFG_MPC5606S) && !defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC5606S) && !defined(CFG_MPC560XB)\r
CGM.AC1_SC.R = 0x03000000; /* MPC56xxS: Select aux. set 1 clock to be FMPLL0 */\r
CGM.AC2_SC.R = 0x03000000; /* MPC56xxS: Select aux. set 2 clock to be FMPLL0 */\r
#endif\r
// Pwm_DisableNotification(channel);\r
\r
// Install ISR\r
- #if defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC560XB)\r
switch(channel)\r
{\r
case 0:\r
#include "Det.h"\r
#include "isr.h"\r
/* ----------------------------[private define]------------------------------*/\r
-\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5567)\r
-#define SPI_CONTROLLER_TOTAL_CNT 4\r
-#elif defined(CFG_MPC5604B)\r
-#define SPI_CONTROLLER_TOTAL_CNT 3\r
-#elif defined(CFG_MPC560X)\r
-#define SPI_CONTROLLER_TOTAL_CNT 2\r
-#endif\r
+#define DSPI_CTRL_A 0\r
+#define DSPI_CTRL_B 1\r
+#define DSPI_CTRL_C 2\r
+#define DSPI_CTRL_D 3\r
+#define DSPI_CTRL_E 4\r
+#define DSPI_CTRL_F 5\r
\r
#if defined(CFG_MPC560X)\r
#define DSPI_A_ISR_EOQF DSPI_0_ISR_EOQF\r
#define DSPI_B_ISR_EOQF DSPI_1_ISR_EOQF\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
#define DSPI_C_ISR_EOQF DSPI_2_ISR_EOQF\r
#endif\r
+#if defined(CFG_MPC5606B)\r
+#define DSPI_D_ISR_EOQF DSPI_3_ISR_EOQF\r
+#define DSPI_E_ISR_EOQF DSPI_4_ISR_EOQF\r
+#define DSPI_F_ISR_EOQF DSPI_5_ISR_EOQF\r
+#endif\r
#endif\r
\r
#define SPIE_BAD (-1)\r
#define SPIE_OK 0\r
#define SPIE_JOB_NOT_DONE 1\r
\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
#define CTAR_CNT 6\r
#else\r
#define CTAR_CNT 8\r
.TxDmaChannel = DMA_DSPI_D_COMMAND_CHANNEL,\r
}\r
#endif\r
+#if (SPI_USE_HW_UNIT_4 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_E_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_E_COMMAND_CHANNEL,\r
+ }\r
+#endif\r
+#if (SPI_USE_HW_UNIT_5 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_F_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_F_COMMAND_CHANNEL,\r
+ }\r
+#endif\r
};\r
#endif\r
\r
\r
static void Spi_Isr(Spi_UnitType *uPtr );\r
\r
+#if (SPI_USE_HW_UNIT_0 == STD_ON )\r
static void Spi_Isr_A(void) {\r
Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_A));\r
}\r
+#endif\r
+#if (SPI_USE_HW_UNIT_1 == STD_ON )\r
static void Spi_Isr_B(void) {\r
Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_B));\r
}\r
+#endif\r
+#if (SPI_USE_HW_UNIT_2 == STD_ON )\r
static void Spi_Isr_C(void) {\r
Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_C));\r
}\r
+#endif\r
+#if (SPI_USE_HW_UNIT_3 == STD_ON )\r
static void Spi_Isr_D(void) {\r
Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_D));\r
}\r
+#endif\r
+#if (SPI_USE_HW_UNIT_4 == STD_ON )\r
+static void Spi_Isr_E(void) {\r
+ Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_E));\r
+}\r
+#endif\r
+#if (SPI_USE_HW_UNIT_5 == STD_ON )\r
+static void Spi_Isr_F(void) {\r
+ Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_F));\r
+}\r
+#endif\r
/* ----------------------------[public functions]----------------------------*/\r
\r
uint32 Spi_GetJobCnt(void);\r
*/\r
\r
switch(unit) {\r
+#if (SPI_USE_HW_UNIT_0 == STD_ON )\r
case 0:\r
perClock = PERIPHERAL_CLOCK_DSPI_A;\r
break;\r
+#endif\r
+#if (SPI_USE_HW_UNIT_1 == STD_ON )\r
case 1:\r
perClock = PERIPHERAL_CLOCK_DSPI_B;\r
break;\r
-#if (SPI_CONTROLLER_TOTAL_CNT>2)\r
+#endif\r
+#if (SPI_USE_HW_UNIT_2 == STD_ON )\r
case 2:\r
perClock = PERIPHERAL_CLOCK_DSPI_C;\r
break;\r
#endif\r
-#if (SPI_CONTROLLER_TOTAL_CNT>3)\r
+#if (SPI_USE_HW_UNIT_3 == STD_ON )\r
case 3:\r
perClock = PERIPHERAL_CLOCK_DSPI_D;\r
break;\r
#endif\r
+#if (SPI_USE_HW_UNIT_4 == STD_ON )\r
+ case 4:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_E;\r
+ break;\r
+#endif\r
+#if (SPI_USE_HW_UNIT_5 == STD_ON )\r
+ case 5:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_F;\r
+ break;\r
+#endif\r
+\r
default:\r
assert(0);\r
break;\r
\r
// Install EOFQ int..\r
switch (uPtr->hwUnit) {\r
+#if (SPI_USE_HW_UNIT_0 == STD_ON )\r
case 0:\r
ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_A_ISR_EOQF, 15, 0);\r
break;\r
+#endif\r
+#if (SPI_USE_HW_UNIT_1 == STD_ON )\r
case 1:\r
ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_B_ISR_EOQF, 15, 0);\r
break;\r
-#if (SPI_CONTROLLER_TOTAL_CNT > 2)\r
+#endif\r
+#if (SPI_USE_HW_UNIT_2 == STD_ON )\r
case 2:\r
ISR_INSTALL_ISR2("SPI_C",Spi_Isr_C, DSPI_C_ISR_EOQF, 15, 0);\r
break;\r
#endif\r
-#if (SPI_CONTROLLER_TOTAL_CNT > 3)\r
+#if (SPI_USE_HW_UNIT_3 == STD_ON )\r
case 3:\r
ISR_INSTALL_ISR2("SPI_D",Spi_Isr_D, DSPI_D_ISR_EOQF, 15, 0);\r
break;\r
+#endif\r
+#if (SPI_USE_HW_UNIT_4 == STD_ON )\r
+ case 4:\r
+ ISR_INSTALL_ISR2("SPI_E",Spi_Isr_E, DSPI_E_ISR_EOQF, 15, 0);\r
+ break;\r
+#endif\r
+#if (SPI_USE_HW_UNIT_5 == STD_ON )\r
+ case 5:\r
+ ISR_INSTALL_ISR2("SPI_F",Spi_Isr_F, DSPI_F_ISR_EOQF, 15, 0);\r
+ break;\r
#endif\r
}\r
}\r
static const Wdg_ConfigType *configWdgPtr;\r
static const Wdg_SettingsType *modeWdgConfig;\r
\r
+\r
+\r
void StartWatchdog(void)\r
{\r
#if defined(CFG_MPC5567)\r
ECSM.SWTCR.R = 0x00D8;;\r
-#elif defined(CFG_MPC560X)\r
+#elif defined(CFG_MPC560X) || defined(CFG_MPC5668)\r
SWT.CR.R = 0x8000011B;\r
#else\r
MCM.SWTCR.R = 0x00D8;\r
{\r
#if defined(CFG_MPC5567)\r
ECSM.SWTCR.R = 0x0059;;\r
- #elif defined(CFG_MPC560X)\r
+ #elif defined(CFG_MPC560X) || defined(CFG_MPC5668)\r
SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */\r
SWT.SR.R = 0x0000d928;\r
SWT.CR.R = 0x8000010A;\r
vuint32_t VALID:1;\r
vuint32_t OVERW:1;\r
vuint32_t RESULT:2;\r
+#ifdef CFG_MPC5606B\r
+ vuint32_t:4;\r
+ vuint32_t CDATA:12;\r
+#else\r
vuint32_t:6;\r
vuint32_t CDATA:10;\r
+#endif\r
} B;\r
} CDR[96]; /* Channel 0-95 Data REGISTER - 0-31, 48-63, 72-95 not supported */\r
\r
\r
/* Define memories */\r
\r
+#if 0\r
#define SRAM_START 0x40000000\r
#define SRAM_SIZE 0x10000\r
#define SRAM_END 0x4000FFFF\r
#define FLASH_START 0x0\r
#define FLASH_SIZE 0x100000\r
#define FLASH_END 0xFFFFF\r
+#endif\r
\r
/* Define instances of modules */\r
//#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)\r
\r
/* Define memories */\r
\r
+#if 0\r
#define SRAM_START 0x40000000\r
#define SRAM_SIZE 0x10000\r
#define SRAM_END 0x4000FFFF\r
#define FLASH_START 0x0\r
#define FLASH_SIZE 0x200000\r
#define FLASH_END 0x1FFFFF\r
+#endif\r
\r
/* Define instances of modules */\r
#define PBRIDGE_A (*( struct PBRIDGE_A_tag *) 0xC3F00000)\r
\r
/* Define memories */\r
\r
+#if 0\r
#define SRAM_START 0x40000000\r
#define SRAM_SIZE 0x14000\r
#define SRAM_END 0x40013FFF\r
#define FLASH_START 0x0\r
#define FLASH_SIZE 0x200000\r
#define FLASH_END 0x1FFFFF\r
+#endif\r
\r
/* Define instances of modules */\r
#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)\r
\r
/* Define memories */\r
\r
+#if 0\r
#define SRAM_START 0x40000000\r
#define SRAM_SIZE 0xC000\r
#define SRAM_END 0x4000BFFF\r
#define FLASH_START 0x0\r
#define FLASH_SIZE 0x100000\r
#define FLASH_END 0xFFFFF\r
+#endif\r
\r
/* Define instances of modules */\r
#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)\r
PIT_INT1, // 5606-60\r
PIT_INT2, // 5606-61\r
\r
- ADC_EOC_INT, // 5606-62\r
- ADC_ER_INT, // 5606-63\r
- ADC_WD_INT, // 5606-64\r
+ ADC0_EOC_INT, // 5606-62\r
+ ADC0_ER_INT, // 5606-63\r
+ ADC0_WD_INT, // 5606-64\r
\r
FLEXCAN_0_ESR_ERR_INT, // 5606-65\r
FLEXCAN_0_ESR_BOFF_INT, // 5606-66\r
LINFLEX_0_TXI, // 5606-80\r
LINFLEX_0_ERR, // 5606-81\r
\r
- RESERVED14, // 5606-82\r
- RESERVED15, // 5606-83\r
- RESERVED16, // 5606-84\r
+ ADC1_EOC_INT, // 5606-82\r
+ ADC1_ER_INT, // 5606-83\r
+ ADC1_WD_INT, // 5606-84\r
\r
FLEXCAN_1_ESR_ERR_INT, // 5606-85\r
FLEXCAN_1_ESR_BOFF_INT, // 5606-86\r
\r
PIT_INT4, // 5606-128\r
PIT_INT5, // 5606-129\r
- RESERVED43, // 5606-130\r
- RESERVED44, // 5606-131\r
+ PIT_INT6, // 5606-130\r
+ PIT_INT7, // 5606-131\r
RESERVED45, // 5606-132\r
RESERVED46, // 5606-133\r
RESERVED47, // 5606-134\r
RESERVED51, // 5606-138\r
RESERVED52, // 5606-139\r
RESERVED53, // 5606-140\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
EMIOS_0_GFR_F0_F1, // 5606-141\r
EMIOS_0_GFR_F2_F3, // 5606-142\r
EMIOS_0_GFR_F4_F5, // 5606-143\r
FLEXCAN_3_BUF_12_15, // 5606-179\r
FLEXCAN_3_BUF_16_31, // 5606-180\r
FLEXCAN_3_BUF_32_63, // 5606-181\r
- RESERVED59, // 5606-182\r
- RESERVED60, // 5606-183\r
- RESERVED61, // 5606-184\r
- RESERVED62, // 5606-185\r
- RESERVED63, // 5606-186\r
- RESERVED64, // 5606-187\r
- RESERVED65, // 5606-188\r
- RESERVED66, // 5606-189\r
+ DSPI_3_ISR_TFUF_RFOF, // 5606-182\r
+ DSPI_3_ISR_EOQF, // 5606-183\r
+ DSPI_3_ISR_TFFF, // 5606-184\r
+ DSPI_3_ISR_TCF, // 5606-185\r
+ DSPI_3_ISR_RFDF, // 5606-186\r
+ LINFLEX_4_RXI, // 5606-187\r
+ LINFLEX_4_TXI, // 5606-188\r
+ LINFLEX_4_ERR, // 5606-189\r
FLEXCAN_4_ESR_ERR_INT, // 5606-190\r
FLEXCAN_4_ESR_BOFF_INT, // 5606-191\r
\r
FLEXCAN_4_BUF_12_15, // 5606-196\r
FLEXCAN_4_BUF_16_31, // 5606-197\r
FLEXCAN_4_BUF_32_63, // 5606-198\r
- RESERVED68, // 5606-199\r
- RESERVED69, // 5606-200\r
- RESERVED70, // 5606-201\r
+ LINFLEX_5_RXI, // 5606-199\r
+ LINFLEX_5_TXI, // 5606-200\r
+ LINFLEX_5_ERR, // 5606-201\r
FLEXCAN_5_ESR_ERR_INT, // 5606-202\r
FLEXCAN_5_ESR_BOFF_INT, // 5606-203\r
RESERVED71, // 5606-204\r
FLEXCAN_5_BUF_12_15, // 5606-208\r
FLEXCAN_5_BUF_16_31, // 5606-209\r
FLEXCAN_5_BUF_32_63, // 5606-210\r
- RESERVED72, // 5606-211\r
- RESERVED73, // 5606-212\r
- RESERVED74, // 5606-213\r
- RESERVED75, // 5606-214\r
- RESERVED76, // 5606-215\r
- RESERVED77, // 5606-216\r
+ DSPI_4_ISR_TFUF_RFOF, // 5606-211\r
+ DSPI_4_ISR_EOQF, // 5606-212\r
+ DSPI_4_ISR_TFFF, // 5606-213\r
+ DSPI_4_ISR_TCF, // 5606-214\r
+ DSPI_4_ISR_RFDF, // 5606-215\r
+ LINFLEX_6_RXI, // 5606-216\r
+ LINFLEX_6_TXI, // 5606-217\r
+ LINFLEX_6_ERR, // 5606-218\r
+ DSPI_5_ISR_TFUF_RFOF, // 5606-219\r
+ DSPI_5_ISR_EOQF, // 5606-220\r
+ DSPI_5_ISR_TFFF, // 5606-221\r
+ DSPI_5_ISR_TCF, // 5606-222\r
+ DSPI_5_ISR_RFDF, // 5606-223\r
+ LINFLEX_7_RXI, // 5606-224\r
+ LINFLEX_7_TXI, // 5606-225\r
+ LINFLEX_7_ERR, // 5606-226\r
+ LINFLEX_8_RXI, // 5606-227\r
+ LINFLEX_8_TXI, // 5606-228\r
+ LINFLEX_8_ERR, // 5606-229\r
+ LINFLEX_9_RXI, // 5606-230\r
+ LINFLEX_9_TXI, // 5606-231\r
+ LINFLEX_9_ERR, // 5606-232\r
+\r
#elif defined (CFG_MPC5606S)\r
EMIOS_0_GFR_F8_F9, // 5606-141\r
EMIOS_0_GFR_F10_F11, // 5606-142\r
PERIPHERAL_CLOCK_DSPI_B,\r
PERIPHERAL_CLOCK_DSPI_C,\r
PERIPHERAL_CLOCK_DSPI_D,\r
+ PERIPHERAL_CLOCK_DSPI_E,\r
+ PERIPHERAL_CLOCK_DSPI_F,\r
#if defined(CFG_MPC560X)\r
PERIPHERAL_CLOCK_EMIOS_0,\r
PERIPHERAL_CLOCK_EMIOS_1,\r
\r
MEMORY\r
{\r
+#if defined(CFG_MPC5604B)\r
+ flash: org = 0x00000000, len = 0x00080000 \r
+#elif defined(CFG_MPC5607B)\r
+ flash: org = 0x00000000, len = 0x00180000 \r
+#else\r
flash: org = 0x00000000, len = 0x00100000 \r
+#endif\r
+#if defined(CFG_MPC5606B) \r
+ sram: org = 0x40000000, len = 0x00014000 \r
+#elif defined(CFG_MPC5607B) \r
+ sram: org = 0x40000000, len = 0x00018000 \r
+#else\r
sram: org = 0x40000000, len = 0x0000c000 \r
+#endif\r
}\r
\r
SECTIONS\r
\r
SECTIONS\r
{\r
+\r
+#if 0\r
/* __CALIB_RAM_START, __CALIB_RAM_END, __CALIB_ROM_START are needed by the a2l and the rte generator. \r
CALIBRATION_ENABLED, CALIBRATION_INITIALIZED_RAM, CALIBRATION_FLS_START are generated by rte \r
*/\r
__FLS_PROG_START__ = 0; /* Must be aligned to a sector start. */\r
#endif\r
\r
+#if !defined(CFG_BOOT)\r
.rcw __FLS_PROG_START__ : { *(.rcw) } > flash\r
-\r
-\r
+#endif\r
+#endif\r
.text :\r
{\r
+ crt0.o(.text);\r
*(.text .text.* .init .fini* .eini* .gnu.linkonce* .gnu.warning);\r
PROVIDE( btask_sup_matrix = .);\r
SORT(*)(.test_btask);\r
} > flash\r
\r
/* Read-only data section. */\r
- .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } > flash\r
+ .rodata : { \r
+ *(.rodata .rodata.* .gnu.linkonce.r.*);\r
+ *(.got.plt) *(.got)\r
+ } > flash\r
\r
/* initialized read-only small data section. */\r
.sdata2 : {\r
_SDA2_BASE_ = .; /* r2 */\r
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*);\r
*(PPC.EMB.sdata2 .PPC.EMB.sbss2)\r
+ . = ALIGN(0x10); \r
} > flash\r
\r
-\r
/* uninitialized read-only small data section. */\r
.sbss2 : {\r
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*);\r
__TEXT_END = .;\r
- . = . + ALIGN(8);\r
} > flash\r
+\r
+#if defined(CFG_MPC5516)\r
+ .McuE_LowPowerRecoverFlash 0x000ff000: {\r
+ *(.lowpower_text);\r
+ }\r
+ .lowpower_vector 0x000ffffc: {\r
+ *(.lowpower_vector);\r
+ }\r
+#endif \r
\r
\r
.data : {\r
- . = . + ALIGN(4);\r
__DATA_RAM = .; \r
*(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ . = ALIGN(0x10);\r
} > ram AT> flash\r
\r
.sdata : {\r
- . = . + ALIGN(4);\r
__SDATA_START__ = .;\r
_SDA_BASE_ = .; /* r13 */\r
*(.sdata .sdata.* .gnu.linkonce.s.*)\r
*(PPC.EMB.sdata2 .PPC.EMB.sbss2)\r
- . = . + ALIGN(8);\r
__DATA_END = .;\r
} > ram AT> flash\r
\r
_end = .;\r
} > ram\r
\r
- .got2 ALIGN(0x10): \r
- {\r
- . = . + ALIGN(16);\r
- *(.got2); \r
- . = . + ALIGN(8); \r
- } > ram\r
- .fixup : \r
- { \r
- . = . + ALIGN(16);\r
- *(.fixup);\r
- . = . + ALIGN(8); \r
- } > ram\r
.t32_outport ALIGN(0x10): \r
{ \r
*(.t32_outport); \r
} > ram\r
- \r
- .got : AT(ALIGN(LOADADDR(.sdata)+SIZEOF(.sdata),4)) \r
- { \r
- *(.got.plt) *(.got) \r
- } > ram\r
- \r
- .bss : AT(ADDR(.bss)) \r
- { \r
+ \r
+ .bss (NOLOAD) : \r
+ {\r
+ *(.got2);\r
+ *(.fixup);\r
*(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
__BSS_END = .; \r
} > ram\r
+ \r
.init_stack ALIGN(16) (NOLOAD) : \r
{ \r
__SP_END = .;\r
KEEP (*(SORT(.ctors.*)))\r
}\r
\r
-.uninit ALIGN(0x10): { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+.uninit ALIGN(0x10) (NOLOAD) : { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
\r
/* Always place last in RAM */\r
.heap ALIGN(0x4): {\r
/* __SBSS_END__ = ADDR(.sbss) + SIZEOF(.sbss); */\r
__SDATA2_START__ = ADDR(.sdata2);\r
__SBSS2_END__ = ADDR(.sbss2) + SIZEOF(.sbss2);\r
-__GOT_START__ = ADDR(.got);\r
-__GOT_END__ = ADDR(.got) + SIZEOF(.got);\r
-__GOT2_START__ = ADDR(.got2);\r
-__GOT2_END__ = ADDR(.got2) + SIZEOF(.got2);\r
-__FIXUP_START__ = ADDR(.fixup);\r
-__FIXUP_END__ = ADDR(.fixup) + SIZEOF(.fixup);\r
+//__GOT_START__ = ADDR(.got);\r
+//__GOT_END__ = ADDR(.got) + SIZEOF(.got);\r
+//__GOT2_START__ = ADDR(.got2);\r
+//__GOT2_END__ = ADDR(.got2) + SIZEOF(.got2);\r
+//__FIXUP_START__ = ADDR(.fixup);\r
+//__FIXUP_END__ = ADDR(.fixup) + SIZEOF(.fixup);\r
\r
__EXCEPT_START__ = 0x0;\r
__EXCEPT_END__ = 0x0;\r
obj-$(USE_ECUM) += EcuM.o\r
obj-$(USE_ECUM) += EcuM_Main.o\r
obj-$(USE_ECUM) += EcuM_PBcfg.o\r
+ifneq ($(filter EcuM_Callout_Stubs.o,$(obj-y)),)\r
obj-$(USE_ECUM) += EcuM_Callout_Stubs.o\r
+endif\r
obj-$(USE_ECUM)-$(CFG_ECUM_USE_SERVICE_COMPONENT) += EcuM_ServiceComponent.o\r
inc-$(USE_ECUM) += $(ROOTDIR)/system/EcuM\r
vpath-$(USE_ECUM) += $(ROOTDIR)/system/EcuM\r
# Mcu\r
obj-$(USE_MCU) += Mcu.o\r
obj-$(USE_MCU) += Mcu_Cfg.o\r
+obj-$(USE_MCU) += Mcu_Sleep.o\r
#obj-$(CFG_MPC55XX)-$(USE_MCU) += Mcu_Exceptions.o\r
\r
# Flash\r
obj-$(USE_NVM) += Crc_32.o\r
obj-$(USE_NVM) += Crc_16.o\r
\r
+# SchM, always find the include files.\r
+inc-y += $(ROOTDIR)/system/SchM\r
+vpath-$(USE_SCHM) += $(ROOTDIR)/system/SchM\r
+obj-$(USE_SCHM) += SchM.o\r
+\r
# J1939Tp\r
obj-$(USE_J1939TP) += J1939Tp.o\r
obj-$(USE_J1939TP) += J1939Tp_LCfg.o\r
#endif\r
}\r
\r
-void EcuM_OnEnterRUN(void)\r
+void EcuM_OnEnterRun(void)\r
{\r
\r
}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/3.1.5 autosar_3-1-5.xsd">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>board_mpc5516it</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="648c53b5-9641-4cd5-90c9-805eb89b6bc4">\r
+ <SHORT-NAME>board_mpc5516it</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION />\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">MPC551x</SD>\r
+ <SD GID="GENDIR">${RESOURCE_LOC}</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/board_mpc5516it/SwComposition_board_mpc5516it</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/board_mpc5516it/Dio</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/board_mpc5516it/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/board_mpc5516it/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/board_mpc5516it/EcuM</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="56574a22-5b8c-40d2-8986-8b5a121f8e21">\r
+ <SHORT-NAME>SwComposition_board_mpc5516it</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="de718a54-1bc1-4dc0-88ef-d90ecec33b7c">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Dio</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5d9a2bdf-88b2-4afa-9995-2d4c42ac303d">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="70389048-7f93-448e-8796-1cc10159fde0">\r
+ <SHORT-NAME>LED_PORT</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_D</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="bb5c5466-9542-46a1-9035-32b03ca317eb">\r
+ <SHORT-NAME>LEDS_LED4</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>52</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1cd257d5-4890-414b-948a-f7177260349d">\r
+ <SHORT-NAME>LEDS_LED5</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>53</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="fc2e1375-9142-4dda-96ba-12b7ed0c23ae">\r
+ <SHORT-NAME>LED_GRP_PTR</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannelGroup</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortMask</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortOffset</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8ab8ead7-d7be-4c84-be71-6980a8f426f6">\r
+ <SHORT-NAME>SPI_HOLD</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_G</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e7c20696-0c6d-43d7-ae7e-b2bcd26a483f">\r
+ <SHORT-NAME>SPI_A_HOLD_M95256</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>97</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7fc4cf00-edcc-4d2d-90d5-c739cdf0f2b5">\r
+ <SHORT-NAME>SPI_B_HOLD_M95256</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>102</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4603d58c-0e72-4ea9-b54a-372a4875ba53">\r
+ <SHORT-NAME>SPI_A_HOLD_S25FL016</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>101</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ee51423c-93df-4741-80cb-a5a21eb72290">\r
+ <SHORT-NAME>MISC_PORT</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_E</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="be334253-413e-4918-ac37-01546e979a20">\r
+ <SHORT-NAME>S1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">Push switch S1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
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+ <VALUE>0</VALUE>\r
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+ <VALUE>DIO_PORT_F</VALUE>\r
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+ <SHORT-NAME>OUTIN_0</SHORT-NAME>\r
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+ <SD GID="@ARCCORE_COMMENT">PF[0] Used for IoHwAb to play with</SD>\r
+ </SDG>\r
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+ </ADMIN-DATA>\r
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+ <VALUE>80</VALUE>\r
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+ <CONTAINER UUID="bb62fd40-7cc5-4a9c-882f-4187ef449007">\r
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+ <SD GID="@ARCCORE_COMMENT">PF[1] Used for IoHwAb to play with</SD>\r
+ </SDG>\r
+ </SDGS>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>81</VALUE>\r
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+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="dbfb7be7-37de-4087-b063-397be232ceea">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Mcu</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="0ab2bb62-5561-4f6c-a204-9e5452c8cc90">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuGeneralConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f21be304-420e-421a-a055-df1afa68324a">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuRamSectors</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="8dff9544-cfaa-4d5d-8ed1-bb18e658fe8e">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/board_mpc5516it/Mcu/McuModuleConfiguration/McuClockSettingConfig/EXT_REF_80MHZ</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="f1ac9efa-fe7a-4a4b-965b-719faa35a2a3">\r
+ <SHORT-NAME>EXT_REF_80MHZ</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>8000000.0</VALUE>\r
+ </FLOAT-VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEmfd</DEFINITION-REF>\r
+ <VALUE>104</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllErfd</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
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+ <CONTAINER UUID="5e7f1629-02bc-4f44-8dff-f23458377126">\r
+ <SHORT-NAME>EXT_REF_66MHZ</SHORT-NAME>\r
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+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
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+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>1.6E7</VALUE>\r
+ </FLOAT-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEprediv</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEmfd</DEFINITION-REF>\r
+ <VALUE>83</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllErfd</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
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+ <CONTAINER UUID="49b20ef4-5b28-4241-aaf7-be4837412fc5">\r
+ <SHORT-NAME>XOSC_CAN</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>8000000.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEmfd</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllErfd</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="edd643af-7788-4a0c-bf48-bf4b686db735">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ </PARAMETER-VALUES>\r
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+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="3e5897b8-4af8-4a71-9de6-f999f6a67e61">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5cf89b5f-7998-4820-a1ab-f7bcf4c4f4ef">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="1740d414-498c-4693-8228-9a7d2fba99f9">\r
+ <SHORT-NAME>Misc</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fa67df68-90a6-4771-a01d-fd93c65ac391">\r
+ <SHORT-NAME>BOOTCFG</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>50</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_OTHER</VALUE>\r
+ </ENUMERATION-VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="a0c2497b-fdfc-44d0-a538-43065b7fcabb">\r
+ <SHORT-NAME>PF[15]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">S1 Push Switch</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>95</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
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+ <CONTAINER UUID="01eab2fd-ad42-411c-8b47-e1794c7c78ba">\r
+ <SHORT-NAME>PF[0]</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>80</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2f15131f-aea1-405b-8abb-98a218ed9855">\r
+ <SHORT-NAME>SPI_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">E2 and Flash. CS1 for E2 and CS2 for flash</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="78b185c8-bdbf-4b40-a81e-c92808218492">\r
+ <SHORT-NAME>SIN_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>69</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="41f01582-bdb9-480d-b3d2-04195c6043f3">\r
+ <SHORT-NAME>SOUT_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>68</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1cbb3209-a8ed-4964-a865-3b8f74cb80b4">\r
+ <SHORT-NAME>SCK_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>67</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f9f8be22-04c1-4f11-814f-04691e066841">\r
+ <SHORT-NAME>PCS_A[1]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">CS for M95256</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>65</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="919c81e4-3daf-4548-b36c-04f1effbb0e7">\r
+ <SHORT-NAME>PCS_A[2]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">CS for S25FL016</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>64</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7e36a153-e61b-4f4b-bf48-775f94d5bb51">\r
+ <SHORT-NAME>PG[1]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">HOLD pin for E2 (pull HIGH)</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>97</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f50ff4c2-3c7e-487e-8a79-0ff0a495ed91">\r
+ <SHORT-NAME>PG[5]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">HOLD for flash( Pull HIGH)</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>101</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4c38b10d-8cb1-412b-895f-748083061775">\r
+ <SHORT-NAME>SPI_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="53c39411-5783-4024-b201-3b0787de51ea">\r
+ <SHORT-NAME>SIN_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>63</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5fe0516e-1bcd-486c-92c2-4718418ad0c1">\r
+ <SHORT-NAME>SOUT_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>62</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="153fbcb1-c546-42b2-bb43-f3dac65cdefc">\r
+ <SHORT-NAME>SCK_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>61</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ef7abd3e-6e61-44c7-9dca-bccd27f7c7d3">\r
+ <SHORT-NAME>PCS_B[0]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>60</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_SPI</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d827d96d-1eac-495d-9d91-46ff1293dc4c">\r
+ <SHORT-NAME>PG[6]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">HOLD</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>102</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="af797d85-17ae-4538-8c96-4a2d18370fa4">\r
+ <SHORT-NAME>LIN_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5b6dcf9f-f36b-49e6-b9bc-ce43b235206e">\r
+ <SHORT-NAME>TXD_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_OTHER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1144ecd1-4586-4d10-9a98-ac9d4b820c2c">\r
+ <SHORT-NAME>RXD_B</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MAX</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_OTHER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="17593bea-0e41-47dc-9100-cc417f3d8033">\r
+ <SHORT-NAME>LED</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">Should define user LEDs LD4 and LD5</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="d1303274-35c0-47d9-94ae-3d93d7cb2403">\r
+ <SHORT-NAME>PD[4]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>52</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="61034d2f-245a-4827-ae71-27f80ff1c6d4">\r
+ <SHORT-NAME>PD[5]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>53</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3ac3513f-08ba-4dbd-988f-d5cad6b86646">\r
+ <SHORT-NAME>CAN_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions">\r
+ <SD GID="@ARCCORE_COMMENT">The board just contains 1 CAN connector. Connected to CAN_A</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e9ea5a02-d2d9-4556-9a44-b982c3ac60c0">\r
+ <SHORT-NAME>CNTX_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="54c33959-51f0-4f00-9b03-a4f4abe273b3">\r
+ <SHORT-NAME>CNRX_A</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d0f52e19-2f0c-4427-802c-0af263505366">\r
+ <SHORT-NAME>SerialPort</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6d961ced-d519-4de1-89fd-f347a2efed00">\r
+ <SHORT-NAME>RXD_D</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>93</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_OTHER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="498e6f32-da69-4918-8c77-dfda63e7a3bd">\r
+ <SHORT-NAME>TXD_D</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>92</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_OTHER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="dd3a7ccd-9c9b-4d50-b7af-58afb7b9e137">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="ed211179-bf2b-4083-81b1-1053739458b0">\r
+ <SHORT-NAME>EcuM</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuM</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="b1564e99-d948-4202-85d7-1d7b516d0047">\r
+ <SHORT-NAME>EcuMGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMIncludeNvramMgr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMMainFunctionPeriod</DEFINITION-REF>\r
+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8991f1dd-8416-4401-8f7b-4859c3e2a5b0">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="8ade5dca-9412-4f57-a6bb-4d9a4c21951b">\r
+ <SHORT-NAME>User_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMUserConfig</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
# Memory + Peripherals\r
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS SPI EEP \r
# System + Communication + Diagnostic\r
-MOD_AVAIL+=CANIF CANTP LINIF COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE J1939TP\r
+MOD_AVAIL+=CANIF CANTP LINIF COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM WDGIF RTE J1939TP\r
# Network management\r
MOD_AVAIL+=COMM NM CANNM CANSM EA LINSM\r
# Additional\r
-MOD_AVAIL+= RAMLOG \r
+MOD_AVAIL+= RAMLOG SCHM\r
# CRC\r
MOD_AVAIL+=CRC32 CRC16\r
# Required modules\r
# Default cross compiler\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
\r
+# Defines\r
+def-y += SRAM_SIZE=0x14000\r
#include "mpc55xx.h"\r
#include "Mcu.h"\r
\r
-#define DSPI_CTRL_A 0\r
-#define DSPI_CTRL_B 1\r
-#define DSPI_CTRL_C 2\r
-#define DSPI_CTRL_D 3\r
-\r
/*\r
* General configuration\r
*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef WDG_CFG_H_\r
+#define WDG_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "WdgIf_Types.h"\r
+\r
+typedef struct\r
+{\r
+ uint32 ReloadValue;\r
+ uint8 ActivationBit;\r
+}Wdg_SettingsType;\r
+\r
+typedef struct\r
+{\r
+ WdgIf_ModeType Wdg_DefaultMode;\r
+ Wdg_SettingsType WdgSettingsFast;\r
+ Wdg_SettingsType WdgSettingsSlow;\r
+ Wdg_SettingsType WdgSettingsOff;\r
+}Wdg_ModeConfigType;\r
+\r
+typedef struct\r
+{\r
+ const Wdg_GeneralType *Wdg_General;\r
+ const Wdg_ModeConfigType *Wdg_ModeConfig;\r
+}Wdg_ConfigType;\r
+\r
+ extern const Wdg_GeneralType WdgGeneral;\r
+ extern const Wdg_ConfigType WdgConfig;\r
+\r
+#endif /* WDG_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Wdg.h"\r
+\r
+const Wdg_ModeConfigType WdgModeConfig =\r
+{\r
+ .Wdg_DefaultMode = WDGIF_OFF_MODE,\r
+ .WdgSettingsFast =\r
+ {\r
+ .ReloadValue = 0x200,\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsSlow =\r
+ {\r
+ .ReloadValue = 0x7D00,\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsOff =\r
+ {\r
+ .ReloadValue = 0x7D00,\r
+ .ActivationBit = 0,\r
+ },\r
+};\r
+\r
+const Wdg_GeneralType WdgGeneral =\r
+{\r
+ .Wdg_Index = 1,\r
+ .Wdg_TriggerLocationPtr = Wdg_Trigger,\r
+ .Wdg_SetModeLocationPtr = Wdg_SetMode,\r
+};\r
+\r
+\r
+const Wdg_ConfigType WdgConfig =\r
+{\r
+ .Wdg_General = &WdgGeneral,\r
+ .Wdg_ModeConfig = &WdgModeConfig,\r
+};\r
+\r
+\r
* 5517S,5516G,5516E, 64K RAM\r
* 5517G,E , 80K RAM\r
*/\r
-ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x00c000\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = SRAM_SIZE\r
\r
# Default cross compiler\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
+\r
+# Defines\r
+def-y += SRAM_SIZE=0x14000\r
* 5517S,5516G,5516E, 64K RAM\r
* 5517G,E , 80K RAM\r
*/\r
-ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = SRAM_SIZE\r
# Default cross compiler\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
\r
+# Defines\r
+def-y += SRAM_SIZE=0x14000\r
* 5517S,5516G,5516E, 64K RAM\r
* 5517G,E , 80K RAM\r
*/\r
-ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = SRAM_SIZE\r
--- /dev/null
+\r
+BOOT_IMAGE_ADDR=0x1c000\r
+BOOT_BLOB_LOAD_ADDR=0x1c100\r
+BOOT_BLOB_START_ADDR=$(BOOT_BLOB_LOAD_ADDR)\r
# CFG (y/n) macros\r
CFG=PPC BOOKE E200Z6 MPC55XX MPC5567 BRD_MPC5567QRTECH SPE\r
\r
+#CFG+=BOOT\r
+\r
# What buildable modules does this board have, \r
# default or private\r
\r
# Default cross compiler\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
\r
+# Defines\r
+def-y += SRAM_SIZE=0x14000\r
+\r
\r
VPATH += $(ROOTDIR)/examples\r
VPATH += $(ROOTDIR)/examples/$(PROJECTNAME)\r
-\r
+ \r
endif\r
\r
\r
\r
\r
\r
+\r
+\r
--- /dev/null
+\r
+# Version of build system\r
+REQUIRED_BUILD_SYSTEM_VERSION=1.0.0\r
+\r
+# Get configuration makefiles\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
+\r
+MOD_USE+= DET ECUM KERNEL RAMLOG
\ No newline at end of file
--- /dev/null
+/*\r
+* Configuration of module: Rte (Calibration_Settings.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Calibration_Settings.h */
+
+#ifndef CALIBRATION_SETTINGS_H
+#define CALIBRATION_SETTINGS_H
+
+#undef CALIBRATION_INITIALIZED_RAM
+
+#undef CALIBRATION_ENABLED
+
+#undef CALIBRATION_FLS_START
+
+
+
+#endif
--- /dev/null
+/*\r
+* Configuration of module: CanIf (CanIf_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.6\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+ \r
+#include "CanIf.h"\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#include "CanTp_Cbk.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#include "J1939Tp_Cbk.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm_Cbk.h"\r
+#endif\r
+#include <stdlib.h>\r
+\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+\r
+\r
+// Contains the mapping from CanIf-specific Channels to Can Controllers\r
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {\r
+ FLEXCAN_A, // Channel_1\r
+};\r
+\r
+const uint8 CanIf_Arc_ChannelDefaultConfIndex[CANIF_CHANNEL_CNT] = {\r
+ CANIF_Channel_1_CONFIG_0,\r
+};\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] = {\r
+ // This is the ConfigurationIndex in CanIf_InitController()\r
+ \r
+ \r
+ { \r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CANIF_Channel_1,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+ \r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+\r
+// Data for init configuration CanIfInitConfiguration\r
+\r
+ \r
+\r
+const CanIf_HthConfigType CanIfHthConfigData_Hoh_1[] =\r
+{\r
+ \r
+ { \r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_Channel_1,\r
+ .CanIfHthIdSymRef = HWObj_2,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+const CanIf_HrhConfigType CanIfHrhConfigData_Hoh_1[] =\r
+{\r
+ \r
+ {\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE,\r
+ .CanIfCanControllerHrhIdRef = CANIF_Channel_1,\r
+ .CanIfHrhIdSymRef = HWObj_1,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] = { \r
+ \r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData_Hoh_1,\r
+ .CanIfHthConfig = CanIfHthConfigData_Hoh_1,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+ \r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] = { \r
+ {\r
+ .CanIfTxPduId = PDUR_REVERSE_PDU_ID_TX_PDU,\r
+ .CanIfCanTxPduIdCanId = 2,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = false, \r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData_Hoh_1[0],\r
+ .PduIdRef = NULL,\r
+ }, \r
+ {\r
+ .CanIfTxPduId = PDUR_REVERSE_PDU_ID_FreqInd,\r
+ .CanIfCanTxPduIdCanId = 258,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = false, \r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData_Hoh_1[0],\r
+ .PduIdRef = NULL,\r
+ }, \r
+};\r
+\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] = { \r
+ {\r
+ .CanIfCanRxPduId = PDUR_PDU_ID_RX_PDU,\r
+ .CanIfCanRxPduCanId = 1,\r
+ .CanIfCanRxPduDlc = 8,\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON ) \r
+ .CanIfReadRxPduData = false,\r
+#endif \r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = false, \r
+#endif\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData_Hoh_1[0],\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfUserRxIndication = NULL,\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK,\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ .PduIdRef = NULL,\r
+ }, \r
+ {\r
+ .CanIfCanRxPduId = PDUR_PDU_ID_FreqReq,\r
+ .CanIfCanRxPduCanId = 256,\r
+ .CanIfCanRxPduDlc = 8,\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON ) \r
+ .CanIfReadRxPduData = false,\r
+#endif \r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = false, \r
+#endif\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData_Hoh_1[0],\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfUserRxIndication = NULL,\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK,\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ .PduIdRef = NULL,\r
+ }, \r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used \r
+ .CanIfNumberOfCanRxPduIds = 2,\r
+ .CanIfNumberOfCanTXPduIds = 2,\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+ // This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap, \r
+ .Arc_ChannelDefaultConfIndex = CanIf_Arc_ChannelDefaultConfIndex,\r
+};\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: CanIf (CanIf_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.6\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 3)) )
+#error CanIf: Configuration file expected BSW module version to be 1.3.*
+#endif
+
+\r
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_OFF\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_ARC_RUNTIME_PDU_CONFIGURATION STD_OFF\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+\r
+#define CANIF_PDU_ID_RX_PDU 0\r
+#define CANIF_PDU_ID_FreqReq 1\r
+\r
+#define CANIF_PDU_ID_TX_PDU 0\r
+#define CANIF_PDU_ID_FreqInd 1\r
+\r
+// Identifiers for the elements in CanIfControllerConfig[]\r
+// This is the ConfigurationIndex in CanIf_InitController()\r
+typedef enum {\r
+ CANIF_Channel_1_CONFIG_0,\r
+ CANIF_CHANNEL_CONFIGURATION_CNT\r
+} CanIf_Arc_ConfigurationIndexType;\r
+\r
+typedef enum {\r
+ CANIF_Channel_1,\r
+ CANIF_CHANNEL_CNT\r
+} CanIf_Arc_ChannelIdType;\r
+\r
+#define CANIF_CONTROLLER_ID_Controller_1 CANIF_Channel_1\r
+\r
+\r
+#include "CanIf_ConfigTypes.h"\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: CanIf (CanIf_SpecialPdus.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.6\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 3)) )
+#error CanIf: Configuration file expected BSW module version to be 1.3.*
+#endif
+
+\r
+#ifndef CANIF_SPECIALPDUS_H_\r
+#define CANIF_SPECIALPDUS_H_\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Can (Can_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((CAN_SW_MAJOR_VERSION == 1) && (CAN_SW_MINOR_VERSION == 0)) )
+#error Can: Configuration file expected BSW module version to be 1.0.*
+#endif
+
+ \r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ FLEXCAN_A = 0,\r
+ CAN_CTRL_A = 0,\r
+ FLEXCAN_B = 1,\r
+ CAN_CTRL_B = 1,\r
+ FLEXCAN_C = 2,\r
+ CAN_CTRL_C = 2,\r
+ FLEXCAN_D = 3,\r
+ CAN_CTRL_D = 3,\r
+ FLEXCAN_E = 4,\r
+ CAN_CTRL_E = 4,\r
+ CAN_CONTROLLER_CNT = 5\r
+}CanControllerIdType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_2,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ uint8 CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING\r
+} Can_Arc_ProcessType;\r
+\r
+struct Can_ControllerConfig;\r
+struct Can_Callback;\r
+\r
+typedef struct {\r
+ const struct Can_ControllerConfig *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const struct Can_Callback *CanCallbacks; \r
+ const uint8 * const ArcHthToUnit;\r
+ const uint8 * const ArcHthToHoh;\r
+ const uint8 * const ArcCtrlToUnit;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+ \r
+} Can_ConfigType;\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Can (Can_PBcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1 = 0x0;\r
+Can_FilterMaskType Can_FilterMaskConfigData_FULLMask = 0x1FFFFFFF;\r
+\r
+\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanIdValue = 0x0,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1,\r
+ \r
+ .Can_Arc_Flags = (0),\r
+ \r
+ \r
+ /* Mailbox(es): 8 */\r
+ .ArcMailboxMask = 0x100ULL ,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanIdValue = 0x0,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = 0,\r
+ \r
+ .Can_Arc_Flags = (0),\r
+ \r
+ \r
+ /* Mailbox(es): 9 */\r
+ .ArcMailboxMask = 0x200ULL ,\r
+ },\r
+};\r
+\r
+PduIdType Can_swPduHandles_Controller_1[1];\r
+\r
+// NEW\r
+const uint8 Can_MailBoxToHrh_Controller_1[]= {\r
+ 0,\r
+ 0,\r
+ 0,\r
+ 0,\r
+ 0,\r
+ 0,\r
+ 0,\r
+ 0, \r
+ HWObj_1,\r
+};\r
+\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{ \r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = FLEXCAN_A,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .Can_Arc_Flags = (CAN_CTRL_BUSOFF_PROCESSING_INTERRUPT | CAN_CTRL_RX_PROCESSING_INTERRUPT | CAN_CTRL_TX_PROCESSING_INTERRUPT | CAN_CTRL_WAKEUP_PROCESSING_INTERRUPT | CAN_CTRL_ERROR_PROCESSING_INTERRUPT | CAN_CTRL_ACTIVATION),\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_HohCnt = 2,\r
+ .Can_Arc_HohFifoCnt = 0,\r
+ .Can_Arc_RxMailBoxMask = 0x100ULL,\r
+ .Can_Arc_TxMailBoxMask = 0x200ULL,\r
+ .Can_Arc_TxMailboxStart = 9,\r
+ .Can_Arc_MailBoxToHrh = Can_MailBoxToHrh_Controller_1,\r
+ .Can_Arc_TxPduHandles = Can_swPduHandles_Controller_1,\r
+ .Can_Arc_MailboxMax = 10,\r
+ },\r
+};\r
+\r
+const uint8 Can_HthToUnit[] = {\r
+ [HWObj_2] = 0,\r
+};\r
+\r
+const uint8 Can_HthToHohMap[] = {\r
+ [HWObj_2] = 1,\r
+};\r
+\r
+const uint8 Can_CtrlToUnit[] = {\r
+ [FLEXCAN_A] = 0,\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+ .ArcHthToUnit = Can_HthToUnit,\r
+ .ArcHthToHoh = Can_HthToHohMap,\r
+ .ArcCtrlToUnit = Can_CtrlToUnit,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Com (Com_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.1.1\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 2)) )
+#error Com: Configuration file expected BSW module version to be 1.2.*
+#endif
+
+\r
+#ifndef COM_CFG_H\r
+#define COM_CFG_H\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT STD_ON\r
+\r
+#define COM_N_IPDUS 4\r
+#define COM_N_SIGNALS 5\r
+#define COM_N_GROUP_SIGNALS 0\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_INVALID_SIGNAL_ID 109\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
+\r
+#define ComConfigurationTimeBase 0.0\r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H*/\r
--- /dev/null
+/*\r
+* Configuration of module: Com (Com_PbCfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.1.1\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include <stdlib.h>\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+\r
+\r
+/*\r
+ * Signal init values.\r
+ */\r
+const uint8 Com_SignalInitValue_Arg1 = 5;\r
+const uint8 Com_SignalInitValue_ResultSig = 0;\r
+const uint8 Com_SignalInitValue_Arg2 = 3;\r
+const uint32 Com_SignalInitValue_FreqIndSig = 0;\r
+const uint32 Com_SignalInitValue_FreqReqSig = 1000;\r
+ \r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+const ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/* SignalGroup GroupSignals lists. */\r
+\r
+\r
+/* IPdu buffers and signal group buffers */\r
+uint8 ComArcIPduBuffer_FreqInd[8]; \r
+ \r
+uint8 ComArcIPduBuffer_FreqReq[8];\r
+uint8 ComArcIPduDeferredRxBuffer_FreqReq[8]; \r
+ \r
+uint8 ComArcIPduBuffer_RX_PDU[8];\r
+uint8 ComArcIPduDeferredRxBuffer_RX_PDU[8]; \r
+ \r
+uint8 ComArcIPduBuffer_TX_PDU[8]; \r
+ \r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+ \r
+const ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = Arg1,\r
+ .ComIPduHandleId = 2,\r
+ .Com_Arc_ShadowBuffer = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = PENDING,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_Arg1,\r
+ \r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 8,\r
+ \r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT8,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ \r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .ComHandleId = ResultSig,\r
+ .ComIPduHandleId = 3,\r
+ .Com_Arc_ShadowBuffer = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_ResultSig,\r
+ \r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 8,\r
+ \r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT8,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ \r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .ComHandleId = Arg2,\r
+ .ComIPduHandleId = 2,\r
+ .Com_Arc_ShadowBuffer = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = PENDING,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_Arg2,\r
+ \r
+ .ComBitPosition = 15,\r
+ .ComBitSize = 8,\r
+ \r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT8,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ \r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .ComHandleId = FreqIndSig,\r
+ .ComIPduHandleId = 0,\r
+ .Com_Arc_ShadowBuffer = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_FreqIndSig,\r
+ \r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 32,\r
+ \r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT32,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ \r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .ComHandleId = FreqReqSig,\r
+ .ComIPduHandleId = 1,\r
+ .Com_Arc_ShadowBuffer = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = Rte_COMCbk_FreqReqSig,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = PENDING,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_FreqReqSig,\r
+ \r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 32,\r
+ \r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT32,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ \r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+const ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = ComPduGroup,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+/* IPdu signal lists. */\r
+const ComSignal_type * const ComIPduSignalRefs_FreqInd[] = {\r
+ &ComSignal[ FreqIndSig ], \r
+ NULL,\r
+};\r
+const ComSignal_type * const ComIPduSignalRefs_FreqReq[] = {\r
+ &ComSignal[ FreqReqSig ], \r
+ NULL,\r
+};\r
+const ComSignal_type * const ComIPduSignalRefs_RX_PDU[] = {\r
+ &ComSignal[ Arg1 ],\r
+ &ComSignal[ Arg2 ], \r
+ NULL,\r
+};\r
+const ComSignal_type * const ComIPduSignalRefs_TX_PDU[] = {\r
+ &ComSignal[ ResultSig ], \r
+ NULL,\r
+};\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+const ComIPdu_type ComIPdu[] = { \r
+ \r
+ { // FreqInd\r
+ .ArcIPduOutgoingId = PDUR_PDU_ID_FreqInd,\r
+ .ComIPduCallout = NULL,\r
+ \r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = ComPduGroup,\r
+ \r
+ .ComIPduDeferredDataPtr = 0, \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduDataPtr = ComArcIPduBuffer_FreqInd, \r
+ .ComIPduSignalRef = ComIPduSignalRefs_FreqInd,\r
+ .ComIPduDynSignalRef = 0,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ { // FreqReq\r
+ .ArcIPduOutgoingId = PDUR_REVERSE_PDU_ID_FreqReq,\r
+ .ComIPduCallout = NULL,\r
+ \r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = ComPduGroup,\r
+ \r
+ .ComIPduDeferredDataPtr = ComArcIPduDeferredRxBuffer_FreqReq,\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = NONE,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduDataPtr = ComArcIPduBuffer_FreqReq, \r
+ .ComIPduSignalRef = ComIPduSignalRefs_FreqReq,\r
+ .ComIPduDynSignalRef = 0,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ { // RX_PDU\r
+ .ArcIPduOutgoingId = PDUR_REVERSE_PDU_ID_RX_PDU,\r
+ .ComIPduCallout = NULL,\r
+ \r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = ComPduGroup,\r
+ \r
+ .ComIPduDeferredDataPtr = ComArcIPduDeferredRxBuffer_RX_PDU,\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = NONE,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduDataPtr = ComArcIPduBuffer_RX_PDU, \r
+ .ComIPduSignalRef = ComIPduSignalRefs_RX_PDU,\r
+ .ComIPduDynSignalRef = 0,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ { // TX_PDU\r
+ .ArcIPduOutgoingId = PDUR_PDU_ID_TX_PDU,\r
+ .ComIPduCallout = NULL,\r
+ \r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = ComPduGroup,\r
+ \r
+ .ComIPduDeferredDataPtr = 0, \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduDataPtr = ComArcIPduBuffer_TX_PDU, \r
+ .ComIPduSignalRef = ComIPduSignalRefs_TX_PDU,\r
+ .ComIPduDynSignalRef = 0,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
+ { // FreqInd\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ }, \r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+ { // FreqReq\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ }, \r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+ { // RX_PDU\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ }, \r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+ { // TX_PDU\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ }, \r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+};\r
+\r
+Com_Arc_Signal_type Com_Arc_Signal[] = {\r
+ { // Arg1\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComSignalUpdated = 0,\r
+ },\r
+ \r
+ { // ResultSig\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComSignalUpdated = 0,\r
+ },\r
+ \r
+ { // Arg2\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComSignalUpdated = 0,\r
+ },\r
+ \r
+ { // FreqIndSig\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComSignalUpdated = 0,\r
+ },\r
+ \r
+ { // FreqReqSig\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComSignalUpdated = 0,\r
+ },\r
+ \r
+};\r
+\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = NULL\r
+};\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Com (Com_PbCfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.1.1\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 2)) )
+#error Com: Configuration file expected BSW module version to be 1.2.*
+#endif
+
+#ifndef COM_PBCFG_H\r
+#define COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// COM Polite Defines.\r
+#define COM_PDU_ID_FreqInd 0\r
+#define COM_PDU_ID_FreqReq 1\r
+#define COM_PDU_ID_RX_PDU 2\r
+#define COM_PDU_ID_TX_PDU 3\r
+\r
+\r
+\r
+// PDU group definitions\r
+#define ComPduGroup 0\r
+\r
+\r
+// Signal definitions\r
+#define Arg1 0\r
+#define ResultSig 1\r
+#define Arg2 2\r
+#define FreqIndSig 3\r
+#define FreqReqSig 4\r
+\r
+\r
+\r
+// Notifications\r
+\r
+void Rte_COMCbk_FreqReqSig(void);
+\r
+\r
+// Callouts\r
+\r
+\r
+#endif /* COM_PBCFG_H */\r
--- /dev/null
+/*\r
+* Configuration of module: Det (Det_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.1\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((DET_SW_MAJOR_VERSION == 1) && (DET_SW_MINOR_VERSION == 0)) )
+#error Det: Configuration file expected BSW module version to be 1.0.*
+#endif
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H \r
+\r
+#define DET_ENABLE_CALLBACKS STD_OFF // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+#define DET_DEINIT_API STD_OFF // Enable/Disable the Det_DeInit function\r
+#define DET_RAMLOG_SIZE (16) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /* DET_CFG_H */\r
--- /dev/null
+/*\r
+* Configuration of module: Dio (Dio_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.0\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((DIO_SW_MAJOR_VERSION == 1) && (DIO_SW_MINOR_VERSION == 0)) )
+#error Dio: Configuration file expected BSW module version to be 1.0.*
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_OFF\r
+#define DIO_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define DIO_END_OF_LIST (-1u)\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_MPC5567_GENERIC_PORT = 0,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_LED_CHANNEL 0\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (DIO_MPC5567_GENERIC_PORT)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Dio (Dio_Lcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.0\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_LED_CHANNEL,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_LED_PORT, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = 0, \r
+ .mask = 0, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+\r
+MOD_USE += CANIF COM DET ECUM KERNEL PDUR RTE CAN MCU DIO PORT \r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+\r
+typedef enum {\r
+ ECUM_USER_User_1,\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+\r
+#endif /*ECUM_CFG_H_*/\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Generated_Types.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#ifdef CFG_ECUM_USE_SERVICE_COMPONENT\r
+#include "Rte_EcuM.h"\r
+#endif\r
+\r
+#include "EcuM_Types.h"\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#endif\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#endif\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+#if defined(USE_WDGIF)\r
+#include "WdgIf.h"\r
+#endif\r
+\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultSleepMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ const UdpNm_ConfigType* UdpNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ const J1939Tp_ConfigType* J1939TpConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+#if defined(USE_EEP)\r
+ const Eep_ConfigType* EepConfig;\r
+#endif\r
+#if defined(USE_SPI)\r
+ const Spi_ConfigType* SpiConfig;\r
+#endif\r
+#if defined(USE_WDG)\r
+ const Wdg_ConfigType* WdgConfig;\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ const WdgIf_ConfigType* WdgIfConfig;\r
+#endif\r
+#if defined(USE_WDGM)\r
+ const WdgM_ConfigType* WdgMConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_PBcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#if defined(USE_CANSM)\r
+extern const CanSM_ConfigType CanSM_Config;\r
+#endif\r
+#if defined(USE_NM)\r
+extern const Nm_ConfigType Nm_Config;\r
+#endif\r
+#if defined(USE_CANNM)\r
+extern const CanNm_ConfigType CanNm_Config;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+extern const UdpNm_ConfigType UdpNm_Config;\r
+#endif\r
+#if defined(USE_COMM)\r
+extern const ComM_ConfigType ComM_Config;\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+extern const J1939Tp_ConfigType J1939Tp_Config;\r
+#endif\r
+\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultSleepMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ .UdpNmConfig = &UdpNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_WDG)\r
+ .WdgConfig = &WdgConfig,\r
+#endif\r
+#if defined(USE_WDGM)\r
+ .WdgMConfig = &WdgMConfig,\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ .WdgIfConfig = &WdgIfConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+#if defined(USE_EEP)\r
+ .EepConfig = EepConfigData,\r
+#endif\r
+#if defined(USE_SPI)\r
+ .SpiConfig = &SpiConfigData,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.3\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 0UL,\r
+ .Pll1 = 0,\r
+ .Pll2 = 0,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = MCU_NBR_OF_RAM_SECTIONS,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.3\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error Mcu: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_OFF \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_Clock = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+\r
+#define MCU_NBR_OF_RAM_SECTIONS 0\r
+\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+ \r
+\r
+#include "kernel.h"\r
+\r
+\r
+// ############################### EXTERNAL REFERENCES #############################\r
+\r
+/* Application externals */\r
+\r
+/* Interrupt externals */\r
+\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+// ############################### APPLICATIONS #############################\r
+GEN_APPLICATION_HEAD = {\r
+ GEN_APPLICATION(\r
+ /* id */ APPLICATION_ID_OsApplication1,\r
+ /* name */ "OsApplication1",\r
+ /* trusted */ true, /* NOT CONFIGURABLE IN TOOLS */\r
+ /* core */ 0, /* Default value, multicore not enabled.*/\r
+ /* StartupHook */ NULL,\r
+ /* ShutdownHook */ NULL,\r
+ /* ErrorHook */ NULL,\r
+ /* rstrtTaskId */ 0 /* NOT CONFIGURABLE IN TOOLS */\r
+ ), \r
+};\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD = {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+ CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_BlinkerAlarm, ALARM_AUTOSTART_ABSOLUTE, 100, 1000, OSDEFAULTAPPMODE );\r
+ \r
+GEN_ALARM_AUTOSTART(ALARM_ID_MainFunctionAlarm, ALARM_AUTOSTART_ABSOLUTE, 10, 10, OSDEFAULTAPPMODE );\r
+ \r
+GEN_ALARM_AUTOSTART(ALARM_ID_StepAlarm, ALARM_AUTOSTART_ABSOLUTE, 20, 100, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD = {\r
+ GEN_ALARM( ALARM_ID_BlinkerAlarm,\r
+ "BlinkerAlarm",\r
+ COUNTER_ID_Counter1,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_BlinkerAlarm),\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_BlinkerTask,\r
+ 0,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+ GEN_ALARM( ALARM_ID_MainFunctionAlarm,\r
+ "MainFunctionAlar",\r
+ COUNTER_ID_Counter1,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_MainFunctionAlarm),\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_MainFunctionTask,\r
+ 0,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+ GEN_ALARM( ALARM_ID_StepAlarm,\r
+ "StepAlarm",\r
+ COUNTER_ID_Counter1,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_StepAlarm),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_StepTask,\r
+ EVENT_MASK_StepEvent,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+\r
+DECLARE_STACK(BlinkerTask,2048);\r
+DECLARE_STACK(MainFunctionTask,2048);\r
+DECLARE_STACK(StartupTask,2048);\r
+DECLARE_STACK(StepTask,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD = {\r
+ GEN_BTASK( /* */OsIdle,\r
+ /* name */"OsIdle",\r
+ /* priority */0,\r
+ /* schedule */FULL,\r
+ /* autostart */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */0,\r
+ /* Accessing apps */1 \r
+ ),\r
+ GEN_BTASK(\r
+ /* */BlinkerTask,\r
+ /* name */"BlinkerTask",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* autostart */FALSE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_BTASK(\r
+ /* */MainFunctionTask,\r
+ /* name */"MainFunctionTask",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* autostart */FALSE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_BTASK(\r
+ /* */StartupTask,\r
+ /* name */"StartupTask",\r
+ /* priority */10,\r
+ /* schedule */FULL,\r
+ /* autostart */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_ETASK(\r
+ /* */StepTask,\r
+ /* name */"StepTask",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* name */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* event mask */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+GEN_ISR_MAP = {\r
+ 0\r
+};\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error Os: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+// Application Id's\r
+#define APPLICATION_ID_OsApplication1 0\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_BlinkerAlarm 0\r
+#define ALARM_ID_MainFunctionAlarm 1\r
+#define ALARM_ID_StepAlarm 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// System counter\r
+#define OSMAXALLOWEDVALUE UINT_MAX// NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKSPERBASE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKDURATION 1000000UL // Time between ticks in nano seconds\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 OSMAXALLOWEDVALUE\r
+#define OSTICKSPERBASE_Counter1 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE_Counter1 1\r
+#define OS_TICKS2SEC_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000000UL )\r
+#define OS_TICKS2MS_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000UL )\r
+#define OS_TICKS2US_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000UL )\r
+#define OS_TICKS2NS_Counter1(_ticks) (OSTICKDURATION * _ticks)\r
+\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_StepEvent 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+\r
+#define TASK_ID_BlinkerTask 1\r
+#define TASK_ID_MainFunctionTask 2\r
+#define TASK_ID_StartupTask 3\r
+#define TASK_ID_StepTask 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void BlinkerTask( void );\r
+void MainFunctionTask( void );\r
+void StartupTask( void );\r
+void StepTask( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+//#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+#define OS_APPLICATION_CNT 1\r
+#define OS_SERVICE_CNT 0 /* ARCTICSTUDIO_GENERATOR_TODO */\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_APPLICATIONS STD_ON\r
+#define OS_USE_MEMORY_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_TASK_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_ISR_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+//#define OS_SC3 STD_ON /* NOT CONFIGURABLE IN TOOLS */ \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_PARAMETER_ACCESS STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_RES_SCHEDULER STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+\r
+#define OS_ISR_CNT 0\r
+#define OS_ISR2_CNT 0\r
+#define OS_ISR1_CNT 0\r
+\r
+#define OS_ISR_MAX_CNT 10\r
+\r
+#define OS_NUM_CORES 1\r
+\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: PduR (PduR_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 3.1.10\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 2) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error PduR: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef PDUR_CFG_H_\r
+#define PDUR_CFG_H_\r
+\r
+// Module support\r
+#define PDUR_CANIF_SUPPORT STD_ON\r
+#define PDUR_CANTP_SUPPORT STD_OFF\r
+#define PDUR_FRIF_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_FRTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_LINIF_SUPPORT STD_OFF\r
+#define PDUR_LINTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_COM_SUPPORT STD_ON\r
+#define PDUR_DCM_SUPPORT STD_OFF\r
+#define PDUR_IPDUM_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_J1939TP_SUPPORT STD_OFF\r
+\r
+#define PDUR_DEV_ERROR_DETECT STD_OFF\r
+#define PDUR_VERSION_INFO_API STD_OFF\r
+\r
+\r
+// Zero cost operation mode\r
+#define PDUR_ZERO_COST_OPERATION STD_OFF\r
+#define PDUR_SINGLE_IF NULL\r
+#define PDUR_SINGLE_TP NULL\r
+\r
+// Gateway operation\r
+#define PDUR_GATEWAY_OPERATION STD_ON\r
+#define PDUR_MEMORY_SIZE 10 /* Not used */\r
+#define PDUR_SB_TX_BUFFER_SUPPORT STD_ON\r
+#define PDUR_FIFO_TX_BUFFER_SUPPORT STD_OFF\r
+\r
+/**\r
+ * The maximum numbers of Tx buffers.\r
+ */\r
+#define PDUR_MAX_TX_BUFFER_NUMBER 10 /* Not used */\r
+\r
+\r
+// Multicast\r
+#define PDUR_MULTICAST_TOIF_SUPPORT STD_ON\r
+#define PDUR_MULTICAST_FROMIF_SUPPORT STD_ON\r
+#define PDUR_MULTICAST_TOTP_SUPPORT STD_ON\r
+#define PDUR_MULTICAST_FROMTP_SUPPORT STD_ON\r
+\r
+// Minimum routing\r
+/* Minimum routing not supported.\r
+#define PDUR_MINIMUM_ROUTING_UP_MODULE COM\r
+#define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF\r
+#define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)\r
+#define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)\r
+*/\r
+\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: PduR (PduR_PbCfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 3.1.10\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#include "PduR.h"\r
+\r
+\r
+#if PDUR_CANIF_SUPPORT == STD_ON\r
+#include "CanIf.h"\r
+#endif\r
+#if PDUR_CANTP_SUPPORT == STD_ON\r
+#include "CanTp.h"\r
+#endif\r
+#if PDUR_LINIF_SUPPORT == STD_ON\r
+#include "LinIf.h"\r
+#endif\r
+#if PDUR_COM_SUPPORT == STD_ON\r
+#include "Com.h"\r
+#endif\r
+#if PDUR_DCM_SUPPORT == STD_ON\r
+#include "Dcm.h"\r
+#endif\r
+#if PDUR_J1939TP_SUPPORT == STD_ON\r
+#include "J1939Tp.h"\r
+#endif\r
+\r
+\r
+\r
+PduRTpBufferInfo_type PduRTpBuffers[] = {\r
+ {\r
+ .pduInfoPtr = NULL,\r
+ .status = PDUR_BUFFER_FREE,\r
+ .bufferSize = 0\r
+ }\r
+};\r
+\r
+PduRTpBufferInfo_type *PduRTpRouteBufferPtrs[] = {\r
+ NULL\r
+};\r
+\r
+\r
+ \r
+const PduRDestPdu_type PduRDestination_FreqInd_PduRDestination = {\r
+ .DestModule = ARC_PDUR_CANIF,\r
+ .DestPduId = CANIF_PDU_ID_TX_PDU,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ .TxBufferRef = NULL\r
+}; \r
+const PduRDestPdu_type PduRDestination_FreqReq_PduRDestination = {\r
+ .DestModule = ARC_PDUR_COM,\r
+ .DestPduId = COM_PDU_ID_FreqReq,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ .TxBufferRef = NULL\r
+}; \r
+const PduRDestPdu_type PduRDestination_RX_PDU_PduRDestination = {\r
+ .DestModule = ARC_PDUR_COM,\r
+ .DestPduId = COM_PDU_ID_RX_PDU,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ .TxBufferRef = NULL\r
+}; \r
+const PduRDestPdu_type PduRDestination_TX_PDU_PduRDestination = {\r
+ .DestModule = ARC_PDUR_CANIF,\r
+ .DestPduId = CANIF_PDU_ID_FreqInd,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ .TxBufferRef = NULL\r
+}; \r
+\r
+const PduRDestPdu_type * const PduRDestinations_FreqInd[] = { \r
+ &PduRDestination_FreqInd_PduRDestination,\r
+ NULL\r
+};\r
+const PduRDestPdu_type * const PduRDestinations_FreqReq[] = { \r
+ &PduRDestination_FreqReq_PduRDestination,\r
+ NULL\r
+};\r
+const PduRDestPdu_type * const PduRDestinations_RX_PDU[] = { \r
+ &PduRDestination_RX_PDU_PduRDestination,\r
+ NULL\r
+};\r
+const PduRDestPdu_type * const PduRDestinations_TX_PDU[] = { \r
+ &PduRDestination_TX_PDU_PduRDestination,\r
+ NULL\r
+};\r
+\r
+\r
+const PduRRoutingPath_type PduRRoutingPath_FreqInd = { \r
+ .SrcModule = ARC_PDUR_COM,\r
+ .SrcPduId = COM_PDU_ID_TX_PDU,\r
+ .SduLength = 0,\r
+ .PduRDestPdus = PduRDestinations_FreqInd\r
+}; \r
+const PduRRoutingPath_type PduRRoutingPath_FreqReq = { \r
+ .SrcModule = ARC_PDUR_CANIF,\r
+ .SrcPduId = CANIF_PDU_ID_FreqReq,\r
+ .SduLength = 0,\r
+ .PduRDestPdus = PduRDestinations_FreqReq\r
+}; \r
+const PduRRoutingPath_type PduRRoutingPath_RX_PDU = { \r
+ .SrcModule = ARC_PDUR_CANIF,\r
+ .SrcPduId = CANIF_PDU_ID_RX_PDU,\r
+ .SduLength = 0,\r
+ .PduRDestPdus = PduRDestinations_RX_PDU\r
+}; \r
+const PduRRoutingPath_type PduRRoutingPath_TX_PDU = { \r
+ .SrcModule = ARC_PDUR_COM,\r
+ .SrcPduId = COM_PDU_ID_FreqInd,\r
+ .SduLength = 0,\r
+ .PduRDestPdus = PduRDestinations_TX_PDU\r
+}; \r
+\r
+\r
+const PduRRoutingPath_type * const PduRRoutingPaths[] = { \r
+ &PduRRoutingPath_FreqInd,\r
+ &PduRRoutingPath_FreqReq,\r
+ &PduRRoutingPath_RX_PDU,\r
+ &PduRRoutingPath_TX_PDU,\r
+ NULL\r
+};\r
+\r
+\r
+PduR_PBConfigType PduR_Config = {\r
+ .PduRConfigurationId = 0,\r
+ .RoutingPaths = PduRRoutingPaths,\r
+ .TpBuffers = PduRTpBuffers,\r
+ .TpRouteBuffers = PduRTpRouteBufferPtrs,\r
+ .NRoutingPaths = 4\r
+};\r
--- /dev/null
+/*\r
+* Configuration of module: PduR (PduR_PbCfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 3.1.10\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 2) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error PduR: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+\r
+extern PduR_PBConfigType PduR_Config;\r
+\r
+// PduR Polite Defines.\r
+#define PDUR_PDU_ID_TX_PDU 0\r
+#define PDUR_REVERSE_PDU_ID_TX_PDU 0\r
+#define PDUR_PDU_ID_FreqReq 1\r
+#define PDUR_REVERSE_PDU_ID_FreqReq 1\r
+#define PDUR_PDU_ID_RX_PDU 2\r
+#define PDUR_REVERSE_PDU_ID_RX_PDU 2\r
+#define PDUR_PDU_ID_FreqInd 3\r
+#define PDUR_REVERSE_PDU_ID_FreqInd 3\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Port (Port_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+ \r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ ( PORT_FUNC0 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 0 : PORT_PIN_MODE_DIO */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ PORT_PCR_RESET, /* PCR 48 */\r
+ PORT_PCR_RESET, /* PCR 49 */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ PORT_PCR_RESET, /* PCR 53 */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 83 : PORT_PIN_MODE_CAN */\r
+ ( PORT_FUNC1 | PORT_IBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 84 : PORT_PIN_MODE_CAN */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+ PORT_PCR_RESET, /* PCR 145 */\r
+ PORT_PCR_RESET, /* PCR 146 */\r
+ PORT_PCR_RESET, /* PCR 147 */\r
+ PORT_PCR_RESET, /* PCR 148 */\r
+ PORT_PCR_RESET, /* PCR 149 */\r
+ PORT_PCR_RESET, /* PCR 150 */\r
+ PORT_PCR_RESET, /* PCR 151 */\r
+ PORT_PCR_RESET, /* PCR 152 */\r
+ PORT_PCR_RESET, /* PCR 153 */\r
+ PORT_PCR_RESET, /* PCR 154 */\r
+ PORT_PCR_RESET, /* PCR 155 */\r
+ PORT_PCR_RESET, /* PCR 156 */\r
+ PORT_PCR_RESET, /* PCR 157 */\r
+ PORT_PCR_RESET, /* PCR 158 */\r
+ PORT_PCR_RESET, /* PCR 159 */\r
+ PORT_PCR_RESET, /* PCR 160 */\r
+ PORT_PCR_RESET, /* PCR 161 */\r
+ PORT_PCR_RESET, /* PCR 162 */\r
+ PORT_PCR_RESET, /* PCR 163 */\r
+ PORT_PCR_RESET, /* PCR 164 */\r
+ PORT_PCR_RESET, /* PCR 165 */\r
+ PORT_PCR_RESET, /* PCR 166 */\r
+ PORT_PCR_RESET, /* PCR 167 */\r
+ PORT_PCR_RESET, /* PCR 168 */\r
+ PORT_PCR_RESET, /* PCR 169 */\r
+ PORT_PCR_RESET, /* PCR 170 */\r
+ PORT_PCR_RESET, /* PCR 171 */\r
+ PORT_PCR_RESET, /* PCR 172 */\r
+ PORT_PCR_RESET, /* PCR 173 */\r
+ PORT_PCR_RESET, /* PCR 174 */\r
+ PORT_PCR_RESET, /* PCR 175 */\r
+ PORT_PCR_RESET, /* PCR 176 */\r
+ PORT_PCR_RESET, /* PCR 177 */\r
+ PORT_PCR_RESET, /* PCR 178 */\r
+ PORT_PCR_RESET, /* PCR 179 */\r
+ PORT_PCR_RESET, /* PCR 180 */\r
+ PORT_PCR_RESET, /* PCR 181 */\r
+ PORT_PCR_RESET, /* PCR 182 */\r
+ PORT_PCR_RESET, /* PCR 183 */\r
+ PORT_PCR_RESET, /* PCR 184 */\r
+ PORT_PCR_RESET, /* PCR 185 */\r
+ PORT_PCR_RESET, /* PCR 186 */\r
+ PORT_PCR_RESET, /* PCR 187 */\r
+ PORT_PCR_RESET, /* PCR 188 */\r
+ PORT_PCR_RESET, /* PCR 189 */\r
+ PORT_PCR_RESET, /* PCR 190 */\r
+ PORT_PCR_RESET, /* PCR 191 */\r
+ PORT_PCR_RESET, /* PCR 192 */\r
+ PORT_PCR_RESET, /* PCR 193 */\r
+ PORT_PCR_RESET, /* PCR 194 */\r
+ PORT_PCR_RESET, /* PCR 195 */\r
+ PORT_PCR_RESET, /* PCR 196 */\r
+ PORT_PCR_RESET, /* PCR 197 */\r
+ PORT_PCR_RESET, /* PCR 198 */\r
+ PORT_PCR_RESET, /* PCR 199 */\r
+ PORT_PCR_RESET, /* PCR 200 */\r
+ PORT_PCR_RESET, /* PCR 201 */\r
+ PORT_PCR_RESET, /* PCR 202 */\r
+ PORT_PCR_RESET, /* PCR 203 */\r
+ PORT_PCR_RESET, /* PCR 204 */\r
+ PORT_PCR_RESET, /* PCR 205 */\r
+ PORT_PCR_RESET, /* PCR 206 */\r
+ PORT_PCR_RESET, /* PCR 207 */\r
+ PORT_PCR_RESET, /* PCR 208 */\r
+ PORT_PCR_RESET, /* PCR 209 */\r
+ PORT_PCR_RESET, /* PCR 210 */\r
+ PORT_PCR_RESET, /* PCR 211 */\r
+ PORT_PCR_RESET, /* PCR 212 */\r
+ PORT_PCR_RESET, /* PCR 213 */\r
+ PORT_PCR_RESET, /* PCR 214 */\r
+ PORT_PCR_RESET, /* PCR 215 */\r
+ PORT_PCR_RESET, /* PCR 216 */\r
+ PORT_PCR_RESET, /* PCR 217 */\r
+ PORT_PCR_RESET, /* PCR 218 */\r
+ PORT_PCR_RESET, /* PCR 219 */\r
+ PORT_PCR_RESET, /* PCR 220 */\r
+ PORT_PCR_RESET, /* PCR 221 */\r
+ PORT_PCR_RESET, /* PCR 222 */\r
+ PORT_PCR_RESET, /* PCR 223 */\r
+ PORT_PCR_RESET, /* PCR 224 */\r
+ PORT_PCR_RESET, /* PCR 225 */\r
+ PORT_PCR_RESET, /* PCR 226 */\r
+ PORT_PCR_RESET, /* PCR 227 */\r
+ PORT_PCR_RESET, /* PCR 228 */\r
+ PORT_PCR_RESET, /* PCR 229 */\r
+ PORT_PCR_RESET, /* PCR 230 */\r
+ PORT_PCR_RESET, /* PCR 231 */\r
+ PORT_PCR_RESET, /* PCR 232 */\r
+ PORT_PCR_RESET, /* PCR 233 */\r
+ PORT_PCR_RESET, /* PCR 234 */\r
+ PORT_PCR_RESET, /* PCR 235 */\r
+ PORT_PCR_RESET, /* PCR 236 */\r
+ PORT_PCR_RESET, /* PCR 237 */\r
+ PORT_PCR_RESET, /* PCR 238 */\r
+ PORT_PCR_RESET, /* PCR 239 */\r
+ PORT_PCR_RESET, /* PCR 240 */\r
+ PORT_PCR_RESET, /* PCR 241 */\r
+ PORT_PCR_RESET, /* PCR 242 */\r
+ PORT_PCR_RESET, /* PCR 243 */\r
+ PORT_PCR_RESET, /* PCR 244 */\r
+ PORT_PCR_RESET, /* PCR 245 */\r
+ PORT_PCR_RESET, /* PCR 246 */\r
+ PORT_PCR_RESET, /* PCR 247 */\r
+ PORT_PCR_RESET, /* PCR 248 */\r
+ PORT_PCR_RESET, /* PCR 249 */\r
+ PORT_PCR_RESET, /* PCR 250 */\r
+ PORT_PCR_RESET, /* PCR 251 */\r
+ PORT_PCR_RESET, /* PCR 252 */\r
+ PORT_PCR_RESET, /* PCR 253 */\r
+ PORT_PCR_RESET, /* PCR 254 */\r
+ PORT_PCR_RESET, /* PCR 255 */\r
+ PORT_PCR_RESET, /* PCR 256 */\r
+ PORT_PCR_RESET, /* PCR 257 */\r
+ PORT_PCR_RESET, /* PCR 258 */\r
+ PORT_PCR_RESET, /* PCR 259 */\r
+ PORT_PCR_RESET, /* PCR 260 */\r
+ PORT_PCR_RESET, /* PCR 261 */\r
+ PORT_PCR_RESET, /* PCR 262 */\r
+ PORT_PCR_RESET, /* PCR 263 */\r
+ PORT_PCR_RESET, /* PCR 264 */\r
+ PORT_PCR_RESET, /* PCR 265 */\r
+ PORT_PCR_RESET, /* PCR 266 */\r
+ PORT_PCR_RESET, /* PCR 267 */\r
+ PORT_PCR_RESET, /* PCR 268 */\r
+ PORT_PCR_RESET, /* PCR 269 */\r
+ PORT_PCR_RESET, /* PCR 270 */\r
+ PORT_PCR_RESET, /* PCR 271 */\r
+ PORT_PCR_RESET, /* PCR 272 */\r
+ PORT_PCR_RESET, /* PCR 273 */\r
+ PORT_PCR_RESET, /* PCR 274 */\r
+ PORT_PCR_RESET, /* PCR 275 */\r
+ PORT_PCR_RESET, /* PCR 276 */\r
+ PORT_PCR_RESET, /* PCR 277 */\r
+ PORT_PCR_RESET, /* PCR 278 */\r
+ PORT_PCR_RESET, /* PCR 279 */\r
+ PORT_PCR_RESET, /* PCR 280 */\r
+ PORT_PCR_RESET, /* PCR 281 */\r
+ PORT_PCR_RESET, /* PCR 282 */\r
+ PORT_PCR_RESET, /* PCR 283 */\r
+ PORT_PCR_RESET, /* PCR 284 */\r
+ PORT_PCR_RESET, /* PCR 285 */\r
+ PORT_PCR_RESET, /* PCR 286 */\r
+ PORT_PCR_RESET, /* PCR 287 */\r
+ PORT_PCR_RESET, /* PCR 288 */\r
+ PORT_PCR_RESET, /* PCR 289 */\r
+ PORT_PCR_RESET, /* PCR 290 */\r
+ PORT_PCR_RESET, /* PCR 291 */\r
+ PORT_PCR_RESET, /* PCR 292 */\r
+ PORT_PCR_RESET, /* PCR 293 */\r
+ PORT_PCR_RESET, /* PCR 294 */\r
+ PORT_PCR_RESET, /* PCR 295 */\r
+ PORT_PCR_RESET, /* PCR 296 */\r
+ PORT_PCR_RESET, /* PCR 297 */\r
+ PORT_PCR_RESET, /* PCR 298 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+ PORT_GPDO_RESET, /* GPDO 143 */\r
+ PORT_GPDO_RESET, /* GPDO 144 */\r
+ PORT_GPDO_RESET, /* GPDO 145 */\r
+ PORT_GPDO_RESET, /* GPDO 146 */\r
+ PORT_GPDO_RESET, /* GPDO 147 */\r
+ PORT_GPDO_RESET, /* GPDO 148 */\r
+ PORT_GPDO_RESET, /* GPDO 149 */\r
+ PORT_GPDO_RESET, /* GPDO 150 */\r
+ PORT_GPDO_RESET, /* GPDO 151 */\r
+ PORT_GPDO_RESET, /* GPDO 152 */\r
+ PORT_GPDO_RESET, /* GPDO 153 */\r
+ PORT_GPDO_RESET, /* GPDO 154 */\r
+ PORT_GPDO_RESET, /* GPDO 155 */\r
+ PORT_GPDO_RESET, /* GPDO 156 */\r
+ PORT_GPDO_RESET, /* GPDO 157 */\r
+ PORT_GPDO_RESET, /* GPDO 158 */\r
+ PORT_GPDO_RESET, /* GPDO 159 */\r
+ PORT_GPDO_RESET, /* GPDO 160 */\r
+ PORT_GPDO_RESET, /* GPDO 161 */\r
+ PORT_GPDO_RESET, /* GPDO 162 */\r
+ PORT_GPDO_RESET, /* GPDO 163 */\r
+ PORT_GPDO_RESET, /* GPDO 164 */\r
+ PORT_GPDO_RESET, /* GPDO 165 */\r
+ PORT_GPDO_RESET, /* GPDO 166 */\r
+ PORT_GPDO_RESET, /* GPDO 167 */\r
+ PORT_GPDO_RESET, /* GPDO 168 */\r
+ PORT_GPDO_RESET, /* GPDO 169 */\r
+ PORT_GPDO_RESET, /* GPDO 170 */\r
+ PORT_GPDO_RESET, /* GPDO 171 */\r
+ PORT_GPDO_RESET, /* GPDO 172 */\r
+ PORT_GPDO_RESET, /* GPDO 173 */\r
+ PORT_GPDO_RESET, /* GPDO 174 */\r
+ PORT_GPDO_RESET, /* GPDO 175 */\r
+ PORT_GPDO_RESET, /* GPDO 176 */\r
+ PORT_GPDO_RESET, /* GPDO 177 */\r
+ PORT_GPDO_RESET, /* GPDO 178 */\r
+ PORT_GPDO_RESET, /* GPDO 179 */\r
+ PORT_GPDO_RESET, /* GPDO 180 */\r
+ PORT_GPDO_RESET, /* GPDO 181 */\r
+ PORT_GPDO_RESET, /* GPDO 182 */\r
+ PORT_GPDO_RESET, /* GPDO 183 */\r
+ PORT_GPDO_RESET, /* GPDO 184 */\r
+ PORT_GPDO_RESET, /* GPDO 185 */\r
+ PORT_GPDO_RESET, /* GPDO 186 */\r
+ PORT_GPDO_RESET, /* GPDO 187 */\r
+ PORT_GPDO_RESET, /* GPDO 188 */\r
+ PORT_GPDO_RESET, /* GPDO 189 */\r
+ PORT_GPDO_RESET, /* GPDO 190 */\r
+ PORT_GPDO_RESET, /* GPDO 191 */\r
+ PORT_GPDO_RESET, /* GPDO 192 */\r
+ PORT_GPDO_RESET, /* GPDO 193 */\r
+ PORT_GPDO_RESET, /* GPDO 194 */\r
+ PORT_GPDO_RESET, /* GPDO 195 */\r
+ PORT_GPDO_RESET, /* GPDO 196 */\r
+ PORT_GPDO_RESET, /* GPDO 197 */\r
+ PORT_GPDO_RESET, /* GPDO 198 */\r
+ PORT_GPDO_RESET, /* GPDO 199 */\r
+ PORT_GPDO_RESET, /* GPDO 200 */\r
+ PORT_GPDO_RESET, /* GPDO 201 */\r
+ PORT_GPDO_RESET, /* GPDO 202 */\r
+ PORT_GPDO_RESET, /* GPDO 203 */\r
+ PORT_GPDO_RESET, /* GPDO 204 */\r
+ PORT_GPDO_RESET, /* GPDO 205 */\r
+ PORT_GPDO_RESET, /* GPDO 206 */\r
+ PORT_GPDO_RESET, /* GPDO 207 */\r
+ PORT_GPDO_RESET, /* GPDO 208 */\r
+ PORT_GPDO_RESET, /* GPDO 209 */\r
+ PORT_GPDO_RESET, /* GPDO 210 */\r
+ PORT_GPDO_RESET, /* GPDO 211 */\r
+ PORT_GPDO_RESET, /* GPDO 212 */\r
+ PORT_GPDO_RESET, /* GPDO 213 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+* Configuration of module: Port (Port_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error Port: Configuration file expected BSW module version to be 1.0.*
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_OFF\r
+#define PORT_DEV_ERROR_DETECT STD_OFF\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_GPIO_APC PORT_BIT2\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_CNTXA 83 \r
+#define PORT_PIN_NAME_CNRXA 84 \r
+#define PORT_PIN_NAME_GPIO0 0 \r
+\r
+#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte.c */\r
+#include "Os.h"\r
+#include "Rte_Type.h"\r
+#include "Rte_Data.h"\r
+#include <string.h>\r
+#include "Rte_Calculator_Internal.h"\r
+#include "Rte_Tester_Internal.h"\r
+#include "Rte_Logger_Internal.h"\r
+#include "Rte_Logger2_Internal.h"\r
+#include "Com.h"\r
+\r
+Rte_DE_Read_TesterRunnable_ReadArg1 Rte_Buf_TesterRunnable_Argumentsarg1_ibuffer;\r
+Rte_DE_Read_TesterRunnable_ReadArg2 Rte_Buf_TesterRunnable_Argumentsarg2_ibuffer;\r
+Rte_DE_Read_FreqReqRunnable_ReadFreqReq Rte_Buf_FreqReqRunnable_FreqReqfreq_ibuffer;\r
+Rte_DE_Write_TesterRunnable_WriteResult Rte_Buf_TesterRunnable_Resultresult_ibuffer;\r
+Rte_DE_Write_FreqReqRunnable_WriteFreqReqInd Rte_Buf_FreqReqRunnable_FreqReqIndfreq_ibuffer;\r
+Rte_CDS_Tester Rte_Inst_Tester =\r
+{\r
+ .TesterRunnable_Arguments_arg1 = &Rte_Buf_TesterRunnable_Argumentsarg1_ibuffer,\r
+ .TesterRunnable_Arguments_arg2 = &Rte_Buf_TesterRunnable_Argumentsarg2_ibuffer,\r
+ .FreqReqRunnable_FreqReq_freq = &Rte_Buf_FreqReqRunnable_FreqReqfreq_ibuffer,\r
+ .TesterRunnable_Result_result = &Rte_Buf_TesterRunnable_Resultresult_ibuffer,\r
+ .FreqReqRunnable_FreqReqInd_freq = &Rte_Buf_FreqReqRunnable_FreqReqIndfreq_ibuffer,\r
+};\r
+\r
+Rte_DE_Read_LoggerRunnable_ReadResult Rte_Buf_LoggerRunnable_Resultresult_ibuffer;\r
+Rte_CDS_Logger Rte_Inst_Logger =\r
+{\r
+ .LoggerRunnable_Result_result = &Rte_Buf_LoggerRunnable_Resultresult_ibuffer,\r
+};\r
+\r
+Rte_DE_Read_Logger2Runnable_ReadResult Rte_Buf_Logger2Runnable_Resultresult_ibuffer;\r
+Rte_CDS_Logger2 Rte_Inst_Logger2 =\r
+{\r
+ .Logger2Runnable_Result_result = &Rte_Buf_Logger2Runnable_Resultresult_ibuffer,\r
+};\r
+\r
+void Rte_PRE_TesterRunnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ uint8 Arg1_buf = 0;\r
+ Com_ReceiveSignal(Arg1, &Arg1_buf);\r
+ Rte_Inst_Tester.TesterRunnable_Arguments_arg1->value = (UInt8) Arg1_buf;\r
+\r
+ uint8 Arg2_buf = 0;\r
+ Com_ReceiveSignal(Arg2, &Arg2_buf);\r
+ Rte_Inst_Tester.TesterRunnable_Arguments_arg2->value = (UInt8) Arg2_buf;\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_PRE_FreqReqRunnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ uint32 FreqReqSig_buf = 0;\r
+ Com_ReceiveSignal(FreqReqSig, &FreqReqSig_buf);\r
+ Rte_Inst_Tester.FreqReqRunnable_FreqReq_freq->value =\r
+ (UInt32) FreqReqSig_buf;\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_PRE_LoggerRunnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ Rte_Inst_Logger.LoggerRunnable_Result_result->value =\r
+ Rte_Buf_Tester_prototype_Result_result;\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_PRE_Logger2Runnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ Rte_Inst_Logger2.Logger2Runnable_Result_result->value =\r
+ Rte_Buf_Tester_prototype_Result_result;\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_POST_TesterRunnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ uint8 ResultSig_buf =\r
+ (uint8) Rte_Inst_Tester.TesterRunnable_Result_result->value;\r
+ Com_SendSignal(ResultSig, &ResultSig_buf);\r
+\r
+ Rte_WriteBuffer_Rte_Buf_Tester_prototype_Result_result(\r
+ Rte_Inst_Tester.TesterRunnable_Result_result->value);\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_POST_FreqReqRunnable() {\r
+ GetResource(RES_SCHEDULER);\r
+\r
+ uint32 FreqIndSig_buf =\r
+ (uint32) Rte_Inst_Tester.FreqReqRunnable_FreqReqInd_freq->value;\r
+ Com_SendSignal(FreqIndSig, &FreqIndSig_buf);\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+}\r
+\r
+void Rte_TesterRunnable() {\r
+ Rte_PRE_TesterRunnable();\r
+ TesterRunnable();\r
+ Rte_POST_TesterRunnable();\r
+}\r
+\r
+void Rte_FreqReqRunnable() {\r
+ Rte_PRE_FreqReqRunnable();\r
+ FreqReqRunnable();\r
+ Rte_POST_FreqReqRunnable();\r
+}\r
+\r
+Std_ReturnType Rte_Multiply(const UInt8 arg1, const UInt8 arg2,\r
+ UInt16* result) {\r
+ Std_ReturnType retVal = Multiply(arg1, arg2, result);\r
+ return retVal;\r
+}\r
+\r
+void Rte_LoggerRunnable() {\r
+ Rte_PRE_LoggerRunnable();\r
+ LoggerRunnable();\r
+}\r
+\r
+void Rte_Logger2Runnable() {\r
+ Rte_PRE_Logger2Runnable();\r
+ Logger2Runnable();\r
+}\r
+\r
+Std_ReturnType Rte_Start() {\r
+ return RTE_E_OK;\r
+}\r
+\r
+void StepTask() {\r
+ EventMaskType eventMask = 0;\r
+ while (1) {\r
+ WaitEvent(EVENT_MASK_StepEvent);\r
+ GetResource(RES_SCHEDULER);\r
+ GetEvent(TASK_ID_StepTask, &eventMask);\r
+ ClearEvent(EVENT_MASK_StepEvent);\r
+ ReleaseResource(RES_SCHEDULER);\r
+ if (eventMask & EVENT_MASK_StepEvent) {\r
+ Rte_TesterRunnable();\r
+ }\r
+ if (eventMask & EVENT_MASK_StepEvent) {\r
+ Rte_Logger2Runnable();\r
+ }\r
+ if (eventMask & EVENT_MASK_StepEvent) {\r
+ Rte_LoggerRunnable();\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+obj-y += Rte.o
+obj-y += Rte_Data.o
+obj-y += Rte_Cbk.o
+obj-y += Rte_Calculator.o
+obj-y += Rte_Tester.o
+obj-y += Rte_Logger.o
+obj-y += Rte_Logger2.o
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Calculator.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Calculator.c */\r
+#include <string.h>\r
+#include "Os.h"\r
+#include "Rte_Calculator.h"\r
+#include "Rte_Data.h"\r
+#include "Com.h"\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Calculator.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Calculator.h */\r
+\r
+#ifndef RTE_CALCULATOR_H\r
+#define RTE_CALCULATOR_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+Std_ReturnType Multiply(const UInt8 arg1, const UInt8 arg2, UInt16* result);\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Calculator_Internal.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Calculator.h */\r
+\r
+#ifndef RTE_CALCULATOR_H\r
+#define RTE_CALCULATOR_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+Std_ReturnType Multiply(const UInt8 arg1, const UInt8 arg2, UInt16* result);\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Cbk.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Cbk.c */\r
+#include "Os.h"\r
+#include "Rte_Data.h"\r
+\r
+void Rte_COMCbk_Arg1() {\r
+}\r
+\r
+void Rte_COMCbkTOut_Arg1() {\r
+}\r
+\r
+void Rte_COMCbk_Arg2() {\r
+}\r
+\r
+void Rte_COMCbkTOut_Arg2() {\r
+}\r
+\r
+void Rte_COMCbk_ResultSig() {\r
+}\r
+\r
+void Rte_COMCbkTOut_ResultSig() {\r
+}\r
+\r
+void Rte_COMCbk_FreqReqSig() {\r
+ Rte_FreqReqRunnable();\r
+}\r
+\r
+void Rte_COMCbkTOut_FreqReqSig() {\r
+}\r
+\r
+void Rte_COMCbk_FreqIndSig() {\r
+}\r
+\r
+void Rte_COMCbkTOut_FreqIndSig() {\r
+}\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Data.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Data.c */\r
+#include "Os.h"\r
+#include "Rte_Data.h"\r
+#include "Rte_Type.h"\r
+#include <string.h>\r
+\r
+UInt16 Rte_Buf_Tester_prototype_Result_result;\r
+\r
+void Rte_WriteBuffer_Rte_Buf_Tester_prototype_Result_result(UInt16 Value) {\r
+ Rte_Buf_Tester_prototype_Result_result = Value;\r
+}\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Data.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Data.h */\r
+\r
+#ifndef RTE_DATA_H\r
+#define RTE_DATA_H\r
+\r
+#include "Rte_Type.h"\r
+#include "cirq_buffer.h"\r
+\r
+extern UInt16 Rte_Buf_Tester_prototype_Result_result;\r
+\r
+void Rte_WriteBuffer_Rte_Buf_Tester_prototype_Result_result(UInt16 Value);\r
+\r
+void Rte_TesterRunnable();\r
+\r
+void Rte_FreqReqRunnable();\r
+\r
+Std_ReturnType Rte_Multiply(const UInt8 arg1, const UInt8 arg2, UInt16* result);\r
+\r
+void Rte_LoggerRunnable();\r
+\r
+void Rte_Logger2Runnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger.c */\r
+#include <string.h>\r
+#include "Os.h"\r
+#include "Rte_Logger.h"\r
+#include "Rte_Data.h"\r
+#include "Com.h"\r
+\r
+extern Rte_CDS_Logger Rte_Inst_Logger;\r
+\r
+UInt16 Rte_IRead_LoggerRunnable_Result_result() {\r
+ return Rte_Inst_Logger.LoggerRunnable_Result_result->value;\r
+}\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger.h */\r
+\r
+#ifndef RTE_LOGGER_H\r
+#define RTE_LOGGER_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+UInt16 Rte_IRead_LoggerRunnable_Result_result();\r
+\r
+void LoggerRunnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger2.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger2.c */\r
+#include <string.h>\r
+#include "Os.h"\r
+#include "Rte_Logger2.h"\r
+#include "Rte_Data.h"\r
+#include "Com.h"\r
+\r
+extern Rte_CDS_Logger2 Rte_Inst_Logger2;\r
+\r
+UInt16 Rte_IRead_Logger2Runnable_Result_result() {\r
+ return Rte_Inst_Logger2.Logger2Runnable_Result_result->value;\r
+}\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger2.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger2.h */\r
+\r
+#ifndef RTE_LOGGER2_H\r
+#define RTE_LOGGER2_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+UInt16 Rte_IRead_Logger2Runnable_Result_result();\r
+\r
+void Logger2Runnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger2_Internal.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger2.h */\r
+\r
+#ifndef RTE_LOGGER2_H\r
+#define RTE_LOGGER2_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+UInt16 Rte_IRead_Logger2Runnable_Result_result();\r
+\r
+void Logger2Runnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Logger_Internal.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Logger.h */\r
+\r
+#ifndef RTE_LOGGER_H\r
+#define RTE_LOGGER_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+UInt16 Rte_IRead_LoggerRunnable_Result_result();\r
+\r
+void LoggerRunnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Tester.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Tester.c */\r
+#include <string.h>\r
+#include "Os.h"\r
+#include "Rte_Tester.h"\r
+#include "Rte_Data.h"\r
+#include "Com.h"\r
+#include "Rte_Calculator.h"\r
+\r
+extern Rte_CDS_Tester Rte_Inst_Tester;\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg1() {\r
+ return Rte_Inst_Tester.TesterRunnable_Arguments_arg1->value;\r
+}\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg2() {\r
+ return Rte_Inst_Tester.TesterRunnable_Arguments_arg2->value;\r
+}\r
+\r
+void Rte_IWrite_TesterRunnable_Result_result(UInt16 Value) {\r
+ /** Note: this API is required to be called during execution of runnable TesterRunnable. If this API is not called invalid data will be written back to the RTE buffers. See note on page 113 of the AUTOSAR RTE specification. */\r
+ Rte_Inst_Tester.TesterRunnable_Result_result->value = Value;\r
+}\r
+\r
+Std_ReturnType Rte_Call_Tester_Calculator_Multiply(const UInt8 arg1,\r
+ const UInt8 arg2, UInt16* result) {\r
+ return Rte_Multiply(arg1, arg2, result);\r
+}\r
+\r
+UInt32 Rte_IRead_FreqReqRunnable_FreqReq_freq() {\r
+ return Rte_Inst_Tester.FreqReqRunnable_FreqReq_freq->value;\r
+}\r
+\r
+void Rte_IWrite_FreqReqRunnable_FreqReqInd_freq(UInt32 Value) {\r
+ /** Note: this API is required to be called during execution of runnable FreqReqRunnable. If this API is not called invalid data will be written back to the RTE buffers. See note on page 113 of the AUTOSAR RTE specification. */\r
+ Rte_Inst_Tester.FreqReqRunnable_FreqReqInd_freq->value = Value;\r
+}\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Tester.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Tester.h */\r
+\r
+#ifndef RTE_TESTER_H\r
+#define RTE_TESTER_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+#define Rte_Call_Calculator_Multiply Rte_Call_Tester_Calculator_Multiply\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg1();\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg2();\r
+\r
+void Rte_IWrite_TesterRunnable_Result_result(UInt16 Value);\r
+\r
+Std_ReturnType Rte_Call_Tester_Calculator_Multiply(const UInt8 arg1,\r
+ const UInt8 arg2, UInt16* result);\r
+\r
+UInt32 Rte_IRead_FreqReqRunnable_FreqReq_freq();\r
+\r
+void Rte_IWrite_FreqReqRunnable_FreqReqInd_freq(UInt32 Value);\r
+\r
+void TesterRunnable();\r
+\r
+void FreqReqRunnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Tester_Internal.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Tester.h */\r
+\r
+#ifndef RTE_TESTER_H\r
+#define RTE_TESTER_H\r
+\r
+#include "Rte_Type.h"\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg1();\r
+\r
+UInt8 Rte_IRead_TesterRunnable_Arguments_arg2();\r
+\r
+void Rte_IWrite_TesterRunnable_Result_result(UInt16 Value);\r
+\r
+Std_ReturnType Rte_Call_Tester_Calculator_Multiply(const UInt8 arg1,\r
+ const UInt8 arg2, UInt16* result);\r
+\r
+UInt32 Rte_IRead_FreqReqRunnable_FreqReq_freq();\r
+\r
+void Rte_IWrite_FreqReqRunnable_FreqReqInd_freq(UInt32 Value);\r
+\r
+void TesterRunnable();\r
+\r
+void FreqReqRunnable();\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* Configuration of module: Rte (Rte_Type.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC5567\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 0.0.9\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+/* Rte_Type.h */\r
+\r
+#ifndef RTE_TYPE_H\r
+#define RTE_TYPE_H\r
+\r
+#include "Rte.h"\r
+\r
+typedef void * Rte_Instance;\r
+\r
+typedef boolean Boolean;\r
+\r
+#define _DEFINED_TYPEDEF_FOR_Boolean_ \r
+\r
+typedef float Float;\r
+\r
+#define _DEFINED_TYPEDEF_FOR_Float_ \r
+\r
+typedef sint16 SInt16;\r
+#define SInt16_LowerLimit -32768\r
+#define SInt16_UpperLimit 32767\r
+\r
+#define _DEFINED_TYPEDEF_FOR_SInt16_ \r
+\r
+typedef sint32 SInt32;\r
+#define SInt32_LowerLimit -2147483648\r
+#define SInt32_UpperLimit 2147483647\r
+\r
+#define _DEFINED_TYPEDEF_FOR_SInt32_ \r
+\r
+typedef sint8 SInt8;\r
+#define SInt8_LowerLimit -128\r
+#define SInt8_UpperLimit 127\r
+\r
+#define _DEFINED_TYPEDEF_FOR_SInt8_ \r
+\r
+typedef uint16 UInt16;\r
+#define UInt16_LowerLimit 0\r
+#define UInt16_UpperLimit 65535\r
+\r
+#define _DEFINED_TYPEDEF_FOR_UInt16_ \r
+\r
+typedef uint32 UInt32;\r
+#define UInt32_LowerLimit 0\r
+#define UInt32_UpperLimit 4294967295\r
+\r
+#define _DEFINED_TYPEDEF_FOR_UInt32_ \r
+\r
+typedef uint8 UInt8;\r
+#define UInt8_LowerLimit 0\r
+#define UInt8_UpperLimit 255\r
+\r
+#define _DEFINED_TYPEDEF_FOR_UInt8_ \r
+\r
+typedef struct {\r
+ UInt8 value;\r
+} Rte_DE_Read_TesterRunnable_ReadArg1;\r
+\r
+typedef struct {\r
+ UInt8 value;\r
+} Rte_DE_Read_TesterRunnable_ReadArg2;\r
+\r
+typedef struct {\r
+ UInt16 value;\r
+} Rte_DE_Write_TesterRunnable_WriteResult;\r
+\r
+typedef struct {\r
+ UInt32 value;\r
+} Rte_DE_Read_FreqReqRunnable_ReadFreqReq;\r
+\r
+typedef struct {\r
+ UInt32 value;\r
+} Rte_DE_Write_FreqReqRunnable_WriteFreqReqInd;\r
+\r
+typedef struct {\r
+ UInt16 value;\r
+} Rte_DE_Read_LoggerRunnable_ReadResult;\r
+\r
+typedef struct {\r
+ UInt16 value;\r
+} Rte_DE_Read_Logger2Runnable_ReadResult;\r
+\r
+typedef struct {\r
+} Rte_PDS_Calculator_CalculatorOperations_P;\r
+typedef struct {\r
+} Rte_PDS_Calculator_CalculatorOperations_R;\r
+\r
+typedef struct {\r
+} Rte_PDS_Tester_CalculatorOperations_P;\r
+typedef struct {\r
+} Rte_PDS_Tester_CalculatorOperations_R;\r
+\r
+typedef struct {\r
+ Std_ReturnType (*Write_arg1)(UInt8);\r
+ Std_ReturnType (*Write_arg2)(UInt8);\r
+} Rte_PDS_Tester_ArgumentIf_P;\r
+typedef struct {\r
+ Std_ReturnType (*Read_arg1)(UInt8);\r
+ Std_ReturnType (*Read_arg2)(UInt8);\r
+} Rte_PDS_Tester_ArgumentIf_R;\r
+\r
+typedef struct {\r
+ Std_ReturnType (*Write_result)(UInt16);\r
+} Rte_PDS_Tester_ResultIf_P;\r
+typedef struct {\r
+ Std_ReturnType (*Read_result)(UInt16);\r
+} Rte_PDS_Tester_ResultIf_R;\r
+\r
+typedef struct {\r
+ Std_ReturnType (*Write_freq)(UInt32);\r
+} Rte_PDS_Tester_FreqReqIf_P;\r
+typedef struct {\r
+ Std_ReturnType (*Read_freq)(UInt32);\r
+} Rte_PDS_Tester_FreqReqIf_R;\r
+\r
+typedef struct {\r
+ Rte_DE_Read_TesterRunnable_ReadArg1* TesterRunnable_Arguments_arg1;\r
+ Rte_DE_Read_TesterRunnable_ReadArg2* TesterRunnable_Arguments_arg2;\r
+ Rte_DE_Read_FreqReqRunnable_ReadFreqReq* FreqReqRunnable_FreqReq_freq;\r
+ Rte_DE_Write_TesterRunnable_WriteResult* TesterRunnable_Result_result;\r
+ Rte_DE_Write_FreqReqRunnable_WriteFreqReqInd* FreqReqRunnable_FreqReqInd_freq;\r
+} Rte_CDS_Tester;\r
+\r
+typedef struct {\r
+ Std_ReturnType (*Write_result)(UInt16);\r
+} Rte_PDS_Logger_ResultIf_P;\r
+typedef struct {\r
+ Std_ReturnType (*Read_result)(UInt16);\r
+} Rte_PDS_Logger_ResultIf_R;\r
+\r
+typedef struct {\r
+ Rte_DE_Read_LoggerRunnable_ReadResult* LoggerRunnable_Result_result;\r
+} Rte_CDS_Logger;\r
+\r
+typedef struct {\r
+ Std_ReturnType (*Write_result)(UInt16);\r
+} Rte_PDS_Logger2_ResultIf_P;\r
+typedef struct {\r
+ Std_ReturnType (*Read_result)(UInt16);\r
+} Rte_PDS_Logger2_ResultIf_R;\r
+\r
+typedef struct {\r
+ Rte_DE_Read_Logger2Runnable_ReadResult* Logger2Runnable_Result_result;\r
+} Rte_CDS_Logger2;\r
+\r
+#endif\r
--- /dev/null
+\r
+\r
+PROJECTNAME=rte_simple\r
+ROOTDIR?=../../../..\r
+include $(ROOTDIR)/scripts/project_defaults.mk\r
+include $(ROOTDIR)/examples/rte_simple/rte_simple.mk\r
+\r
+ifneq (${MAKELEVEL},0) \r
+\r
+ # object files\r
+ PROJECT_C_FILES=$(notdir $(wildcard ../*.c))\r
+ obj-y += $(PROJECT_C_FILES:%.c=%.o)\r
+ \r
+ VPATH += $(ROOTDIR)/examples\r
+ VPATH += $(ROOTDIR)/examples/$(PROJECTNAME)\r
+\r
+endif\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/3.1.5 autosar_3-1-5.xsd">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>rte_simple_mpc5567qrtech</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="e933134b-ab53-4c9b-8075-815097cbc4a5">\r
+ <SHORT-NAME>rte_simple_mpc5567qrtech</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION />\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">MPC5567</SD>\r
+ <SD GID="GENDIR">${PROJECT_LOC}/config</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-EXTRACT-REF DEST="SYSTEM">/rte_simple_extract/rte_simple_extract</ECU-EXTRACT-REF>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/rte_simple_mpc5567qrtech/SwComposition_rte_simple_mpc5567qrtech</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/CanIf</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Com</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Det</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/EcuM</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/PduR</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Rte</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/EcuC</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Can</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Dio</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/rte_simple_mpc5567qrtech/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="b12f61f3-06aa-4f92-9b39-45f70fffdf3e">\r
+ <SHORT-NAME>SwComposition_rte_simple_mpc5567qrtech</SHORT-NAME>\r
+ <ECU-EXTRACT-REF DEST="SYSTEM">/rte_simple_extract/rte_simple_extract</ECU-EXTRACT-REF>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="4d83e597-90c1-4d3f-a705-7fc429969c15">\r
+ <SHORT-NAME>CanIf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.5</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/CanIf</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="eda70b57-11bd-4cdf-b638-9519212d3619">\r
+ <SHORT-NAME>CanIfDispatchConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDispatchConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
+ <VALUE />\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
+ <VALUE />\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE />\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
+ <VALUE />\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0dbd69ee-2890-4bae-b68f-bd81da282868">\r
+ <SHORT-NAME>CanIfDriverConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDriverConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfBusoffNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfReceiveIndication</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTransmitCancellation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTxConfirmation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f18a6f44-69e8-4c03-912b-2a81d7cde71e">\r
+ <SHORT-NAME>CanIfInitConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
+ <VALUE />\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanTXPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfDynamicCanTXPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="8b258b27-c416-4b76-a6be-7238d03f718f">\r
+ <SHORT-NAME>Hoh_1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="118f681e-c4c2-4898-a90b-2a75aa699fd5">\r
+ <SHORT-NAME>Hrh_1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfHrhType</DEFINITION-REF>\r
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+ <CONTAINER UUID="27ca5378-dc5d-41ed-8e6e-e072c9aabc95">\r
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+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsNumberOfCores</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/ArcOsIsrMaxCount</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="13341f07-800c-42bb-92fc-142661b95d00">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6efe1be-ba6f-4725-87bc-9dcca88d0353">\r
+ <SHORT-NAME>StartupTask</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="1583c915-9447-44b1-94e3-ba9474adb449">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6ba2f802-b7df-4086-9127-81afe7564afd">\r
+ <SHORT-NAME>StepTask</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StepEvent</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fadee99c-384c-45c7-80ad-bacf73ed4020">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="84a7ccc3-bbf0-4c38-99cc-8920f0405b93">\r
+ <SHORT-NAME>StepAlarm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/Counter1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="2c60f4c3-3029-4976-bdc4-9373b380157f">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ea35f8d3-85bb-4d74-95f7-b0abc8eb0179">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StepEvent</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StepTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6c247e60-bd37-4aa6-87f8-82f65ce14c38">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2b3062b7-134f-4fa5-a7d7-688dd0b6c8e0">\r
+ <SHORT-NAME>OsApplication1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsApplication</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsApplication/ArcOsAppCoreId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsApplication/OsTrusted</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppAlarmRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StepAlarm</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/Counter1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StartupTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
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+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/StepTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppAlarmRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/MainFunctionAlarm</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppTaskRef</DEFINITION-REF>\r
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+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppAlarmRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/BlinkerAlarm</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsApplication/OsAppTaskRef</DEFINITION-REF>\r
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+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6cb490b8-4cf0-4c24-a017-1cfc957da368">\r
+ <SHORT-NAME>OsApplicationHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsApplication/OsApplicationHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsApplication/OsApplicationHooks/OsAppErrorHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsApplication/OsApplicationHooks/OsAppShutdownHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsApplication/OsApplicationHooks/OsAppStartupHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ae9a5118-b552-4f22-af5a-a3912a537b5d">\r
+ <SHORT-NAME>StepEvent</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/ArcOsEventId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsEvent/ArcOsEventAutoMask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f6b88c14-731f-4156-9dc2-b1bb542da0db">\r
+ <SHORT-NAME>MainFunctionTask</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3d4a6633-3d19-4ecb-925d-f32c746f4587">\r
+ <SHORT-NAME>MainFunctionAlarm</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
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+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/rte_simple_mpc5567qrtech/Os/Counter1</VALUE-REF>\r
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+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="28437fdb-6270-49f7-b169-03383189afed">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f4199712-bda0-4366-a22f-45747fc2d2e7">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7484ad59-feb8-4ee6-bc9a-abc3db67c360">\r
+ <SHORT-NAME>BlinkerTask</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
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+ <CONTAINER UUID="a6db33eb-3669-4ded-873a-c2f18fe7f115">\r
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+ <CONTAINER UUID="cbd0de80-1099-4673-9f5b-6549c765b358">\r
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+ <CONTAINER UUID="65fe95e8-4bb8-4842-b956-be3a1fa58237">\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/ArcCanNumMailboxes</DEFINITION-REF>\r
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+ <VALUE>1</VALUE>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <VALUE>CanIf_Arc_Error</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="19115ed0-f3f0-4a6a-9d51-183494e82d84">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ <CONTAINER UUID="ef6aa42e-f2d9-45a7-8a26-7e3d1507e36a">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <CONTAINER UUID="995355ae-8c54-474a-b7c6-8ca237e89af2">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
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+ <REFERENCE-VALUES>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="8beda446-deaa-4522-8337-3a3e94e1c5f1">\r
+ <SHORT-NAME>Clock</SHORT-NAME>\r
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+ </ADMIN-DATA>\r
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+ <FLOAT-VALUE>\r
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+ <VALUE>0.0</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <CONTAINER UUID="abbec6bd-bfe2-4c2f-8949-e8793a33138b">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="5f5f54b8-b64f-488d-b8ab-dc9e8831fd27">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ </SDGS>\r
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+ <CONTAINER UUID="2d532b1a-3c04-42d9-bbcb-2925b38b6be0">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
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+ <VALUE>false</VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <CONTAINER UUID="1f3dd181-fe91-4d89-87fe-42fd6ce7bf5f">\r
+ <SHORT-NAME>LED_PORT</SHORT-NAME>\r
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+ <SDG GID="Arccore::IdentifiableOptions" />\r
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+ <VALUE>0</VALUE>\r
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+ <VALUE>DIO_MPC5567_GENERIC_PORT</VALUE>\r
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+ <CONTAINER UUID="c7540d44-ea56-4042-8a0a-097029c36fa3">\r
+ <SHORT-NAME>LED_CHANNEL</SHORT-NAME>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
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+ <MODULE-CONFIGURATION UUID="bfa628e5-168f-4481-8599-75fcd648f78a">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
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+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
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+ <CONTAINER UUID="645b91a2-820a-4f7b-81b8-4bb8187f8b81">\r
+ <SHORT-NAME>PortContainer_1</SHORT-NAME>\r
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+ <CONTAINER UUID="92d1d78f-265b-4189-b17d-384b8a2164e7">\r
+ <SHORT-NAME>CNTXA</SHORT-NAME>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
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+ <VALUE>PORT_PIN_OUT</VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <VALUE>83</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c0ffa3e0-0d86-4f20-803b-bbafab48da72">\r
+ <SHORT-NAME>CNRXA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>84</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3b730a79-e042-4c6b-86ec-337bec214ec3">\r
+ <SHORT-NAME>GPIO[0]</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7bc7ecbd-e09c-4122-94de-432c6f87d9bb">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
/* MPC55xx Reset Control Word(RCW) */\r
+#if defined(CFG_BOOT)\r
+flash(R) : ORIGIN = 0x0001c100, LENGTH = 2M\r
+#else \r
flash(R) : ORIGIN = 0x00000000, LENGTH = 2M\r
+#endif\r
ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x014000\r
ARCH_MCU=mpc5604b\r
\r
# CFG (y/n) macros\r
-CFG=PPC E200Z0 MPC55XX MPC560X MPC5604B BRD_MPC5604B_TRK VLE\r
+CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5604B BRD_MPC5604B_TRK VLE\r
\r
# What buildable modules does this board have, \r
# default or private\r
COMPILER?=cw\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
DEFAULT_CW_COMPILE= /opt/cw\r
+\r
+# Defines\r
+def-y += SRAM_SIZE=0xc000\r
+\r
+\r
--- /dev/null
+\r
+\r
+\r
+The Freescale MPC5606B is an PowerPC process with a e200Z0h core, VLE only \r
+ \r
+Datasheets:\r
+ See http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xB&webpageId=121120349534072559427E&nodeId=01624606C1427E&fromPage=tax\r
+ \r
+Board:\r
+ 8Mhz external crystal\r
+\r
+Supported compilers:\r
+ Code Warrior\r
+ \r
+Info: \r
+ MPC5606B\r
+ CPU: e200z0h (VLE only)\r
+ Freq: 64 Mhz\r
+ Flash: 1.0 MB, primary\r
+ 64K, data flash\r
+ RAM: 80K, ECC RAM\r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> 0x000f_ffff Flash\r
+ 0x0080_0000 -> 0x0080_ffff Data Flash\r
+ 0x4000_0000 -> 0x4001_3fff SRAM\r
+ \r
+ \r
+\r
+== SPI == \r
+\r
+Adding a SPI EEPROM (Microship 25LC160B)\r
+\r
+To the left are the pins as they are names in XPC56xxMBSCH (schema for the main board, page 11 of 12) \r
+\r
+<- XPC560S ->#<---------------------- MCU --->\r
+ # PAD Func \r
+----------------------------------------------\r
+SINB,PJ1-7 # PB[7] 23 1 SIN_0 \r
+SOUTB,PJ1-8 # PB[8] 24 1 SOUT_0 \r
+SCKB,PJ1-9 # PB[9] 25 1 SCK_0 \r
+PCSB1,PJ1-11 # PB[13] 29 3 PCS1_0 \r
+\r
+PCSB2,PJ1-12 # PB[12] 28 3 PCS2_0 NOT USED\r
+PCSB0,PJ1-10 # PH[4] 103 1 PCS0_0 NOT USED\r
+\r
+SPI MEMORY \r
+ 25LC160B\r
+ CS - Connect to PJ1-11\r
+ /WP - High\r
+ /HOLD - Low\r
+ Rest of the pins are obvious\r
+ \r
+ Connected with 5V logic\r
+\r
+---------------------------------- NOTE ----------------------------------\r
+ The xPC560S EVB v1.0.1 manual is total crap in chapter "3.8 Pin Mapping"\r
+ Known errors:\r
+ PJ1\r
+ PCS0.2, should be PCS1_0 \r
+ PJ9-Port F\r
+ As I understand it should map to Port F. However, PCS1_1 is\r
+ located on PCR[78]=PF[8] on CPU is connected to PF[0] on PJ9!! \r
+---------------------------------- NOTE ---------------------------------- \r
+ \r
+SPI_0\r
+ PJ1 Connector will have the following layout \r
+ (With ArcCore internal harness and SO/SI as seen from memory):\r
+\r
+ PJ1 \r
+ 1-X X-2\r
+ 3-X X-4 \r
+ 5-X X-6\r
+ SO/Brown 7-X X-8 SI/Orange\r
+ SCK/Blue 9-X X-10 \r
+ CS/Green 11-X X-12\r
+ 13-X X-14\r
+ 15-X X-16 \r
+ Gnd/Black 17-X X-18 VCC/Red \r
+ \r
+ \r
+ If software CS is used Connector PJ2 and PJ[0] is used for that\r
+ PJ2 \r
+ CS and PJ[0] 1-X X-2\r
+ 3-X X-4 \r
+ ... \r
+\r
+\r
+SPI_1\r
+\r
+ PCR[20]/PB[4]/SCK_1\r
+ PCR[21]/PB[5]/SOUT_1\r
+ PCR[22]/PB[6]/SIN_1\r
+\r
+ PJ5 \r
+ 1-X X-2\r
+ 3-X X-4\r
+ SCK/Blue 5-X X-6 SI/Orange\r
+ SO/Brown 7-X X-8 \r
+ 9-X X-10 \r
+ 11-X X-12\r
+ 13-X X-14\r
+ 15-X X-16 \r
+ Gnd/Black 17-X X-18 VCC/Red \r
+\r
+ PJ9\r
+ CS/Green (See NOTE)\r
+ | \r
+ ... 6 4 2 0\r
+ 7 5 3 1\r
+\r
+\r
+\r
+\r
+\r
+ \r
+ \r
+ \r
+\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5606b\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5606B BRD_MPC560X_XPC560B VLE\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS SPI EEP EA\r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=LINIF CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM WDGIF RTE J1939TP\r
+# Network management\r
+MOD_AVAIL+=COMM NM CANNM CANSM LINSM\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
+# CRC\r
+MOD_AVAIL+=CRC32 CRC16\r
+# Required modules\r
+MOD_USE += MCU KERNEL ECUM DET\r
+\r
+# Default cross compiler\r
+COMPILER?=cw\r
+DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
+DEFAULT_CW_COMPILE= /opt/cw\r
+\r
+# Defines\r
+def-y += SRAM_SIZE=0x14000\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dma.h"\r
+\r
+const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX\r
+ },\r
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
+ },
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC
+ }
+};\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ },
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ }
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{
+ {
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)\r
+ DmaMuxConfig,
+#endif
+ DmaChannelConfig,
+ DMA_FIXED_PRIORITY_ARBITRATION
+ }
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+typedef enum\r
+{
+ DMA_DSPI_A_COMMAND_CHANNEL,\r
+ DMA_DSPI_A_RESULT_CHANNEL,\r
+ DMA_DSPI_B_COMMAND_CHANNEL,\r
+ DMA_DSPI_B_RESULT_CHANNEL,\r
+
+ DMA_ADC_GROUP0_RESULT_CHANNEL,
+
+ DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+#endif /* DMA_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef EEP_CFG_H_
+#define EEP_CFG_H_
+
+
+#define EEP_USES_EXTERNAL_DRIVER
+
+#include "Spi.h"
+#include "Eep_ConfigTypes.h"
+
+
+// M95256 or 25LC160B
+#define E2_WREN 0x6 // Write Enable 0000 0110
+#define E2_WRDI 0x4 // Write Disable 0000 0100
+#define E2_RDSR 0x5 // Read Status Register 0000 0101
+ // 1 - Read data
+#define E2_WRSR 0x1 // Write Status Register 0000 0001
+ // 1 - Write data
+#define E2_READ 0x3 // Read from Memory Array 0000 0011
+ // 1 - Write 16-bit address
+ // n - 8 -bit read data
+#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
+ // 1 Write 16-bit address
+ // n - 8-bit reads
+
+/* EepGeneral */
+
+// Switches to activate or deactivate interrupt controlled job processing. true:
+// Interrupt controlled job processing enabled. false: Interrupt controlled job
+// processing disabled.
+#define EEP_USE_INTERRUPTS STD_OFF
+
+// Pre-processor switch to enable and disable development error detection.
+// true: Development error detection enabled. false: Development error
+// detection disabled.
+#define EEP_DEV_ERROR_DETECT STD_ON
+
+// Pre-processor switch to enable / disable the API to read out the modules
+// version information. true: Version info API enabled. false: Version info API
+// disabled.
+#define EEP_VERSION_INFO_API STD_ON
+
+// ndex of the driver, used by EA.
+#define EEP_DRIVER_INDEX 1
+
+// Switches to activate or deactivate write cycle reduction (EEPROM value is
+// read and compared before being overwritten). true: Write cycle reduction
+// enabled. false: Write cycle reduction disabled.
+#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
+
+// Container for runtime configuration parameters of the EEPROM driver.
+// Implementation Type: Eep_ConfigType.
+
+/* EepPublishedInformation
+ */
+
+// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
+#define EEP_TOTAL_SIZE TBD
+
+// Size of smallest erasable EEPROM data unit in bytes.
+#define EEP_ERASE_UNIT_SIZE TBD
+
+// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
+// Minimum expected size of Eep_LengthType.
+#define EEP_MINIMUM_LENGTH_TYPE TBD
+
+// Minimum expected size of Eep_AddressType.
+#define EEP_MINIMUM_ADDRESS_TYPE TBD
+
+// Size of smallest writable EEPROM data unit in bytes.
+#define EEP_WRITE_UNIT_SIZE TBD
+
+// Value of an erased EEPROM cell.
+#define EEP_ERASE_VALUE 0
+
+// Number of erase cycles specified for the EEP device (usually given in the
+// device data sheet).
+#define EEP_SPECIFIED_ERASE_CYCLES TBD
+
+// Size of smallest readable EEPROM data unit in bytes.
+#define EEP_READ_UNIT_SIZE TBD
+
+// Time for writing one EEPROM data unit.(float)
+#define EEP_WRITE_TIME TBD
+
+// Time for erasing one EEPROM data unit (float)
+#define EEP_ERASE_TIME TBD
+
+// Specified maximum number of write cycles under worst case conditions of
+// specific EEPROM hardware (e.g. +90°C)
+#define EEP_ALLOWED_WRITE_CYCLES x
+
+
+extern const Eep_ConfigType EepConfigData[];
+
+#define EEP_DEFAULT_CONFIG EepConfigData[0]
+
+#endif /*EEP_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+/* Configured for:
+ * Microchip 25LC160B (32 bytes pages)
+ */
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "debug.h"
+
+#define E2_M9525 1
+#define E2_25LC160B 2
+
+#define E2_CHIP E2_25LC160B
+
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
+}
+
+/*
+ * TODO: probably better to
+ */
+#define SPI_SEQ_EEP_CMD SPI_SEQ_CMD
+#define SPI_SEQ_EEP_CMD2 SPI_SEQ_CMD2
+#define SPI_SEQ_EEP_READ SPI_SEQ_READ
+#define SPI_SEQ_EEP_WRITE SPI_SEQ_WRITE
+
+#define SPI_CH_EEP_CMD SPI_CH_CMD
+#define SPI_CH_EEP_ADDR SPI_CH_ADDR
+#define SPI_CH_EEP_WREN SPI_CH_WREN
+#define SPI_CH_EEP_DATA SPI_CH_DATA
+
+
+const Eep_ExternalDriverType EepExternalDriver = {
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_EEP_CMD,
+ .EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
+ .EepReadSequence = SPI_SEQ_EEP_READ,
+ .EepWriteSequence = SPI_SEQ_EEP_WRITE,
+
+ // Jobs may be left out..
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_EEP_CMD,
+ .EepAddrChannel = SPI_CH_EEP_ADDR,
+ .EepWrenChannel = SPI_CH_EEP_WREN,
+ .EepDataChannel = SPI_CH_EEP_DATA,
+};
+
+
+
+const Eep_ConfigType EepConfigData[] = {
+ {
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+// .EepJobCallCycle = 0.2,
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+#if (E2_CHIP == E2_25LC160B)
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 32,
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 32,
+#elif (E2_CHIP == E2_M9525)
+ .EepFastReadBlockSize = 64,
+ .EepFastWriteBlockSize = 64,
+#endif
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x1000, /* 32K bit for M9525, 16K bit 25LC160B*/
+#if (E2_CHIP == E2_25LC160B)
+ .EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
+#elif (E2_CHIP == E2_M9525)
+ .EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
+#endif
+
+ .externalDriver = &EepExternalDriver,
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Fls.h"\r
+#include "flash.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#if defined(CFG_MPC5606B)\r
+\r
+/* TODO: This can actually be read from the flash instead */\r
+const FlashType flashInfo[] = {\r
+ /* NO RWW */\r
+\r
+ /* Bank 0, Array 0 (LOW) */\r
+ [0].sectCnt = 8,\r
+ [0].bankSize = 0x80000,\r
+// [0].bankRange = BANK_RANGE_CODE_LOW,\r
+ [0].regBase = 0xC3F88000UL,\r
+ [0].sectAddr[0] = 0, /* 0, B0F0, LOW */\r
+ [0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [0].sectAddr[1] = 0x08000, /* 1, B0F1, LOW */\r
+ [0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [0].sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */\r
+ [0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [0].sectAddr[3] = 0x10000, /* 3, B0F3, LOW */\r
+ [0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [0].sectAddr[4] = 0x18000, /* 4, B0F4, LOW */\r
+ [0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,\r
+ [0].sectAddr[5] = 0x20000, /* 5, B0F5, LOW */\r
+ [0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,\r
+ [0].sectAddr[6] = 0x40000, /* 6, B0F6, MID */\r
+ [0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
+ [0].sectAddr[7] = 0x60000, /* 7, B0F7, MID */\r
+ [0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
+ [0].sectAddr[8] = 0x80000, /* End, NOT a sector */\r
+\r
+ /* Bank 1, Data */\r
+ [1].sectCnt = 4,\r
+ [1].bankSize = 0x810000 - 0x800000,\r
+ [1].regBase = 0xC3F8C000UL,\r
+ [1].sectAddr[0] = 0x800000, /* LOW */\r
+ [1].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [1].sectAddr[1] = 0x804000, /* LOW */\r
+ [1].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [1].sectAddr[2] = 0x808000, /* LOW */\r
+ [1].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [1].sectAddr[3] = 0x80c000, /* LOW */\r
+ [1].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [1].sectAddr[4] = 0x810000, /* End, NOT a sector */\r
+\r
+ /* Bank 2, Array 1 (MID)*/\r
+ [2].sectCnt = 4,\r
+ [2].bankSize = 0x100000-0x80000,\r
+ [2].regBase = 0xC3FB0000UL,\r
+ [2].sectAddr[0] = 0x80000, /* 0, B2F0, LOW */\r
+ [2].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [2].sectAddr[1] = 0xa0000, /* 1, B2F1, LOW */\r
+ [2].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [2].sectAddr[2] = 0xc0000, /* 2, B2F2, MID */\r
+ [2].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
+ [2].sectAddr[3] = 0xe0000, /* 3, B2F3, MID */\r
+ [2].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
+ [2].sectAddr[4] = 0x100000, /* End, NOT a sector */\r
+};\r
+\r
+#else\r
+#error CPU NOT supported\r
+#endif\r
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+ .FlsInfo = flashInfo,\r
+// .FlsSectorList = &fls_evbSectorList[0],\r
+// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),\r
+// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Fls Flash Driver\r
+ * @{ */\r
+\r
+/** @file Fls_Cfg.h\r
+ * Definitions of configuration parameters for Flash Driver.\r
+ */\r
+\r
+\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#define USE_FLS_INFO STD_ON\r
+\r
+\r
+/* STD container : Fls\r
+ * FlsConfigSet 1..*\r
+ * FlsGeneral 1\r
+ * FlsPublishedInformation 1\r
+ */\r
+\r
+#include "MemIf_Types.h"\r
+\r
+/* FlsGeneral, 3.0 OK */\r
+#define FLS_VARIANT_PB STD_OFF\r
+#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */\r
+#define FLS_BASE_ADDRESS 0x00000000\r
+#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */\r
+#define FLS_COMPARE_API STD_ON\r
+#define FLS_DEV_ERROR_DETECT STD_ON\r
+#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */\r
+#define FLS_GET_JOB_RESULT_API STD_ON\r
+#define FLS_GET_STATUS_API STD_ON\r
+#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */\r
+//#define FLS_TOTAL_SIZE\r
+#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */\r
+#define FLS_VERSION_INFO_API STD_ON\r
+\r
+/* FlsPublishedInformation, 3.0 OK */\r
+#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */\r
+#define FLS_ERASE_TIME 0 /* NO SUPPORT */\r
+#define FLS_ERASED_VALUE 0xff /* NO SUPPORT */\r
+#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */\r
+#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */\r
+#define FLS_WRITE_TIME 0 /* NO SUPPORT */\r
+\r
+/* MCU Specific */\r
+#if defined(CFG_MPC5606B)\r
+\r
+#define FLASH_BANK_CNT 3\r
+#define FLASH_PAGE_SIZE 8\r
+#define FLASH_MAX_SECTORS 16\r
+#define FLS_TOTAL_SIZE ((16*4+512+512)*1024)\r
+\r
+#else\r
+#error CPU not supported\r
+#endif\r
+\r
+#if (USE_FLS_INFO==STD_ON)\r
+\r
+typedef struct Flash {\r
+ uint32_t size;\r
+ uint32_t sectCnt;\r
+ uint32_t bankSize;\r
+ uint32_t regBase;\r
+ uint32_t sectAddr[FLASH_MAX_SECTORS+1];\r
+ uint16_t addrSpace[FLASH_MAX_SECTORS+1];\r
+} FlashType;\r
+\r
+\r
+#else\r
+typedef struct {\r
+ Fls_LengthType FlsNumberOfSectors;\r
+ Fls_LengthType FlsPageSize;\r
+ Fls_LengthType FlsSectorSize;\r
+ Fls_AddressType FlsSectorStartaddress;\r
+} Fls_SectorType;\r
+#endif\r
+\r
+\r
+struct Flash;\r
+\r
+typedef struct {\r
+ void (*FlsAcErase)(); /* NO SUPPORT */\r
+ void (*FlsAcWrite)(); /* NO SUPPORT */\r
+ // FlsCallCycle N/A in core.\r
+ void (*FlsJobEndNotification)();\r
+ void (*FlsJobErrorNotification)();\r
+ uint32_t FlsMaxReadFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxReadNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsProtection; /* NO SUPPORT */\r
+#if (USE_FLS_INFO==STD_ON)\r
+ const struct Flash *FlsInfo;\r
+#else\r
+ const Fls_SectorType *FlsSectorList;\r
+#endif\r
+// const uint32 FlsSectorListSize; /* NO SUPPORT */\r
+} Fls_ConfigSetType;\r
+\r
+typedef Fls_ConfigSetType Fls_ConfigType;\r
+\r
+extern const Fls_ConfigSetType FlsConfigSet[];\r
+\r
+#endif /*FLS_CFG_H_*/\r
+/** @} */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef WDG_CFG_H_\r
+#define WDG_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "WdgIf_Types.h"\r
+\r
+typedef struct\r
+{\r
+ uint32 ReloadValue;\r
+ uint8 ActivationBit;\r
+}Wdg_SettingsType;\r
+\r
+typedef struct\r
+{\r
+ WdgIf_ModeType Wdg_DefaultMode;\r
+ Wdg_SettingsType WdgSettingsFast;\r
+ Wdg_SettingsType WdgSettingsSlow;\r
+ Wdg_SettingsType WdgSettingsOff;\r
+}Wdg_ModeConfigType;\r
+\r
+typedef struct\r
+{\r
+ const Wdg_GeneralType *Wdg_General;\r
+ const Wdg_ModeConfigType *Wdg_ModeConfig;\r
+}Wdg_ConfigType;\r
+\r
+ extern const Wdg_GeneralType WdgGeneral;\r
+ extern const Wdg_ConfigType WdgConfig;\r
+\r
+#endif /* WDG_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Wdg.h"\r
+\r
+const Wdg_ModeConfigType WdgModeConfig =\r
+{\r
+ .Wdg_DefaultMode = WDGIF_OFF_MODE,\r
+ .WdgSettingsFast =\r
+ {\r
+ .ReloadValue = 0x280, // 5 ms\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsSlow =\r
+ {\r
+ .ReloadValue = 0xA00, // 20 ms\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsOff =\r
+ {\r
+ .ReloadValue = 0x7D00,\r
+ .ActivationBit = 0,\r
+ },\r
+};\r
+\r
+const Wdg_GeneralType WdgGeneral =\r
+{\r
+ .Wdg_Index = 1,\r
+ .Wdg_TriggerLocationPtr = Wdg_Trigger,\r
+ .Wdg_SetModeLocationPtr = Wdg_SetMode,\r
+};\r
+\r
+\r
+const Wdg_ConfigType WdgConfig =\r
+{\r
+ .Wdg_General = &WdgGeneral,\r
+ .Wdg_ModeConfig = &WdgModeConfig,\r
+};\r
+\r
+\r
--- /dev/null
+\r
+# Version of build system\r
+REQUIRED_BUILD_SYSTEM_VERSION=1.0.0\r
+\r
+# Get configuration makefiles\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
+\r
+\r
+# Project settings\r
+\r
+SELECT_CONSOLE = RAMLOG\r
+\r
+SELECT_OPT = OPT_DEBUG \r
+\r
--- /dev/null
+\r
+MOD_USE += KERNEL ECUM MCU \r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Callout_Stubs.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Generated_Types.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#endif\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();/** @req EcuM2783 */\r
+ Det_Start();/** @req EcuM2634 */\r
+}\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ /* Set up default clock (Mcu_InitClock requires initRun==1) */\r
+ /* Ignoring return value */\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+#if defined(USE_WDG)\r
+ Wdg_Init(ConfigPtr->WdgConfig);\r
+#endif\r
+#if defined(USE_WDGM)\r
+ WdgM_Init(ConfigPtr->WdgMConfig);\r
+#endif\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EepConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_Init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+ // Setup J1939Tp\r
+ J1939Tp_Init(ConfigPtr->J1939TpConfig);\r
+#endif\r
+\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_UDPNM)\r
+ // Setup Udp Network Manager\r
+ UdpNm_Init(ConfigPtr->UdpNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+\r
+typedef enum {\r
+ ECUM_USER_User_1,\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+\r
+#endif /*ECUM_CFG_H_*/\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Generated_Types.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#ifdef CFG_ECUM_USE_SERVICE_COMPONENT\r
+#include "Rte_EcuM.h"\r
+#endif\r
+\r
+#include "EcuM_Types.h"\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#endif\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#endif\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+#if defined(USE_WDGIF)\r
+#include "WdgIf.h"\r
+#endif\r
+\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultSleepMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ const UdpNm_ConfigType* UdpNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ const J1939Tp_ConfigType* J1939TpConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+#if defined(USE_EEP)\r
+ const Eep_ConfigType* EepConfig;\r
+#endif\r
+#if defined(USE_SPI)\r
+ const Spi_ConfigType* SpiConfig;\r
+#endif\r
+#if defined(USE_WDG)\r
+ const Wdg_ConfigType* WdgConfig;\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ const WdgIf_ConfigType* WdgIfConfig;\r
+#endif\r
+#if defined(USE_WDGM)\r
+ const WdgM_ConfigType* WdgMConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_PBcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#if defined(USE_CANSM)\r
+extern const CanSM_ConfigType CanSM_Config;\r
+#endif\r
+#if defined(USE_NM)\r
+extern const Nm_ConfigType Nm_Config;\r
+#endif\r
+#if defined(USE_CANNM)\r
+extern const CanNm_ConfigType CanNm_Config;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+extern const UdpNm_ConfigType UdpNm_Config;\r
+#endif\r
+#if defined(USE_COMM)\r
+extern const ComM_ConfigType ComM_Config;\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+extern const J1939Tp_ConfigType J1939Tp_Config;\r
+#endif\r
+\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultSleepMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ .UdpNmConfig = &UdpNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_WDG)\r
+ .WdgConfig = &WdgConfig,\r
+#endif\r
+#if defined(USE_WDGM)\r
+ .WdgMConfig = &WdgMConfig,\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ .WdgIfConfig = &WdgIfConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+#if defined(USE_EEP)\r
+ .EepConfig = EepConfigData,\r
+#endif\r
+#if defined(USE_SPI)\r
+ .SpiConfig = &SpiConfigData,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 0,\r
+ .Pll2 = 64,\r
+ .Pll3 = 2,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = MCU_NBR_OF_RAM_SECTIONS,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error Mcu: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_OFF \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_Clock = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+\r
+#define MCU_NBR_OF_RAM_SECTIONS 0\r
+\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+ \r
+\r
+#include "kernel.h"\r
+\r
+\r
+// ############################### EXTERNAL REFERENCES #############################\r
+\r
+/* Application externals */\r
+\r
+/* Interrupt externals */\r
+\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+// ############################### APPLICATIONS #############################\r
+GEN_APPLICATION_HEAD = {\r
+ GEN_APPLICATION(\r
+ /* id */ APPLICATION_ID_OsApplication1,\r
+ /* name */ "OsApplication1",\r
+ /* trusted */ true, /* NOT CONFIGURABLE IN TOOLS */\r
+ /* core */ 0, /* Default value, multicore not enabled.*/\r
+ /* StartupHook */ NULL,\r
+ /* ShutdownHook */ NULL,\r
+ /* ErrorHook */ NULL,\r
+ /* rstrtTaskId */ 0 /* NOT CONFIGURABLE IN TOOLS */\r
+ ), \r
+};\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD = {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+ CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_RELATIVE, 100, 100, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD = {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_Counter1,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_eTask1,\r
+ EVENT_MASK_Event1,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+\r
+DECLARE_STACK(bTask3,2048);\r
+DECLARE_STACK(eTask1,2048);\r
+DECLARE_STACK(eTask2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD = {\r
+ GEN_BTASK( /* */OsIdle,\r
+ /* name */"OsIdle",\r
+ /* priority */0,\r
+ /* schedule */FULL,\r
+ /* autostart */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */0,\r
+ /* Accessing apps */1 \r
+ ),\r
+ GEN_BTASK(\r
+ /* */bTask3,\r
+ /* name */"bTask3",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* autostart */FALSE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_ETASK(\r
+ /* */eTask1,\r
+ /* name */"eTask1",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* name */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* event mask */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_ETASK(\r
+ /* */eTask2,\r
+ /* name */"eTask2",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* name */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* event mask */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+GEN_ISR_MAP = {\r
+ 0\r
+};\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error Os: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+// Application Id's\r
+#define APPLICATION_ID_OsApplication1 0\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// System counter\r
+#define OSMAXALLOWEDVALUE UINT_MAX// NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKSPERBASE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKDURATION 1000000UL // Time between ticks in nano seconds\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 OSMAXALLOWEDVALUE\r
+#define OSTICKSPERBASE_Counter1 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE_Counter1 1\r
+#define OS_TICKS2SEC_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000000UL )\r
+#define OS_TICKS2MS_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000UL )\r
+#define OS_TICKS2US_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000UL )\r
+#define OS_TICKS2NS_Counter1(_ticks) (OSTICKDURATION * _ticks)\r
+\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_Event1 1\r
+#define EVENT_MASK_Event2 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+\r
+#define TASK_ID_bTask3 1\r
+#define TASK_ID_eTask1 2\r
+#define TASK_ID_eTask2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void bTask3( void );\r
+void eTask1( void );\r
+void eTask2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 2\r
+//#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+#define OS_APPLICATION_CNT 1\r
+#define OS_SERVICE_CNT 0 /* ARCTICSTUDIO_GENERATOR_TODO */\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_APPLICATIONS STD_ON\r
+#define OS_USE_MEMORY_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_TASK_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_ISR_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+//#define OS_SC3 STD_ON /* NOT CONFIGURABLE IN TOOLS */ \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_PARAMETER_ACCESS STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_RES_SCHEDULER STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+\r
+#define OS_ISR_CNT 0\r
+#define OS_ISR2_CNT 0\r
+#define OS_ISR1_CNT 0\r
+\r
+#define OS_ISR_MAX_CNT 10\r
+\r
+#define OS_NUM_CORES 1\r
+\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+PROJECTNAME=os_simple\r
+ROOTDIR?=../../../..\r
+include $(ROOTDIR)/scripts/project_defaults.mk\r
+\r
+ifneq (${MAKELEVEL},0) \r
+\r
+ # object files\r
+ obj-y += os_simple.o\r
+ obj-y += system_hooks.o\r
+ \r
+ VPATH += $(ROOTDIR)/examples\r
+ VPATH += $(ROOTDIR)/examples/$(PROJECTNAME)\r
+\r
+endif\r
+\r
+\r
+\r
+\r
+\r
COMPILER?=cw\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
DEFAULT_CW_COMPILE= /opt/cw\r
+\r
+# Defines\r
+def-y += SRAM_SIZE=0xc000\r
--- /dev/null
+\r
+BOOT_IMAGE_ADDR=0x20000\r
+BOOT_BLOB_LOAD_ADDR=0x20100\r
+BOOT_BLOB_START_ADDR=$(BOOT_BLOB_LOAD_ADDR)\r
# Default cross compiler\r
DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
\r
+# Defines (can be 0x94000 if MMU is setup for more that 256K)\r
+def-y += SRAM_SIZE=0x40000\r
\r
VPATH += $(ROOTDIR)/examples\r
VPATH += $(ROOTDIR)/examples/$(PROJECTNAME)\r
-\r
+ \r
endif\r
\r
\r
\r
\r
\r
+\r
/* Flash sizes\r
* 5668, 2.0M\r
*/\r
-flash(R) : ORIGIN = 0x00000000, LENGTH = 2M\r
+#if defined(CFG_BOOT)\r
+flash(R) : ORIGIN = 0x00020100, LENGTH = 2M\r
/* Ram sizes\r
* 5668G: 512K + 80K\r
*/\r
+ #else\r
+flash(R) : ORIGIN = 0x00000000, LENGTH = 2M\r
+#endif\r
+ \r
+ \r
ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x080000\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<VALUE>PENDING</VALUE>\r
</ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComRxDataTimeoutAction</DEFINITION-REF>\r
+ <VALUE>NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<CONTAINER UUID="7dd06b07-796d-4fc1-ba0b-4f5181b6c9c8">\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<VALUE>TRIGGERED</VALUE>\r
</ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComRxDataTimeoutAction</DEFINITION-REF>\r
+ <VALUE>NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<CONTAINER UUID="ae24e011-a990-4da9-b31a-922f4e9db3c8">\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<VALUE>PENDING</VALUE>\r
</ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComRxDataTimeoutAction</DEFINITION-REF>\r
+ <VALUE>NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<CONTAINER UUID="19c577da-ea27-429d-91b9-43a72b575cab">\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<VALUE>TRIGGERED</VALUE>\r
</ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComRxDataTimeoutAction</DEFINITION-REF>\r
+ <VALUE>NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<CONTAINER UUID="f51bb691-2289-4f69-9f43-e54fe0a555fb">\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<VALUE>PENDING</VALUE>\r
</ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComRxDataTimeoutAction</DEFINITION-REF>\r
+ <VALUE>NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
</SUB-CONTAINERS>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
</ELEMENTS>\r
- <SUB-PACKAGES>\r
- <AR-PACKAGE UUID="d6752ac1-8921-416a-b21a-90618507b8ec">\r
- <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
- <ELEMENTS>\r
- <SYSTEM-SIGNAL UUID="621d2baf-b15a-4762-bdce-b3c4041fefd0">\r
- <SHORT-NAME>Arg1</SHORT-NAME>\r
- <INIT-VALUE-REF DEST="INTEGER-LITERAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/IntegerLiterals/Arg1InitValue/Arg1InitValueLiteral</INIT-VALUE-REF>\r
- <LENGTH>8</LENGTH>\r
- </SYSTEM-SIGNAL>\r
- <SYSTEM-SIGNAL UUID="2e984323-7a3d-4dcc-a8e4-b96b83ede7ff">\r
- <SHORT-NAME>ResultSig</SHORT-NAME>\r
- <INIT-VALUE-REF DEST="INTEGER-LITERAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/IntegerLiterals/ResultSigInitValue/ResultSigInitValueLiteral</INIT-VALUE-REF>\r
- <LENGTH>8</LENGTH>\r
- </SYSTEM-SIGNAL>\r
- <SYSTEM-SIGNAL UUID="cd67d3b0-05a7-4484-8a09-720f56e57b43">\r
- <SHORT-NAME>Arg2</SHORT-NAME>\r
- <INIT-VALUE-REF DEST="INTEGER-LITERAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/IntegerLiterals/Arg2InitValue/Arg2InitValueLiteral</INIT-VALUE-REF>\r
- <LENGTH>8</LENGTH>\r
- </SYSTEM-SIGNAL>\r
- <SYSTEM-SIGNAL UUID="f6e1d366-e5a5-4a15-b271-7d1ede75ff76">\r
- <SHORT-NAME>FreqIndSig</SHORT-NAME>\r
- <INIT-VALUE-REF DEST="INTEGER-LITERAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/IntegerLiterals/FreqIndSigInitValue/FreqIndSigInitValueLiteral</INIT-VALUE-REF>\r
- <LENGTH>32</LENGTH>\r
- </SYSTEM-SIGNAL>\r
- <SYSTEM-SIGNAL UUID="edbd6fdf-d43b-45f8-9416-a267a595460e">\r
- <SHORT-NAME>FreqReqSig</SHORT-NAME>\r
- <INIT-VALUE-REF DEST="INTEGER-LITERAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/IntegerLiterals/FreqReqSigInitValue/FreqReqSigInitValueLiteral</INIT-VALUE-REF>\r
- <LENGTH>32</LENGTH>\r
- </SYSTEM-SIGNAL>\r
- </ELEMENTS>\r
- <SUB-PACKAGES>\r
- <AR-PACKAGE>\r
- <SHORT-NAME>Data</SHORT-NAME>\r
- <ELEMENTS>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>UInt8</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">255</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>UInt16</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>UInt32</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">4294967295</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>SInt8</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>SInt16</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- <INTEGER-TYPE>\r
- <SHORT-NAME>SInt32</SHORT-NAME>\r
- <SW-DATA-DEF-PROPS />\r
- <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
- <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
- </INTEGER-TYPE>\r
- </ELEMENTS>\r
- <SUB-PACKAGES>\r
- <AR-PACKAGE>\r
- <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
- <ELEMENTS>\r
- <CONSTANT-SPECIFICATION>\r
- <SHORT-NAME>Arg1InitValue</SHORT-NAME>\r
- <VALUE>\r
- <INTEGER-LITERAL UUID="080df379-fc64-4efd-bbc9-d32088afb7cc">\r
- <SHORT-NAME>Arg1InitValueLiteral</SHORT-NAME>\r
- <VALUE>5</VALUE>\r
- </INTEGER-LITERAL>\r
- </VALUE>\r
- </CONSTANT-SPECIFICATION>\r
- <CONSTANT-SPECIFICATION>\r
- <SHORT-NAME>ResultSigInitValue</SHORT-NAME>\r
- <VALUE>\r
- <INTEGER-LITERAL UUID="d1928d1c-e6e5-460f-9dbd-7ae73ed5ee8b">\r
- <SHORT-NAME>ResultSigInitValueLiteral</SHORT-NAME>\r
- <VALUE>0</VALUE>\r
- </INTEGER-LITERAL>\r
- </VALUE>\r
- </CONSTANT-SPECIFICATION>\r
- <CONSTANT-SPECIFICATION>\r
- <SHORT-NAME>Arg2InitValue</SHORT-NAME>\r
- <VALUE>\r
- <INTEGER-LITERAL UUID="a958db62-4b46-4945-bf1e-361f33bac22a">\r
- <SHORT-NAME>Arg2InitValueLiteral</SHORT-NAME>\r
- <VALUE>3</VALUE>\r
- </INTEGER-LITERAL>\r
- </VALUE>\r
- </CONSTANT-SPECIFICATION>\r
- <CONSTANT-SPECIFICATION>\r
- <SHORT-NAME>FreqIndSigInitValue</SHORT-NAME>\r
- <VALUE>\r
- <INTEGER-LITERAL UUID="2336cf72-d52c-411b-b500-8853d0f429e0">\r
- <SHORT-NAME>FreqIndSigInitValueLiteral</SHORT-NAME>\r
- <VALUE>0</VALUE>\r
- </INTEGER-LITERAL>\r
- </VALUE>\r
- </CONSTANT-SPECIFICATION>\r
- <CONSTANT-SPECIFICATION>\r
- <SHORT-NAME>FreqReqSigInitValue</SHORT-NAME>\r
- <VALUE>\r
- <INTEGER-LITERAL UUID="51e36755-d899-4001-be53-0ac283f450b6">\r
- <SHORT-NAME>FreqReqSigInitValueLiteral</SHORT-NAME>\r
- <VALUE>1000</VALUE>\r
- </INTEGER-LITERAL>\r
- </VALUE>\r
- </CONSTANT-SPECIFICATION>\r
- </ELEMENTS>\r
- </AR-PACKAGE>\r
- </SUB-PACKAGES>\r
- </AR-PACKAGE>\r
- </SUB-PACKAGES>\r
- </AR-PACKAGE>\r
- </SUB-PACKAGES>\r
</AR-PACKAGE>\r
</TOP-LEVEL-PACKAGES>\r
</AUTOSAR>\r
* @param str Pointer to the string to write to\r
* @param base The base\r
*/\r
-void itoa(int value, char* str, int base) {\r
+char * itoa(int value, char* str, int base) {\r
xtoa(value, str, base, (value < 0));\r
+ return str;\r
}\r
\r
//#include "SchM_Dem.h"\r
#include "MemMap.h"\r
#include "Cpu.h"\r
-#include "DEM_Types.h"\r
-#include "DEM_Lcfg.h"\r
+#include "Dem_Types.h"\r
+#include "Dem_Lcfg.h"\r
\r
#define USE_DEBUG_PRINTF\r
#include "debug.h"\r
/*\r
* Local types\r
*/\r
+#if !defined(USE_DCM)\r
+typedef uint8 Dcm_NegativeResponseCodeType;\r
+#define DCM_E_POSITIVERESPONSE ((Dcm_NegativeResponseCodeType)0x00)\r
+#endif\r
\r
// DtcFilterType\r
typedef struct {\r
}\r
}\r
faultCounterAfterDebounce = eventStatusRecPtr->faultDetectionCounter;\r
- \r
+\r
eventStatusRecPtr->errorStatusChanged = FALSE;\r
\r
if (eventStatus == DEM_EVENT_STATUS_FAILED) {\r
//exchange buffer data\r
memcpy(&temp,&freezeFrameBuf[i],sizeof(FreezeFrameRecType));\r
memcpy(&freezeFrameBuf[i],&freezeFrameBuf[j],sizeof(FreezeFrameRecType));\r
- memcpy(&freezeFrameBuf[j],&temp,sizeof(FreezeFrameRecType)); \r
+ memcpy(&freezeFrameBuf[j],&temp,sizeof(FreezeFrameRecType));\r
}\r
}\r
}\r
* Procedure: retrieveEventStatusBit\r
* Description: retrieve Event Status Bit\r
*/\r
-static boolean retrieveEventStatusBit(FreezeFrameRecType *freezeFrameBuf, \r
- uint16 length , \r
- Dem_EventStatusExtendedType nBit, \r
+static boolean retrieveEventStatusBit(FreezeFrameRecType *freezeFrameBuf,\r
+ uint16 length ,\r
+ Dem_EventStatusExtendedType nBit,\r
FreezeFrameRecType **freezeFrame)\r
{\r
boolean freezeFrameFound = FALSE;\r
if(freezeFrameFound == TRUE){\r
*freezeFrame = &freezeFrameBuf[i];\r
}\r
- } \r
+ }\r
}\r
\r
return freezeFrameFound;\r
static boolean lookupFreezeFrameForDisplacementPreInit(FreezeFrameRecType **freezeFrame)\r
{\r
boolean freezeFrameFound = FALSE;\r
- \r
+\r
/* Bubble sort:rearrange priMemFreezeFrameBuffer from little to big */\r
bubbleSort(preInitFreezeFrameBuffer, DEM_MAX_NUMBER_FF_DATA_PRE_INIT);\r
\r
if(freezeFrameFound == FALSE){\r
freezeFrameFound = retrieveEventStatusBit(preInitFreezeFrameBuffer, DEM_MAX_NUMBER_FF_DATA_PRE_INIT, DEM_TEST_FAILED, freezeFrame);\r
}\r
- \r
+\r
/* if all confirmed,lookup the oldest active dtc */\r
if(freezeFrameFound == FALSE){\r
*freezeFrame = &preInitFreezeFrameBuffer[0];\r
freezeFrameFound = TRUE;\r
- } \r
+ }\r
\r
return freezeFrameFound;\r
}\r
static boolean lookupFreezeFrameForDisplacement(FreezeFrameRecType **freezeFrame)\r
{\r
boolean freezeFrameFound = FALSE;\r
- \r
+\r
bubbleSort(priMemFreezeFrameBuffer, DEM_MAX_NUMBER_FF_DATA_PRI_MEM);\r
\r
/* Find out the oldest not confirmed dtc */\r
}\r
\r
/* If all confirmed,lookup the oldest active dtc */\r
- if(freezeFrameFound == FALSE){ \r
+ if(freezeFrameFound == FALSE){\r
*freezeFrame = &priMemFreezeFrameBuffer[0];\r
- freezeFrameFound = TRUE; \r
+ freezeFrameFound = TRUE;\r
}\r
\r
return freezeFrameFound;\r
uint32 i = 0;\r
uint32 j = 0;\r
uint32 k = 0;\r
- \r
+\r
/* Bubble sort:rearrange priMemFreezeFrameBuffer from little to big */\r
for(i=0;i<DEM_MAX_NUMBER_FF_DATA_PRI_MEM;i++){\r
if(priMemFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL){\r
//exchange buffer data\r
memcpy(&temp,&priMemFreezeFrameBuffer[i],sizeof(FreezeFrameRecType));\r
memcpy(&priMemFreezeFrameBuffer[i],&priMemFreezeFrameBuffer[j],sizeof(FreezeFrameRecType));\r
- memcpy(&priMemFreezeFrameBuffer[j],&temp,sizeof(FreezeFrameRecType)); \r
+ memcpy(&priMemFreezeFrameBuffer[j],&temp,sizeof(FreezeFrameRecType));\r
}\r
\r
}\r
- \r
+\r
}\r
priMemFreezeFrameBuffer[i].timeStamp = k++;\r
}\r
- \r
+\r
}\r
/* update the current timeStamp */\r
*timeStamp = k;\r
* Procedure: getFreezeFrameData\r
* Description: get FF data according configuration \r
*/\r
-static void getFreezeFrameData(const Dem_EventParameterType *eventParam, \r
+static void getFreezeFrameData(const Dem_EventParameterType *eventParam,\r
FreezeFrameRecType *freezeFrame,\r
Dem_EventStatusType eventStatus,\r
EventStatusRecType *eventStatusRec)\r
else{\r
DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_E_FF_TOO_BIG);\r
break;\r
- } \r
+ }\r
}\r
else{\r
//TODO:RTE should provide the port\r
DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_FREEZEFRAME_ID, DEM_DSP_DID_USE_PORT_IS_TRUE);\r
}\r
- } \r
+ }\r
}\r
\r
}\r
if(FF_TimeStamp > DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT){\r
rearrangeFreezeFrameTimeStamp(&FF_TimeStamp);\r
}\r
- \r
+\r
freezeFrame->timeStamp = FF_TimeStamp;\r
\r
FF_TimeStamp++;\r
freezeFrame->eventId = DEM_EVENT_ID_NULL;\r
freezeFrame->dataSize = storeIndex;\r
freezeFrame->checksum = 0;\r
- } \r
+ }\r
}\r
\r
\r
if (eventIdFreePositionFound) {\r
memcpy(&preInitFreezeFrameBuffer[i-1], freezeFrame, sizeof(FreezeFrameRecType));\r
}\r
- else { \r
+ else {\r
/* do displacement */\r
if(lookupFreezeFrameForDisplacementPreInit(&freezeFrameLocal)){\r
memcpy(freezeFrameLocal, freezeFrame, sizeof(FreezeFrameRecType));\r
preInitFreezeFrameBuffer[i].occurrence += EventBuffer->occurrence;\r
}\r
}\r
- \r
+\r
}\r
/*\r
* Procedure: initCurrentFreezeFrameTimeStamp\r
\r
/* Find out the biggest timestamp in the last power on */\r
for (i = 0; i<DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++){\r
- if((priMemFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL) && \r
+ if((priMemFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL) &&\r
(priMemFreezeFrameBuffer[i].timeStamp > temp)){\r
temp = priMemFreezeFrameBuffer[i].timeStamp;\r
}\r
preInitFreezeFrameBuffer[i].timeStamp += temp;\r
}\r
}\r
- *timeStampPtr += temp; \r
+ *timeStampPtr += temp;\r
Irq_Restore(state);\r
}\r
\r
}\r
else{\r
DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_FF_DATA_PRI_MEM_ID, DEM_E_PRI_MEM_FF_DATA_BUFF_FULL);\r
- } \r
+ }\r
}\r
}\r
\r
uint16 i;\r
\r
if (*freezeFrameClassPtr != NULL) {\r
- for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_FREEZEFRAME_DATA) && ((*freezeFrameClassPtr)->FFIdClassRef[i].Arc_EOL != TRUE); i++) { \r
+ for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_FREEZEFRAME_DATA) && ((*freezeFrameClassPtr)->FFIdClassRef[i].Arc_EOL != TRUE); i++) {\r
if((*freezeFrameClassPtr)->FFIdClassRef[i].DidReadDataLengthFnc != NULL){\r
callbackReturnCode = (*freezeFrameClassPtr)->FFIdClassRef[i].DidReadDataLengthFnc(&dataSizeLocal);\r
if(callbackReturnCode != E_OK){\r
- return (dataSizeFound = FALSE); \r
+ return (dataSizeFound = FALSE);\r
}\r
}\r
else{\r
dataSizeLocal = (*freezeFrameClassPtr)->FFIdClassRef[i].PidOrDidSize;\r
}\r
- \r
+\r
*dataSize += dataSizeLocal + DEM_DID_IDENTIFIER_SIZE_OF_BYTES;\r
}\r
\r
}\r
}\r
\r
- \r
+\r
}\r
else {\r
// Operation cycle not started\r
else{\r
// do nothing\r
}\r
- } \r
+ }\r
}\r
}\r
else {\r
{\r
uint16 i;\r
boolean agingRecFound = FALSE;\r
- \r
+\r
for (i = 0; i < DEM_MAX_NUMBER_AGING_PRI_MEM && (!agingRecFound); i++) {\r
if(priMemAgingBuffer[i].eventId == eventId){\r
agingRecFound = TRUE;\r
}\r
\r
\r
+\r
// Validate extended data records stored in primary memory\r
for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; i++) {\r
entryValid = checkEntryValid(priMemExtDataBuffer[i].eventId);\r
* Interface for basic software scheduler\r
*/\r
void Dem_MainFunction(void)/** @req DEM125 */\r
-{ \r
+{\r
if (FFIsModified) {\r
storeFreezeFrameDataPerMem(FreezeFrameBlockId);\r
}\r
resetEventStatusRec(eventParam);\r
storeFreezeFrameDataPerMem();\r
break;\r
- \r
+\r
case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
- \r
+\r
break;\r
- \r
- case DEM_DTC_ORIGIN_SECONDARY_MEMORY: \r
+\r
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
// Not yet supported\r
returnCode = DEM_CLEAR_WRONG_DTCORIGIN;\r
* Procedure: Dem_GetFreezeFrameDataByDTC\r
* Reentrant: No\r
*/\r
-/** @req DEM236 */ \r
+/** @req DEM236 */\r
Dem_ReturnGetFreezeFrameDataByDTCType Dem_GetFreezeFrameDataByDTC(uint32 dtc,Dem_DTCKindType dtcKind,Dem_DTCOriginType dtcOrigin,uint8 recordNumber,uint8* destBuffer,uint8* bufSize)\r
{\r
Dem_ReturnGetFreezeFrameDataByDTCType returnCode = DEM_GET_FFDATABYDTC_WRONG_DTC;\r
}\r
*arraySize = didNum;\r
}\r
- \r
+\r
}\r
else{\r
returnCode = DEM_GET_ID_WRONG_FF_TYPE;\r
else{\r
returnCode = DEM_GET_ID_WRONG_DTC;\r
}\r
- \r
- } \r
+\r
+ }\r
else{\r
DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFREEZEFRAMEDATAIDENTIFIERBYDTC_ID, DEM_E_UNINIT);\r
}\r
* Reentrant: No\r
*/\r
/** @req DEM238 */\r
-Dem_ReturnGetSizeOfFreezeFrameType Dem_GetSizeOfFreezeFrame(uint32 dtc,Dem_DTCKindType dtcKind,Dem_DTCOriginType dtcOrigin,uint8 recordNumber,uint16* sizeOfFreezeFrame) \r
+Dem_ReturnGetSizeOfFreezeFrameType Dem_GetSizeOfFreezeFrame(uint32 dtc,Dem_DTCKindType dtcKind,Dem_DTCOriginType dtcOrigin,uint8 recordNumber,uint16* sizeOfFreezeFrame)\r
{\r
Dem_ReturnGetSizeOfFreezeFrameType returnCode = DEM_GET_SIZEOFFF_PENDING;\r
Dem_FreezeFrameClassType const *FFDataRecordClass = NULL;\r
EventStatusRecType *eventRec;\r
uint16 dataSize = 0;\r
uint16 i = 0;\r
- \r
+\r
if (demState == DEM_INITIALIZED) {\r
if (lookupDtcEvent(dtc, &eventRec)) {\r
if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
dataSize = FFDataRecordClass->FFIdClassRef[i].PidOrDidSize;\r
}\r
*sizeOfFreezeFrame += dataSize+DEM_DID_IDENTIFIER_SIZE_OF_BYTES;/** @req DEM074 */\r
- returnCode = DEM_GET_SIZEOFFF_OK; \r
- } \r
+ returnCode = DEM_GET_SIZEOFFF_OK;\r
+ }\r
}\r
}\r
else{\r
else{\r
returnCode = DEM_GET_SIZEOFFF_WRONG_DTC;\r
}\r
- \r
- } \r
+\r
+ }\r
else{\r
DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFREEZEFRAMEDATAIDENTIFIERBYDTC_ID, DEM_E_UNINIT);\r
returnCode = DEM_GET_SIZEOFFF_PENDING;\r
/***********************************\r
* OBD-specific Interfaces (8.3.6) *\r
***********************************/\r
+\r
+\r
+\r
#include "arc.h"\r
#include "Adc_Internal.h"\r
\r
+#ifndef CFG_MPC560X\r
+#define ADC_NOF_GROUP_PER_CONTROLLER 100\r
+#endif\r
+\r
/* Validate functions used for development error check */\r
#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
Std_ReturnType ValidateInit(Adc_StateType adcState, Adc_APIServiceIDType api)\r
Std_ReturnType ValidateGroup(const Adc_ConfigType *ConfigPtr, Adc_GroupType group,Adc_APIServiceIDType api)\r
{\r
Std_ReturnType res = E_OK;\r
- if(!((group >= 0) && (group < ConfigPtr->nbrOfGroups))) {\r
+ if(!(((group % ADC_NOF_GROUP_PER_CONTROLLER) >= 0) && ((group % ADC_NOF_GROUP_PER_CONTROLLER) < ConfigPtr->nbrOfGroups))) {\r
Det_ReportError(MODULE_ID_ADC,0,api,ADC_E_PARAM_GROUP );\r
res = E_NOT_OK;\r
}\r
}\r
else\r
{\r
- returnValue = ConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ returnValue = ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus;\r
}\r
#else\r
- returnValue = ConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ returnValue = ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus;\r
#endif\r
return (returnValue);\r
}\r
{\r
res = E_NOT_OK;\r
}\r
- else if (ConfigPtr->groupConfigPtr[group].groupCallback == NULL)\r
+ else if (ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].groupCallback == NULL)\r
{\r
res = E_NOT_OK;\r
Det_ReportError(MODULE_ID_ADC,0,ADC_ENABLEGROUPNOTIFICATION_ID ,ADC_E_NOTIF_CAPABILITY );\r
res = E_OK;\r
#endif\r
if (E_OK == res){\r
- ConfigPtr->groupConfigPtr[group].status->notifictionEnable = 1;\r
+ ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->notifictionEnable = 1;\r
}\r
}\r
\r
{\r
res = E_NOT_OK;\r
}\r
- else if (ConfigPtr->groupConfigPtr[group].groupCallback == NULL)\r
+ else if (ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].groupCallback == NULL)\r
{\r
res = E_NOT_OK;\r
Det_ReportError(MODULE_ID_ADC,0,ADC_DISABLEGROUPNOTIFICATION_ID ,ADC_E_NOTIF_CAPABILITY );\r
res = E_OK;\r
#endif\r
if (E_OK == res){\r
- ConfigPtr->groupConfigPtr[group].status->notifictionEnable = 0;\r
+ ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->notifictionEnable = 0;\r
}\r
}\r
#endif\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus)\r
{\r
/* ADC388. */\r
returnValue = E_NOT_OK;\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if ( NULL == ConfigPtr->groupConfigPtr[group].status->resultBufferPtr )\r
+ else if ( NULL == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr )\r
{\r
/* ResultBuffer not set, ADC424 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUFFER_UNINIT );\r
returnValue = E_NOT_OK;\r
}\r
- else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].triggerSrc))\r
{\r
/* Wrong trig source, ADC133. */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
returnValue = E_NOT_OK;\r
}\r
- else if (!((ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
- (ADC_STREAM_COMPLETED == ConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ else if (!((ADC_IDLE == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus) ||\r
+ (ADC_STREAM_COMPLETED == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus)))\r
{\r
/* Group status not OK, ADC351, ADC428 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUSY );\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].triggerSrc))\r
{\r
/* Wrong trig source, ADC164. */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STOPGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
returnValue = E_NOT_OK;\r
}\r
- else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus)\r
{\r
/* Group status not OK, ADC241 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STOPGROUPCONVERSION_ID, ADC_E_IDLE );\r
#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
if(ValidateInit(adcState, ADC_DEINIT_ID) == E_OK)\r
{\r
- for (Adc_GroupType group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (Adc_GroupType group = (Adc_GroupType)0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Check ADC is IDLE or COMPLETE*/\r
- if((ConfigPtr->groupConfigPtr[group].status->groupStatus != ADC_IDLE) && (ConfigPtr->groupConfigPtr[group].status->groupStatus != ADC_STREAM_COMPLETED))\r
+ if((ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus != ADC_IDLE) && (ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus != ADC_STREAM_COMPLETED))\r
{\r
Det_ReportError(MODULE_ID_ADC,0,ADC_DEINIT_ID, ADC_E_BUSY );\r
returnValue = E_NOT_OK;\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if(ConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_IDLE)\r
+ else if(ConfigPtr->groupConfigPtr[group%ADC_NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_IDLE)\r
{ /** @req ADC215 Check ADC is not in IDLE */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_GETSTREAMLASTPOINTER_ID, ADC_E_IDLE );\r
returnValue = E_NOT_OK;\r
\r
#include "Adc.h"\r
\r
-#define ADC_GROUP0 0\r
-\r
typedef enum\r
{\r
ADC_UNINIT,\r
<PORT-PROTOTYPE-REF DEST="R-PORT-PROTOTYPE">/rte_simple_extract/rte_simple_extract_toplevelcomposition/Arguments</PORT-PROTOTYPE-REF>\r
<DATA-ELEMENT-REF DEST="DATA-ELEMENT-PROTOTYPE">/rte_simple_lib/Interfaces/ArgumentIf/arg1</DATA-ELEMENT-REF>\r
</DATA-ELEMENT-IREF>\r
- <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Arg1</SIGNAL-REF>\r
+ <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_lib/SystemSignals/Arg1</SIGNAL-REF>\r
</SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<DATA-ELEMENT-IREF>\r
<PORT-PROTOTYPE-REF DEST="R-PORT-PROTOTYPE">/rte_simple_extract/rte_simple_extract_toplevelcomposition/Arguments</PORT-PROTOTYPE-REF>\r
<DATA-ELEMENT-REF DEST="DATA-ELEMENT-PROTOTYPE">/rte_simple_lib/Interfaces/ArgumentIf/arg2</DATA-ELEMENT-REF>\r
</DATA-ELEMENT-IREF>\r
- <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Arg2</SIGNAL-REF>\r
+ <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_lib/SystemSignals/Arg2</SIGNAL-REF>\r
</SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<DATA-ELEMENT-IREF>\r
<PORT-PROTOTYPE-REF DEST="P-PORT-PROTOTYPE">/rte_simple_extract/rte_simple_extract_toplevelcomposition/Result</PORT-PROTOTYPE-REF>\r
<DATA-ELEMENT-REF DEST="DATA-ELEMENT-PROTOTYPE">/rte_simple_lib/Interfaces/ResultIf/result</DATA-ELEMENT-REF>\r
</DATA-ELEMENT-IREF>\r
- <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/ResultSig</SIGNAL-REF>\r
+ <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_lib/SystemSignals/ResultSig</SIGNAL-REF>\r
</SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<DATA-ELEMENT-IREF>\r
<PORT-PROTOTYPE-REF DEST="R-PORT-PROTOTYPE">/rte_simple_extract/rte_simple_extract_toplevelcomposition/FreqReq</PORT-PROTOTYPE-REF>\r
<DATA-ELEMENT-REF DEST="DATA-ELEMENT-PROTOTYPE">/rte_simple_lib/Interfaces/FreqReqIf/freq</DATA-ELEMENT-REF>\r
</DATA-ELEMENT-IREF>\r
- <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/FreqReqSig</SIGNAL-REF>\r
+ <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_lib/SystemSignals/FreqReqSig</SIGNAL-REF>\r
</SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
<DATA-ELEMENT-IREF>\r
<PORT-PROTOTYPE-REF DEST="P-PORT-PROTOTYPE">/rte_simple_extract/rte_simple_extract_toplevelcomposition/FreqReqInd</PORT-PROTOTYPE-REF>\r
<DATA-ELEMENT-REF DEST="DATA-ELEMENT-PROTOTYPE">/rte_simple_lib/Interfaces/FreqReqIf/freq</DATA-ELEMENT-REF>\r
</DATA-ELEMENT-IREF>\r
- <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_ti_tms570ls/GeneratedSystemSignals/FreqIndSig</SIGNAL-REF>\r
+ <SIGNAL-REF DEST="SYSTEM-SIGNAL">/rte_simple_lib/SystemSignals/FreqIndSig</SIGNAL-REF>\r
</SENDER-RECEIVER-TO-SIGNAL-MAPPING>\r
</DATA-MAPPINGS>\r
<SW-IMPL-MAPPINGS>\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt8</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</TYPE-TREF>\r
<DIRECTION>IN</DIRECTION>\r
</ARGUMENT-PROTOTYPE>\r
<ARGUMENT-PROTOTYPE UUID="b48f4f2b-f9e6-444c-b978-efe7411ad553">\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt8</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</TYPE-TREF>\r
<DIRECTION>IN</DIRECTION>\r
</ARGUMENT-PROTOTYPE>\r
<ARGUMENT-PROTOTYPE UUID="7021e210-7039-45cf-aa05-4f56012ce341">\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt16</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt16</TYPE-TREF>\r
<DIRECTION>OUT</DIRECTION>\r
</ARGUMENT-PROTOTYPE>\r
</ARGUMENTS>\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt8</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</TYPE-TREF>\r
</DATA-ELEMENT-PROTOTYPE>\r
<DATA-ELEMENT-PROTOTYPE UUID="7433b2c7-347a-4278-ac96-1db4b4451cde">\r
<SHORT-NAME>arg2</SHORT-NAME>\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt8</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</TYPE-TREF>\r
</DATA-ELEMENT-PROTOTYPE>\r
</DATA-ELEMENTS>\r
</SENDER-RECEIVER-INTERFACE>\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt16</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt16</TYPE-TREF>\r
</DATA-ELEMENT-PROTOTYPE>\r
</DATA-ELEMENTS>\r
</SENDER-RECEIVER-INTERFACE>\r
<SDG GID="Arccore::IdentifiableOptions" />\r
</SDGS>\r
</ADMIN-DATA>\r
- <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_ti_tms570ls/GeneratedSystemSignals/Data/UInt32</TYPE-TREF>\r
+ <TYPE-TREF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt32</TYPE-TREF>\r
</DATA-ELEMENT-PROTOTYPE>\r
</DATA-ELEMENTS>\r
</SENDER-RECEIVER-INTERFACE>\r
</SWC-IMPLEMENTATION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
+ <AR-PACKAGE UUID="3e16e6a8-c2ff-4266-8f2c-276afa37dc50">\r
+ <SHORT-NAME>SystemSignals</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <SYSTEM-SIGNAL UUID="5db60ee9-e91b-454b-81bb-24f0c3011885">\r
+ <SHORT-NAME>Arg1</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DATA-TYPE-REF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</DATA-TYPE-REF>\r
+ <LENGTH>8</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ <SYSTEM-SIGNAL UUID="81fc2d93-168d-4a1c-bf18-dcf6557f898a">\r
+ <SHORT-NAME>Arg2</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DATA-TYPE-REF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt8</DATA-TYPE-REF>\r
+ <LENGTH>8</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ <SYSTEM-SIGNAL UUID="d2012f74-c313-446e-8ab4-7abcc9e08d6e">\r
+ <SHORT-NAME>ResultSig</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DATA-TYPE-REF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt16</DATA-TYPE-REF>\r
+ <LENGTH>16</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ <SYSTEM-SIGNAL UUID="55fa62b0-1724-438b-858e-977f952b2c63">\r
+ <SHORT-NAME>FreqIndSig</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DATA-TYPE-REF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt32</DATA-TYPE-REF>\r
+ <LENGTH>32</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ <SYSTEM-SIGNAL UUID="dc34757f-b33e-4d1b-ade6-ef1f797e3af0">\r
+ <SHORT-NAME>FreqReqSig</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::IdentifiableOptions" />\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DATA-TYPE-REF DEST="INTEGER-TYPE">/rte_simple_lib/DatatypeKit/UInt32</DATA-TYPE-REF>\r
+ <LENGTH>32</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
</SUB-PACKAGES>\r
</AR-PACKAGE>\r
</TOP-LEVEL-PACKAGES>\r
#define DEM_E_UNEXPECTED_EXECUTION 0xfe\r
#define DEM_E_NOT_IMPLEMENTED_YET 0xff\r
\r
-#define DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT ULONG_MAX //when timestamp up to the max value,rearrangement starts.\r
\r
// Service ID in this module\r
#define DEM_PREINIT_ID 0x01\r
\r
#endif\r
\r
-\r
+#define DEM_MAX_TIMESTAMP_FOR_REARRANGEMENT ULONG_MAX //when timestamp up to the max value,rearrangement starts.\r
/*\r
* Interface for upper layer modules (8.3.1)\r
*/\r
#define ECUM_AR_MINOR_VERSION 2\r
#define ECUM_AR_PATCH_VERSION 2\r
\r
-#include "EcuM_Types.h"\r
#include "EcuM_Cfg.h"\r
+#include "EcuM_Types.h"\r
#include "EcuM_Cbk.h"\r
\r
#if defined(USE_COM)\r
#include "ComM.h"\r
#endif\r
\r
-\r
/** @name Error Codes */\r
//@{\r
#define ECUM_E_NOT_INITIATED (0x10)\r
#define ECUM_GETAPPMODE_ID (0x11)\r
#define ECUM_SELECT_BOOTARGET_ID (0x12)\r
#define ECUM_GET_BOOTARGET_ID (0x13)\r
+#define ECUM_VALIDATE_WAKEUP_EVENT_ID 0x14\r
#define ECUM_MAINFUNCTION_ID (0x18)\r
#define ECUM_COMM_HASREQUESTEDRUN_ID (0x1b)\r
#define ECUM_ARC_STARTUPTWO_ID (0x20)\r
Std_ReturnType EcuM_GetLastShutdownTarget(EcuM_StateType* shutdownTarget, uint8* sleepMode);\r
\r
EcuM_WakeupSourceType EcuM_GetPendingWakeupEvents(void);\r
-void EcuM_ClearWakeupEvent(EcuM_WakeupSourceType sources);\r
+void EcuM_ClearWakeupEvent(EcuM_WakeupSourceType source );\r
EcuM_WakeupSourceType EcuM_GetValidatedWakeupEvents(void);\r
EcuM_WakeupSourceType EcuM_GetExpiredWakeupEvents(void);\r
EcuM_WakeupStatusType EcuM_GetStatusOfWakeupSource(EcuM_WakeupSourceType sources);\r
\r
void EcuM_MainFunction(void);\r
\r
+\r
#endif /*ECUM_H_*/\r
/** @} */\r
\r
void EcuM_OnRTEStartup(void);\r
\r
-void EcuM_OnEnterRUN(void);\r
+void EcuM_OnEnterRun(void);\r
void EcuM_OnExitRun(void);\r
void EcuM_OnExitPostRun(void);\r
\r
void EcuM_OnGoOffTwo(void);\r
\r
void EcuM_EnableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
-void Ecum_DisableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
+void EcuM_DisableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
\r
void EcuM_GenerateRamHash(void);\r
uint8 EcuM_CheckRamHash(void);\r
\r
void EcuM_AL_SwitchOff(void);\r
-void Ecum_AL_DriverRestart(void);\r
+void EcuM_AL_DriverRestart(void);\r
\r
void EcuM_StartWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
void EcuM_CheckValidation(EcuM_WakeupSourceType wakeupSource);\r
#include "Rte_Type.h"\r
#endif\r
\r
+\r
#if !defined(_DEFINED_TYPEDEF_FOR_EcuM_StateType_)\r
/** Possible states */\r
typedef enum {\r
\r
#endif\r
\r
+\r
#if !defined(_DEFINED_TYPEDEF_FOR_EcuM_UserType_)\r
typedef uint8 EcuM_UserType;\r
\r
#define _DEFINED_TYPEDEF_FOR_EcuM_UserType_\r
#endif\r
\r
+#if 0\r
enum {\r
/** Internal reset of µC (bit 2).\r
* The internal reset typically only resets the µC\r
ECUM_WKSOURCE_RESET = 0x02\r
};\r
\r
+\r
typedef uint32 EcuM_WakeupSourceType;\r
\r
+#endif\r
+\r
typedef enum\r
{\r
ECUM_WKSTATUS_NONE = 0, /**< No pending wakeup event was detected */\r
\r
typedef enum\r
{\r
- ECUM_WWKACT_RUN = 0, /**< Initialization into RUN state */\r
+ ECUM_WKACT_RUN = 0, /**< Initialization into RUN state */\r
ECUM_WKACT_TTII = 2, /**< Execute time triggered increased inoperation protocol and shutdown */\r
ECUM_WKACT_SHUTDOWN = 3 /**< Immediate shutdown */\r
} EcuM_WakeupReactionType;\r
\r
+\r
#if !defined(_DEFINED_TYPEDEF_FOR_EcuM_BootTargetType_)\r
typedef enum\r
{\r
#define _DEFINED_TYPEDEF_FOR_EcuM_BootTargetType_\r
#endif\r
\r
+\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+\r
+#include "Mcu.h"\r
+\r
+#if defined(USE_WDGM)\r
+typedef struct EcuM_WdgM\r
+{\r
+ WdgM_SupervisedEntityIdType EcuMSupervisedEntity;\r
+ WdgM_ModeType EcuMWdgMWakeupMode;\r
+ WdgM_ModeType EcuMWdgMStartupMode;\r
+ WdgM_ModeType EcuMWdgMRunMode;\r
+ WdgM_ModeType EcuMWdgMPostRunMode;\r
+ WdgM_ModeType EcuMWdgMShutdownMode;\r
+} EcuM_WdgMType;\r
+#endif\r
+\r
+typedef struct EcuM_WakeupSourceConfig {\r
+ EcuM_WakeupSourceType EcuMWakeupSourceId;\r
+ uint32 EcuMValidationTimeout;\r
+ Mcu_ResetType EcuMResetReason;\r
+ boolean EcuMWakeupSourcePolling;\r
+ uint8 EcuMComMChannel;\r
+} EcuM_WakeupSourceConfigType;\r
+\r
+typedef struct EcuM_SleepMode\r
+{\r
+ uint8 EcuMSleepModeId;\r
+ EcuM_WakeupSourceType EcuMWakeupSourceMask;\r
+ Mcu_ModeType EcuMSleepModeMcuMode;\r
+#if defined(USE_WDGM)\r
+ WdgM_ModeType EcuMSleepModeWdgMMode;\r
+#endif\r
+ } EcuM_SleepModeType;\r
+\r
+\r
+\r
#endif /* ECUM_TYPES_H_ */\r
/** @} */\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+\r
+/*\r
+ * Include structure:\r
+ *\r
+ *\r
+ * Gpt.h\r
+ * ^\r
+ * |\r
+ * `---------- Gpt_xxx.c ---> Memmap.h\r
+ *\r
+ *\r
+ */\r
+\r
/** @addtogroup Gpt GPT Driver\r
* @{ */\r
\r
#define GPT_H_\r
\r
#include "Std_Types.h"\r
-//#include "EcuM.h" mahi: What for ???\r
+\r
\r
/** @name Error Codes */\r
//@{\r
#define GPT_CBK_CHECKWAKEUP_SERVICE_ID 0x0c\r
//@}\r
\r
-/** Channel id type */\r
-typedef uint8_t Gpt_ChannelType;\r
-\r
/** Channel time value type */\r
typedef uint32_t Gpt_ValueType;\r
\r
GPT_MODE_SLEEP\r
} Gpt_ModeType;\r
\r
+/** Channel id type */\r
+typedef uint8_t Gpt_ChannelType;\r
\r
#define GPT_VENDOR_ID 1\r
#define GPT_MODULE_ID 1\r
#define GPT_AR_MINOR_VERSION 2\r
#define GPT_AR_PATCH_VERSION 1\r
\r
-#include "Gpt_Cfg.h"\r
+//#if (GPT_REPORT_WAKEUP_SOURCE==STD_ON)\r
+#include "EcuM_Cbk.h" /* @req 4.0.3/GPT271 */\r
+//#endif\r
+\r
+/* Needs Gpt_ConfigType */\r
+#include "Gpt_Cfg.h" /* @req 4.0.3/GPT259 */\r
+\r
+/* The config needs EcuM_WakeupSourceType from EcuM */\r
\r
#if (GPT_VERSION_INFO_API == STD_ON)\r
#define Gpt_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,GPT)\r
void (*GptNotification)();\r
uint8 GptNotificationPriority;\r
uint32 GptChannelPrescale;\r
- boolean GptEnableWakeup;\r
+ boolean GptEnableWakeup; // ?\r
+#if (GPT_REPORT_WAKEUP_SOURCE == STD_ON)\r
+ EcuM_WakeupSourceType GptWakeupSource;\r
+#endif\r
} Gpt_ConfigType;\r
\r
#endif /* GPT_CONFIGTYPES_H */\r
} Mcu_PllStatusType;\r
\r
\r
-typedef enum {\r
- MCU_MODE_NORMAL=0\r
-} Mcu_ModeType;\r
-\r
//TODO\r
typedef uint8_t Mcu_RamSectionType;\r
\r
uint32_t McuE_GetPeripheralClock( McuE_PeriperalClock_t type );\r
#endif\r
\r
+void McuE_EnterLowPower( int mode );\r
+void McuE_LowPowerRecoverFlash( void );\r
+\r
#endif /*MCU_H_*/\r
/** @} */\r
\r
#define INVALID_OSAPPLICATION (-1)\r
\r
+#define TASK(_task) void _task( void )\r
+\r
+\r
/* TODO, I have no idea what this should be*/\r
#if (OS_USE_APPLICATIONS == STD_ON)\r
typedef sint32 ApplicationType;\r
#define WDGM_SW_PATCH_VERSION 0
#include "Std_Types.h"
+/* "forward" declare types due to circular dependency chain */
+typedef uint8 WdgM_SupervisedEntityIdType;
+typedef uint8 WdgM_ModeType;
+
+
#include "WdgM_Cfg.h"
// API Service ID's
const float32 WdgM_TriggerCycle;\r
}WdgM_ActivationSchMType;\r
\r
+#if (WDGM_GPT_USED == STD_ON)\r
typedef struct\r
{\r
const uint32 WdgM_GptCycle;\r
const Gpt_ChannelType WdgM_GptChannelRef;\r
}WdgM_ActivationGPTType;\r
+#endif\r
\r
typedef struct\r
{\r
const boolean WdgM_IsGPTActivated;\r
const WdgM_ActivationSchMType WdgM_ActivationSchM;\r
+#if (WDGM_GPT_USED == STD_ON)\r
const WdgM_ActivationGPTType WdgM_ActivationGPT;\r
+#endif\r
}WdgM_ActivationType;\r
\r
typedef struct\r
#define SPR_SPEFSCR 512\r
#define SPR_MCSR 572\r
\r
+#define SPR_MAS0 624\r
+#define SPR_MAS1 625\r
+#define SPR_MAS2 626\r
+#define SPR_MAS3 627\r
+#define SPR_MAS4 628\r
+#define SPR_MAS6 630\r
+\r
+\r
#define ESR_PTR (1<<(38-32))\r
\r
#define SPR_XER 1\r
\r
#define INTC_SSCIR7 0xFFF48027\r
\r
+/* MAS bits */\r
+#define MAS1_TSIZE_4K (1<<8)\r
+#define MAS1_TSIZE_16K (2<<8)\r
+#define MAS1_TSIZE_64K (3<<8)\r
+#define MAS1_TSIZE_256K (4<<8)\r
+#define MAS1_TSIZE_1M (5<<8)\r
+#define MAS1_TSIZE_4M (6<<8)\r
+#define MAS1_TSIZE_16M (7<<8)\r
+#define MAS1_TSIZE_64M (8<<8)\r
+#define MAS1_TSIZE_256M (8<<9)\r
+\r
+#define MAS2_VLE (1<<5)\r
+#define MAS2_W (1<<4)\r
+#define MAS2_I (1<<3)\r
+#define MAS2_M (1<<2)\r
+#define MAS2_G (1<<1)\r
+#define MAS2_E (1<<0)\r
+\r
+#define MAS3_UX (1<<5)\r
+#define MAS3_SX (1<<4)\r
+#define MAS3_UW (1<<3)\r
+#define MAS3_SW (1<<2)\r
+#define MAS3_UR (1<<1)\r
+#define MAS3_SR (1<<0)\r
+\r
+#define MAS3_FULL_ACCESS (MAS3_UX+MAS3_UW+MAS3_UR+MAS3_SX+MAS3_SW+MAS3_SR)\r
+\r
+\r
#if defined(_ASSEMBLER_)\r
/*\r
* PPC vs VLE assembler:\r
#include "mpc563m.h"\r
#elif defined(CFG_MPC5604B)\r
#include "MPC5604B_0M27V_0102.h"\r
+#elif defined(CFG_MPC5606B)\r
+#include "MPC5606B.h"\r
#elif defined(CFG_MPC5606S)\r
#include "mpc5606s.h"\r
#elif defined(CFG_MPC5668)\r
// unsigned long to string\r
void ultoa(unsigned long value, char* str, int base);\r
// int to string\r
-void itoa(int value, char* str, int base);\r
+char * itoa(int value, char* str, int base);\r
\r
\r
#endif /* XTOA_H_ */\r
.PHONY clean: \r
clean: $(dir_cmd_goals)\r
@echo\r
- @echo " >> Cleaning $(CURDIR)"\r
+ @echo " >> Cleaning MAIN $(CURDIR)"\r
# $(Q)find . -type d -name $(objdir) | xargs rm -rf\r
# $(Q)find . -type f -name *.a | xargs rm -rf\r
# $(Q)rm -rf libs/*\r
\r
\r
/*\r
- * Block numbering recalculation macros
+ * Block numbering recalculation macros\r
*/\r
#define GET_DATASET_FROM_BLOCK_NUMBER(_blocknr) ((_blocknr) & ((uint16)((uint16)1u << NVM_DATASET_SELECTION_BITS) - 1u))\r
\r
/*\r
- * Page alignment macros
+ * Page alignment macros\r
*/\r
#define PAGE_ALIGN(_size) ((uint16)((((_size) + FEE_VIRTUAL_PAGE_SIZE - 1) / FEE_VIRTUAL_PAGE_SIZE) * FEE_VIRTUAL_PAGE_SIZE))\r
\r
/*\r
- * Bank properties list
+ * Bank properties list\r
*/\r
#define NUM_OF_BANKS 2\r
typedef struct {\r
\r
\r
/*\r
- * Macros and variables for flash bank administration
+ * Macros and variables for flash bank administration\r
*/\r
#define BANK_STATUS_OLD 0x00\r
#define BANK_STATUS_NEW 0xFF\r
\r
\r
/*\r
- * Macros and variables for flash block administration in flash
+ * Macros and variables for flash block administration in flash\r
*/\r
#define BLOCK_STATUS_INUSE 0x00\r
#define BLOCK_STATUS_INVALIDATED 0x02\r
\r
typedef struct {\r
uint8 BankNumber;\r
+ boolean ForceGarbageCollect;\r
+ uint8 NofFailedGarbageCollect;\r
Fls_AddressType NewBlockAdminAddress;\r
Fls_AddressType NewBlockDataAddress;\r
FlsBankStatusType BankStatus[NUM_OF_BANKS];\r
\r
\r
/*\r
- * Variables for quick reporting of status and job result
+ * Variables for quick reporting of status and job result\r
*/\r
static MemIf_StatusType ModuleStatus = MEMIF_UNINIT;\r
static MemIf_JobResultType JobResult = MEMIF_JOB_OK;\r
\r
/*\r
- * Variables for the current job
+ * Variables for the current job\r
*/\r
typedef enum {\r
FEE_UNINITIALIZED = 0,\r
FEE_GARBAGE_COLLECT_DATA_WRITE,\r
FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED,\r
FEE_GARBAGE_COLLECT_MAGIC_WRITE,\r
- FEE_GARBAGE_COLLECT_ERASE\r
+ FEE_GARBAGE_COLLECT_ERASE,\r
+\r
+ FEE_CORRUPTED\r
+\r
} CurrentJobStateType;\r
\r
typedef struct {\r
CurrentJobStateType State;\r
- uint16 InStateCounter;\r
uint16 BlockNumber;\r
uint16 Length;\r
const Fee_BlockConfigType *BlockConfigPtr;\r
\r
static CurrentJobType CurrentJob = {\r
.State = FEE_IDLE,\r
- .InStateCounter = 0\r
//lint -e{785} PC-Lint (785) - rest of structure members is initialized when used.\r
};\r
\r
/*\r
- * Misc definitions
+ * Misc definitions\r
*/\r
-#define STATE_COUNTER_MAX 0xffff\r
-#define GARBAGE_COLLECTION_DELAY 10\r
-\r
+#define MAX_NOF_FAILED_GC_ATTEMPTS 5\r
/***************************************\r
* Local functions *\r
***************************************/\r
CurrentJob.State = FEE_IDLE;\r
ModuleStatus = MEMIF_IDLE;\r
JobResult = MEMIF_JOB_OK;\r
-\r
- if (Fee_Config.General.NvmJobEndCallbackNotificationCallback != NULL) {\r
- Fee_Config.General.NvmJobEndCallbackNotificationCallback();\r
+ if(!AdminFls.ForceGarbageCollect){\r
+ if (Fee_Config.General.NvmJobEndCallbackNotificationCallback != NULL) {\r
+ Fee_Config.General.NvmJobEndCallbackNotificationCallback();\r
+ }\r
}\r
}\r
\r
\r
static void AbortJob(MemIf_JobResultType result)\r
{\r
- CurrentJob.State = FEE_IDLE;\r
+ if(AdminFls.NofFailedGarbageCollect >= MAX_NOF_FAILED_GC_ATTEMPTS){\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_GLOBAL_ID, FEE_FLASH_CORRUPT);\r
+ AdminFls.ForceGarbageCollect = FALSE;\r
+ CurrentJob.State = FEE_CORRUPTED;\r
+ } else {\r
+ CurrentJob.State = FEE_IDLE;\r
+ }\r
ModuleStatus = MEMIF_IDLE;\r
JobResult = result;\r
\r
\r
\r
/*\r
- * Check job result of bank status 2 read - request for block status reading
+ * Check job result of bank status 2 read - request for block status reading\r
*/\r
static void StartupReadBank2Status(void)\r
{\r
}\r
\r
/*\r
- * Start of block admin read
+ * Start of block admin read\r
*/\r
static void StartupReadBlockAdminRequested(void)\r
{\r
\r
/*\r
* Check job result of block admin read, if all block processed finish\r
- * otherwise request for a new block admin read
+ * otherwise request for a new block admin read\r
*/\r
static void StartupReadBlockAdmin(void)\r
{\r
}\r
\r
/*\r
- * Check job result of block data read
+ * Check job result of block data read\r
*/\r
static void Reading(void)\r
{\r
*/\r
static void BankHeaderOldWrite(uint8 bank)\r
{\r
+ /* Need to collect garbage */\r
+ AdminFls.ForceGarbageCollect = TRUE;\r
/* Mark the bank as old */\r
memset(RWBuffer.BankCtrl.Data, 0xff, BANK_CTRL_PAGE_SIZE);\r
RWBuffer.BankCtrl.BankStatus = BANK_STATUS_OLD;\r
\r
\r
/*\r
- * Start of header write
+ * Start of header write\r
*/\r
static void WriteHeaderRequested()\r
{\r
\r
\r
/*\r
- * Start block data write
+ * Start block data write\r
*/\r
static void WriteDataRequested(void)\r
{\r
\r
\r
/*\r
- * Start magic write
+ * Start magic write\r
*/\r
static void WriteMagicRequested(void)\r
{\r
} else {\r
if (Fls_Erase(BankProp[sourceBank].Start, BankProp[sourceBank].End - BankProp[sourceBank].Start) == E_OK) {\r
SetFlsJobBusy();\r
+ CurrentJob.Op.GarbageCollect.BankNumber = sourceBank;\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_ERASE;\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
- CurrentJob.Op.GarbageCollect.BankNumber = sourceBank;\r
- CurrentJob.State = FEE_GARBAGE_COLLECT_ERASE;\r
}\r
} else {\r
CurrentJob.State = FEE_IDLE;\r
CurrentJob.State = FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED;\r
}\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
if (Fls_Read(CurrentJob.AdminFlsBlockPtr->BlockDataAddress + CurrentJob.Op.GarbageCollect.DataOffset, RWBuffer.Byte, CurrentJob.Length) == E_OK) {\r
SetFlsJobBusy();\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_WRITE_REQUESTED;\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
if (Fls_Write(CurrentJob.Op.GarbageCollect.WriteDataAddress + CurrentJob.Op.GarbageCollect.DataOffset, RWBuffer.Byte, CurrentJob.Length) == E_OK) {\r
SetFlsJobBusy();\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_READ_REQUESTED;\r
}\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
if (Fls_Write(CurrentJob.Op.GarbageCollect.WriteAdminAddress + BLOCK_CTRL_MAGIC_POS_OFFSET, RWBuffer.BlockCtrl.MagicPage.Byte, BLOCK_CTRL_MAGIC_PAGE_SIZE) == E_OK) {\r
SetFlsJobBusy();\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
+ } else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
+ AbortJob(Fls_GetJobResult());\r
}\r
}\r
\r
if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
CurrentJob.AdminFlsBlockPtr->BlockAdminAddress = CurrentJob.Op.GarbageCollect.WriteAdminAddress;\r
CurrentJob.AdminFlsBlockPtr->BlockDataAddress = CurrentJob.Op.GarbageCollect.WriteDataAddress;\r
- FinnishJob();\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_REQUESTED;\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
if (CheckFlsJobFinnished()) {\r
if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
AdminFls.BankStatus[CurrentJob.Op.GarbageCollect.BankNumber] = BANK_STATUS_NEW;\r
+ AdminFls.ForceGarbageCollect = FALSE;\r
+ AdminFls.NofFailedGarbageCollect = 0;\r
FinnishJob();\r
} else {\r
+ AdminFls.NofFailedGarbageCollect++;\r
AbortJob(Fls_GetJobResult());\r
}\r
}\r
}\r
\r
/*\r
- * Start the writing of the "Invalid" header.
+ * Start the writing of the "Invalid" header.\r
*/\r
static void InvalidateWriteInvalidateHeaderRequested(void)\r
{\r
\r
/* State of device */\r
CurrentJob.State = FEE_STARTUP_REQUESTED;\r
- CurrentJob.InStateCounter = 0;\r
#if (FEE_POLLING_MODE == STD_OFF)\r
FlsJobReady = TRUE;\r
#endif\r
\r
AdminFls.BankNumber = 0;\r
+ AdminFls.ForceGarbageCollect = FALSE;\r
+ AdminFls.NofFailedGarbageCollect = 0;\r
AdminFls.NewBlockDataAddress = BankProp[AdminFls.BankNumber].Start;\r
AdminFls.NewBlockAdminAddress = BankProp[AdminFls.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
\r
uint16 dataset;\r
\r
DET_VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_READ_ID, FEE_E_UNINIT, E_NOT_OK);\r
-\r
+ if(AdminFls.ForceGarbageCollect || (FEE_CORRUPTED == CurrentJob.State)){\r
+ return E_NOT_OK;\r
+ }\r
if( !(ModuleStatus == MEMIF_IDLE) ) {\r
DET_REPORTERROR(MODULE_ID_FEE, FEE_READ_ID, FEE_E_BUSY, E_NOT_OK);\r
return E_NOT_OK;\r
uint16 dataset;\r
\r
DET_VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_WRITE_ID, FEE_E_UNINIT, E_NOT_OK);\r
-\r
+ if(AdminFls.ForceGarbageCollect || (FEE_CORRUPTED == CurrentJob.State)){\r
+ return E_NOT_OK;\r
+ }\r
if( !(ModuleStatus == MEMIF_IDLE) ) {\r
DET_REPORTERROR(MODULE_ID_FEE, FEE_READ_ID, FEE_E_BUSY, E_NOT_OK);\r
return E_NOT_OK;\r
*/\r
MemIf_StatusType Fee_GetStatus(void)\r
{\r
- return ModuleStatus;\r
+ if(AdminFls.ForceGarbageCollect && (FEE_IDLE == CurrentJob.State)){\r
+ return MEMIF_BUSY_INTERNAL;\r
+ } else {\r
+ return ModuleStatus;\r
+ }\r
}\r
\r
\r
uint16 dataset;\r
\r
DET_VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_INVALIDATE_BLOCK_ID, FEE_E_UNINIT, E_NOT_OK);\r
+ if(AdminFls.ForceGarbageCollect || (FEE_CORRUPTED == CurrentJob.State)){\r
+ return E_NOT_OK;\r
+ }\r
if( !(ModuleStatus == MEMIF_IDLE) ) {\r
DET_REPORTERROR(MODULE_ID_FEE, FEE_READ_ID, FEE_E_BUSY, E_NOT_OK);\r
return E_NOT_OK;\r
*/\r
void Fee_MainFunction(void)\r
{\r
- static CurrentJobStateType LastState = FEE_UNINITIALIZED;\r
-\r
- if (CurrentJob.State == LastState) {\r
- if (CurrentJob.InStateCounter < STATE_COUNTER_MAX) {\r
- CurrentJob.InStateCounter++;\r
- }\r
- } else {\r
- LastState = CurrentJob.State;\r
- CurrentJob.InStateCounter = 0;\r
- }\r
\r
switch (CurrentJob.State) {\r
case FEE_UNINITIALIZED:\r
break;\r
\r
case FEE_IDLE:\r
- if (CurrentJob.InStateCounter > GARBAGE_COLLECTION_DELAY) {\r
+ if (AdminFls.ForceGarbageCollect) {\r
CheckIfGarbageCollectionNeeded();\r
}\r
break;\r
break;\r
\r
/*\r
- * Write states
+ * Write states\r
*/\r
case FEE_WRITE_REQUESTED:\r
WriteStartJob();\r
break;\r
\r
/*\r
- * Garbage collection states
+ * Garbage collection states\r
*/\r
case FEE_GARBAGE_COLLECT_REQUESTED:\r
GarbageCollectStartJob();\r
break;\r
\r
/*\r
- * Invalidate states
+ * Invalidate states\r
*/\r
case FEE_INVALIDATE_REQUESTED:\r
InvalidateStartJob();\r
InvalidateWriteInvalidateHeader();\r
break;\r
\r
+ /*\r
+ * Corrupted state\r
+ */\r
+ case FEE_CORRUPTED:\r
+ break;\r
\r
/*\r
- * Other
+ * Other\r
*/\r
default:\r
break;\r
--- /dev/null
+\r
+\r
+MKIMAGE?=/c/Users/mahi/git/bootloader/bin/mkimage\r
+SRECORD_PATH?=/c/devtools/srecord\r
+SREC_CAT=$(Q)$(SRECORD_PATH)/srec_cat.exe\r
+SREC_INFO=$(Q)$(SRECORD_PATH)/srec_info.exe\r
+\r
+# "downloader" need an srecord file \r
+build-srec-image-y = $(PROJECTNAME)_srec_image.srec\r
+build-srec-y = $(PROJECTNAME).srec\r
+build-bin-image-y = $(PROJECTNAME)_bin_image.bin\r
+\r
+# To add a header with mkimage we need a binary file\r
+build-bin-y = $(PROJECTNAME).bin\r
+\r
+all-mod += $(build-srec-image-y)\r
+all-mod += $(build-srec-y)\r
+all-mod += $(build-bin-image-y)\r
+\r
+# To srecord again to load in tool\r
+$(build-srec-image-y): $(build-bin-image-y)\r
+ @echo ">> Binary to SREC to load with tool"\r
+ $(SREC_CAT) $< -binary -offset ${BOOT_IMAGE_ADDR} -o $@\r
+ $(SREC_INFO) $@\r
+\r
+$(build-srec-y) : $(build-exe-y)\r
+ @echo\r
+ @echo " >> OBJCOPY $@" \r
+ $(Q)$(CROSS_COMPILE)objcopy -O srec $< $@\r
+ $(SREC_INFO) $@\r
+\r
+# Binary image down to 0\r
+$(build-bin-y) : $(build-srec-y)\r
+ @echo ">> srec to binary with offset 0"\r
+ $(SREC_INFO) $< \r
+ $(SREC_CAT) $< -offset - -minimum-addr $< -o $@ -binary\r
+\r
+# Add image header \r
+# Should extract the start address with "objdump -f"\r
+$(build-bin-image-y): $(build-bin-y)\r
+ @echo ">> Adding header" \r
+ $(MKIMAGE) -o $@ -l $(BOOT_BLOB_LOAD_ADDR) -s $(BOOT_BLOB_START_ADDR) -m "APP" -v $<\r
$(Q)$(MAKE) -C $(ROOTDIR) BOARDDIR=$(boarddir) BDIR=$(CURDIR) all\r
\r
clean: \r
- @echo Cleaning dir $(boarddir) \r
- $(Q)rm -rf obj_$(boarddir)\r
+ @echo Removing dir $(boarddir) \r
+ rm -rfv obj_$(boarddir)\r
+ rm -rfv $(ROOTDIR)/binaries/$(boarddir)/$(PROJECTNAME)*\r
@echo done!\r
\r
endif\r
include $(ROOTDIR)/boards/board_common.mk\r
endif\r
\r
+# Misc tools\r
+ifneq ($(CFG_BOOT),)\r
+include $(ROOTDIR)/boards/$(BOARDDIR)/boot_info.mk\r
+include $(ROOTDIR)/scripts/bootloader_image.mk\r
+endif \r
\r
##### For backwards compatability with older project makefiles:\r
\r
.PHONY clean: \r
clean: FORCE\r
@echo\r
- @echo " >> Cleaning $(CURDIR)"\r
- $(Q)-rm -f *.o *.d *.h *.elf *.a *.ldp *.lcf *.tmp *.s *.c *.map *.out *.bin *.srec\r
- @echo\r
+ @echo " >> Rules Clean $(CURDIR)"\r
+ $(Q)-rm -v *\r
+ $(Q)-rm -v $(ROOTDIR)/binaries/$(BOARDDIR)/*\r
\r
.PHONY : config \r
config: FORCE\r
$(Q)$(CROSS_COMPILE)objcopy -O ihex $< $@\r
\r
# bin output\r
-$(build-bin-y): $(build-exe-y)\r
- @echo\r
- @echo " >> OBJCOPY $@" \r
- $(Q)$(CROSS_COMPILE)objcopy -O binary $< $@ \r
+#$(build-bin-y): $(build-exe-y)\r
+# @echo\r
+# @echo " >> OBJCOPY $@" \r
+# $(Q)$(CROSS_COMPILE)objcopy -O binary $< $@ \r
\r
# Linker\r
$(build-exe-y): $(dep-y) $(obj-y) $(sim-y) $(libitem-y) $(ldcmdfile-y)\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+\r
+/** @reqSettings DEFAULT_SPECIFICATION_REVISION=3.1.5 */\r
+\r
+/* ----------------------------[information]----------------------------------*/\r
+/*\r
+ * Author: ?+mahi\r
+ *\r
+ * Part of Release:\r
+ * 3.1.5\r
+ *\r
+ * Description:\r
+ * Implements the Can Driver module\r
+ *\r
+ * Support:\r
+ * General Have Support\r
+ * -------------------------------------------\r
+ * ECUM_TTII_ENABLED N\r
+ * ECUM_DEV_ERROR_DETECT Y\r
+ * ECUM_VERSION_INFO_API Y\r
+ * ECUM_INCLUDE_DEM N (controlled by USE_x macro's instead)\r
+ * ECUM_INCLUDE_NVRAM_MGR N (controlled by USE_x macro's instead)\r
+ * ECUM_INLCUDE_DET N (controlled by USE_x macro's instead)\r
+ * ECUM_MAIN_FUNCTION_PERDIOD Y\r
+ * ECUM_TTII_WKSOURCE N\r
+ *\r
+ * Configuration Have Support\r
+ * -------------------------------------------\r
+ * ECUM_SLEEP_ACTIVITY_PERIOD ?\r
+ * ECUM_CONFIGCONSISTENCY_HASH N\r
+ * ECUM_RUN_SELF_REQUEST_PERIOD ?\r
+ * ECUM_NVRAM_WRITEALL_TIMEOUT Y\r
+ * ECUM_DEFAULT_APP_MODE ?\r
+ *\r
+ *\r
+ * DefaultShutdownTarget\r
+ * -------------------------------------------\r
+ * ECUM_DEFAULT_SHUTDOWN_TARGET N\r
+ *\r
+ *\r
+ * Things to start with:\r
+ * - EcuM2181\r
+ * - EcuM2861 , Watchdog\r
+ * - ComM_EcuM_RunModeIndication() not called, See Figure 8 (Seems that the ComM does not do much either)\r
+ *\r
+ *\r
+ *\r
+ */\r
+\r
//lint -emacro(904,VALIDATE,VALIDATE_RV,VALIDATE_NO_RV) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
\r
+\r
+/* ----------------------------[includes]------------------------------------*/\r
+\r
#include "Std_Types.h"\r
#include "EcuM.h"\r
#include "Modules.h"\r
#endif\r
\r
\r
+/* ----------------------------[private define]------------------------------*/\r
+/* ----------------------------[private macro]-------------------------------*/\r
+/* ----------------------------[private typedef]-----------------------------*/\r
+/* ----------------------------[private function prototypes]-----------------*/\r
+/* ----------------------------[private variables]---------------------------*/\r
\r
EcuM_GlobalType internal_data;\r
\r
+/* ----------------------------[private functions]---------------------------*/\r
+\r
+\r
+/* ----------------------------[public functions]----------------------------*/\r
+\r
#if !defined(USE_DET) && defined(ECUM_DEV_ERROR_DETECT)\r
#error EcuM configuration error. DET is not enabled when ECUM_DEV_ERROR_DETECT is set\r
#endif\r
// Determine PostBuild configuration\r
internal_data.config = EcuM_DeterminePbConfiguration();\r
\r
+\r
// TODO: Check consistency of PB configuration\r
\r
// Initialize drivers needed before the OS-starts\r
SchM_Init();\r
#endif\r
\r
+#if defined(USE_WDGM)\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMStartupMode);\r
+#endif\r
+\r
// Initialize drivers that don't need NVRAM data\r
EcuM_AL_DriverInitTwo(internal_data.config);\r
\r
return E_OK;\r
}\r
\r
+/**\r
+ *\r
+ */\r
void EcuM_KillAllRUNRequests( void ) {\r
/* NOT IMPLEMENTED */\r
}\r
\r
+\r
+/**\r
+ *\r
+ * @param sources\r
+ */\r
void EcuM_SetWakeupEvent(EcuM_WakeupSourceType sources) {\r
- /* NOT IMPLEMENTED */\r
+ /* @req 3.1.5/EcuM2826 The function exists */\r
+ /* @req 3.1.5/EcuM2171 */\r
+\r
+ /* @req 3.1.5/EcuM2867 */\r
+#if ( ECUM_DEV_ERROR_DETECT == STD_ON )\r
+ {\r
+ EcuM_WakeupSourceType wkSource;\r
+ const EcuM_SleepModeType *sleepModePtr;\r
+\r
+ sleepModePtr = &internal_data.config->EcuMSleepModeConfig[internal_data.sleep_mode];\r
+ wkSource = sleepModePtr->EcuMWakeupSourceMask;\r
+\r
+ if( !((sources | wkSource) == wkSource)) {\r
+ Det_ReportError(MODULE_ID_ECUM, 0, ECUM_VALIDATE_WAKEUP_EVENT_ID, ECUM_E_UNKNOWN_WAKEUP_SOURCE );\r
+ return;\r
+ }\r
+ }\r
+#endif\r
+\r
+\r
+ /* @req 3.1.5/EcuM1117 */\r
+ internal_data.wakeupEvents |= sources;\r
+\r
+ /* @req 3.1.5/EcuM2707 @req 3.1.5/EcuM2709*/\r
+// internal_data.wakeupTimer = ECUM_VALIDATION_TIMEOUT;\r
+\r
}\r
\r
#if defined(USE_COMM) || defined(USE_ECUM_COMM)\r
return E_OK;\r
}\r
\r
+/*\r
+ * TODO: Don't yet understand the use\r
+ */\r
+void EcuM_ClearWakeupEvent( EcuM_WakeupSourceType source )\r
+{\r
+ switch(source) {\r
+ case ECUM_WKSTATUS_NONE:\r
+ /* Seems quite pointless */\r
+ break;\r
+ case ECUM_WKSTATUS_PENDING:\r
+ break;\r
+ case ECUM_WKSTATUS_VALIDATED:\r
+ break;\r
+ case ECUM_WKSTATUS_EXPIRED:\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * Get the pending wakeup events.\r
+ *\r
+ * @return\r
+ */\r
+EcuM_WakeupSourceType EcuM_GetPendingWakeupEvents( void ) {\r
+ /* @req 3.1.5/EcuM2827 API\r
+ * @req 3.1.5/EcuM2172 Callable from interrupt context\r
+ * */\r
+\r
+ /* @req 3.1.5/EcuM1156 */\r
+ return internal_data.wakeupEvents;\r
+\r
+}\r
+\r
+\r
+void EcuM_CheckValidation(EcuM_WakeupSourceType wakeupSource) {\r
+ /* Used only if CanIf is used ? CanIf_Checkvalidation(wakeupSource) */\r
+ (void)wakeupSource;\r
+}\r
+\r
+\r
+EcuM_WakeupSourceType EcuM_GetValidatedWakeupEvents( void ) {\r
+ // TODO:\r
+ return 0;\r
+}\r
+\r
+EcuM_WakeupStatusType EcuM_GetStatusOfWakeupSource( EcuM_WakeupSourceType sources ) {\r
+ return 0;\r
+}\r
+\r
+\r
#endif\r
uint32 run_requests;\r
uint32 postrun_requests;\r
+ EcuM_WakeupSourceType wakeupEvents;\r
+ uint32 wakeupTimer;\r
} EcuM_GlobalType;\r
\r
extern EcuM_GlobalType internal_data;\r
static NvM_RequestResultType writeAllResult;\r
#endif\r
\r
+static uint32 internal_data_go_sleep_state_timeout = 0;\r
+\r
#ifdef CFG_ECUM_USE_SERVICE_COMPONENT\r
/** @req EcuM2749 */\r
static Rte_ModeType_EcuM_Mode currentMode;\r
#endif\r
\r
\r
+/**\r
+ * RUN II entry\r
+ * - Called from EcuM_StartupTwo()\r
+ * - Called from\r
+ *\r
+ *\r
+ */\r
void EcuM_enter_run_mode(void){\r
set_current_state(ECUM_STATE_APP_RUN);\r
- EcuM_OnEnterRUN(); /** @req EcuM2308 */\r
- //TODO: Call ComM_EcuM_RunModeIndication(NetworkHandleType Channel) for all channels that have requested run.\r
+ EcuM_OnEnterRun(); /** @req EcuM2308 */\r
+\r
+#if defined(USE_WDGM)\r
+ /* This seems strange, should be in FW instead */\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMRunMode);\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ /*\r
+ * Loop over all channels that have requested run,\r
+ * ie EcuM_ComM_RequestRUN()\r
+ */\r
+ {\r
+ uint32 cMask = internal_data.run_comm_requests;\r
+ uint8 channel;\r
+\r
+ for (; cMask; cMask &= ~(1ul << channel)) {\r
+ channel = ilog2(cMask);\r
+ ComM_EcuM_RunModeIndication(channel);\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* We have a configurable minimum time (EcuMRunMinimumDuration)\r
+ * we have to stay in RUN state */\r
internal_data_run_state_timeout = internal_data.config->EcuMRunMinimumDuration / ECUM_MAIN_FUNCTION_PERIOD; /** @req EcuM2310 */\r
}\r
\r
\r
//--------- Local functions ------------------------------------------------------------------------------------------------\r
\r
+\r
+\r
+/**\r
+ * Enter GO SLEEP state ( soon in state ECUM_STATE_GO_SLEEP)\r
+ */\r
static inline void enter_go_sleep_mode(void){\r
+ EcuM_WakeupSourceType wakeupSource;\r
set_current_state(ECUM_STATE_GO_SLEEP);\r
+\r
EcuM_OnGoSleep();\r
+\r
+#if defined(USE_NVM)\r
+ NvM_WriteAll();\r
+\r
+ /* Start timer */\r
+ internal_data_go_sleep_state_timeout = internal_data.config->EcuMNvramWriteAllTimeout / ECUM_MAIN_FUNCTION_PERIOD;\r
+\r
+ wakeupSource = EcuM_GetPendingWakeupEvents();\r
+#else\r
+ wakeupSource = EcuM_GetPendingWakeupEvents();\r
+#endif\r
+}\r
+\r
+/**\r
+ In GO SLEEP state (in state ECUM_STATE_GO_SLEEP)\r
+ */\r
+static void in_state_goSleep( void ) {\r
+\r
+ /* We only wait for NvM_WriteAll() for so long */\r
+ if (internal_data_go_sleep_state_timeout){\r
+ internal_data_go_sleep_state_timeout--;\r
+ }\r
+\r
+ if( (internal_data_go_sleep_state_timeout == 0) ) {\r
+ /*\r
+ * We should go to sleep , enable source that should wake us\r
+ * */\r
+ uint32 cMask;\r
+ uint8 source;\r
+ const EcuM_SleepModeType *sleepModePtr;\r
+\r
+ /* Get the current sleep mode */\r
+\r
+ sleepModePtr = &internal_data.config->EcuMSleepModeConfig[internal_data.sleep_mode];\r
+\r
+ cMask = sleepModePtr->EcuMWakeupSourceMask;\r
+\r
+ /* Loop over the WKSOURCE for this sleep mode */\r
+ for (; cMask; cMask &= ~(1ul << source)) {\r
+ source = ilog2(cMask);\r
+ /* @req 3.1.5/ECUM2389 */\r
+ EcuM_EnableWakeupSources( 1<< source );\r
+\r
+#if defined(WDGM)\r
+ WdgM_SetMode(sleepModePtr->EcuMSleepModeWdgMMode);\r
+#endif\r
+\r
+ /* Let no one else run */\r
+ GetResource(RES_SCHEDULER);\r
+ }\r
+\r
+ } else if( EcuM_GetPendingWakeupEvents() != 0 ) {\r
+ /* We have pending wakeup events, need to startup again */\r
+#if defined(USE_NVM)\r
+ NvM_CancelWriteAll();\r
+#endif\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * In "Sleep Sequence I" (in state ECUM_STATE_SLEEP)\r
+ */\r
+static void in_state_sleep ( void ) {\r
+ const EcuM_SleepModeType *sleepModePtr;\r
+ sleepModePtr = &internal_data.config->EcuMSleepModeConfig[internal_data.sleep_mode];\r
+\r
+ EcuM_GenerateRamHash();\r
+\r
+ Mcu_SetMode(sleepModePtr->EcuMSleepModeMcuMode);\r
+\r
+ /* @req 3.1.5/ECUM2863 */\r
+ if( EcuM_CheckRamHash() == 0) {\r
+#if defined(USE_DEM)\r
+ //\r
+ EcuM_ErrorHook(ECUM_E_RAM_CHECK_FAILED);\r
+#endif\r
+ }\r
+\r
+ set_current_state(ECUM_STATE_WAKEUP_ONE);\r
}\r
\r
static inline void enter_go_off_one_mode(void){\r
}\r
\r
\r
-\r
+/**\r
+ * RUN II Loop (in state ECUM_STATE_APP_RUN)\r
+ * - The entry to RUN II is done in\r
+ */\r
static inline void in_state_appRun(void){\r
if (internal_data_run_state_timeout){\r
internal_data_run_state_timeout--;\r
\r
if ((!hasRunRequests()) && (internal_data_run_state_timeout == 0)){\r
EcuM_OnExitRun(); /** @req EcuM2865 */\r
+\r
+#if defined(USE_WDGM)\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMPostRunMode);\r
+#endif\r
+\r
+#if defined(USE_RTE) && defined(CFG_ECUM_USE_SERVICE_COMPONENT)\r
+ Rte_Switch_currentMode_currentMode(RTE_MODE_EcuM_Mode_POSTRUN);\r
+#endif\r
+\r
set_current_state(ECUM_STATE_APP_POST_RUN);/** @req EcuM2865 */\r
}\r
}\r
\r
\r
+/**\r
+ * RUN III states (in state ECUM_STATE_APP_POST_RUN)\r
+ */\r
static inline void in_state_appPostRun(void){\r
+\r
+ /* @req 3.1.5/ECUM2866 */\r
if (hasRunRequests()){\r
- set_current_state(ECUM_STATE_APP_RUN);/** @req EcuM2866 */ /** @req EcuM2308 */\r
- EcuM_OnEnterRUN(); /** @req EcuM2308 */\r
- //TODO: Call ComM_EcuM_RunModeIndication(NetworkHandleType Channel) for all channels that have requested run.\r
- internal_data_run_state_timeout = internal_data.config->EcuMRunMinimumDuration / ECUM_MAIN_FUNCTION_PERIOD; /** @req EcuM2310 */\r
+ /* We have run requests, return to RUN II */\r
+ EcuM_enter_run_mode();\r
\r
} else if (!hasPostRunRequests()){\r
EcuM_OnExitPostRun(); /** @req EcuM2761 */\r
set_current_state(ECUM_STATE_PREP_SHUTDOWN);/** @req EcuM2761 */\r
-\r
- EcuM_OnPrepShutdown();\r
} else {\r
- // TODO: Do something?\r
+ /* TODO: We have postrun requests */\r
}\r
}\r
\r
+\r
+/**\r
+ * PREP SHUTDOWN state (in state ECUM_STATE_PREP_SHUTDOWN)\r
+ */\r
static inline void in_state_prepShutdown(void){\r
+\r
+ // TODO: The specification does not state what events to clear\r
+ EcuM_ClearWakeupEvent(ECUM_WKSTATUS_NONE);\r
+\r
+ EcuM_OnPrepShutdown();\r
+\r
#if defined(USE_DEM)\r
// DEM shutdown\r
Dem_Shutdown();\r
// Wait for the NVM job (NvmWriteAll) to terminate\r
NvM_GetErrorStatus(0, &writeAllResult);\r
if ((writeAllResult != NVM_REQ_PENDING) || (internal_data_go_off_one_state_timeout == 0)){\r
+\r
+#if defined(USE_WDGM)\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMShutdownMode);\r
+#endif\r
ShutdownOS(E_OK);\r
}\r
#else\r
+\r
+#if defined(USE_WDGM)\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMShutdownMode);\r
+#endif\r
ShutdownOS(E_OK);\r
#endif\r
}\r
\r
//----- MAIN -----------------------------------------------------------------------------------------------------------------\r
void EcuM_MainFunction(void){\r
+ EcuM_WakeupSourceType wMask;\r
+\r
VALIDATE_NO_RV(internal_data.initiated, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
\r
switch(internal_data.current_state){\r
\r
case ECUM_STATE_APP_RUN:\r
+ /* RUN II state */\r
in_state_appRun();\r
break;\r
case ECUM_STATE_APP_POST_RUN:\r
+ /* RUN III state */\r
in_state_appPostRun();\r
break;\r
case ECUM_STATE_PREP_SHUTDOWN:\r
in_state_goOffOne();\r
break;\r
case ECUM_STATE_GO_SLEEP:\r
- // TODO: Fill out\r
+ in_state_goSleep();\r
+ break;\r
+ case ECUM_STATE_SLEEP:\r
+ in_state_sleep();\r
break;\r
+ case ECUM_STATE_WAKEUP_ONE:\r
+ {\r
+ /* TODO: we must have a normal RUN mode.. can't find any\r
+ * in the A3.1.5 spec. */\r
+ Mcu_SetMode(MCU_MODE_NORMAL);\r
+\r
+#if defined(USE_WDGM)\r
+ WdgM_SetMode(internal_data.config->EcuMWdgMConfig->EcuMWdgMWakeupMode);\r
+#endif\r
+\r
+ wMask = EcuM_GetPendingWakeupEvents();\r
+\r
+ EcuM_DisableWakeupSources(wMask);\r
+\r
+ EcuM_AL_DriverRestart();\r
+\r
+ ReleaseResource(RES_SCHEDULER);\r
+\r
+ set_current_state(ECUM_STATE_WAKEUP_VALIDATION);\r
+\r
+ break;\r
+ }\r
+\r
+ case ECUM_STATE_WAKEUP_VALIDATION:\r
+ {\r
+ wMask = EcuM_GetPendingWakeupEvents();\r
+\r
+ EcuM_StartWakeupSources(wMask);\r
+\r
+ EcuM_CheckValidation( wMask );\r
+\r
+ // TODO:\r
+ // ComM_EcuM_WakeupIndication( network handle )\r
+\r
+ set_current_state(ECUM_STATE_WAKEUP_REACTION);\r
+ break;\r
+ }\r
+\r
+ case ECUM_STATE_WAKEUP_REACTION:\r
+ {\r
+ /*\r
+ * At this stage we want to know how to react to the wakeup, e.g. go\r
+ * back to RUN or SHUTDOWN, etc.\r
+ */\r
+ EcuM_WakeupReactionType wReaction;\r
+\r
+ wMask = EcuM_GetValidatedWakeupEvents();\r
+\r
+ /* TODO: We have skipped the TTII timer here */\r
+\r
+ /* If the wakeup mask here is != 0 we have a validated wakeup event ->\r
+ * go back to RUN */\r
+ wReaction = ( 0 == wMask ) ? ECUM_WKACT_SHUTDOWN : ECUM_WKACT_RUN;\r
+ wReaction = EcuM_OnWakeupReaction(wReaction);\r
+\r
+ if( wReaction == ECUM_WKACT_RUN) {\r
+ set_current_state(ECUM_STATE_WAKEUP_TWO);\r
+ } else {\r
+ /* From figure 28 it seems that we should go to SHUTDOWN/GO SLEEP) again from wakeup\r
+ * not going up to RUN/RUN II state again. */\r
+ set_current_state(ECUM_STATE_GO_SLEEP);\r
+ }\r
+ break;\r
+ }\r
+\r
+ case ECUM_STATE_WAKEUP_TWO:\r
+#if defined(USE_DEM)\r
+ Dem_Init();\r
+#endif\r
+ set_current_state(ECUM_STATE_RUN);\r
+ break;\r
+\r
default:\r
//TODO: Report error.\r
break;\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+/* ----------------------------[information]----------------------------------*/\r
+/*\r
+ * Author: mahi\r
+ *\r
+ * Part of Release:\r
+ * 3.1.5\r
+ *\r
+ * Description:\r
+ * Implements the SchM module\r
+ *\r
+ * Support:\r
+ * General Have Support\r
+ * -------------------------------------------\r
+ * SCHM_DEV_ERROR_DETECT N\r
+ * SCHM_VERSION_INFO_API N\r
+ *\r
+ * General Have Support\r
+ * -------------------------------------------\r
+ * SCHM_POSITION_IN_TASK N\r
+ * SCHM_MAINFUNCTION_REF N\r
+ * SCHM_MAPPED_TO_TASK N\r
+ * .....\r
+ *\r
+ * Implementation Notes:\r
+ * There are a lot of examples in SchM about scheduling and it\r
+ * all seems very complicated. What is boils down to is that\r
+ * the BSW MainFunctions have different requirements. Most modules\r
+ * have only periodic needs for timeouts and other things. But there\r
+ * are also module that needs extra iterations at certain points in time, to\r
+ * be really efficient.\r
+ *\r
+ *\r
+ * BSW Module Code:\r
+ * SchM_Enter_NvM(EXCLUSIVE_AREA_0);\r
+ * ..Do stuff...\r
+ * SchM_Enter_NvM(EXCLUSIVE_AREA_0);\r
+ *\r
+ * but today we have Irq_Save(state), Irq_Restore(state).\r
+ * ArcCore Irq_Save/Irq_Restore is almost the same as SuspendAllInterrupts/ResumeAllInterrupts,\r
+ * since they can both be nested and saves state. But the OSEK (Susp../Resume..) can't do it locally, it\r
+ * assumes some kind of local FIFO, that is bad.\r
+ *\r
+ *\r
+ * BSW Modules with generated mainfunction period times. Checked Only 3.1.5\r
+ *\r
+ * Specification Studio Core=Generator\r
+ * --------------------------------------------------------------------------------------\r
+ * Adc N/A *1\r
+ * Can CanMainFunctionReadPerdiod No No\r
+ * CanMainFunctionWritePerdiod\r
+ * ..\r
+ * CanIf Have No mainf N/A\r
+ * CanNm CanNmMainFunctionPeriod Yes Accessible in struct.. not as define\r
+ * CanSm Have mainf. but no period Yes*2 Nothing is generated\r
+ * CanTp CanTpMainFunctionPeriod Yes CANTP_MAIN_FUNCTION_PERIOD_TIME_MS\r
+ * CanTrcv Have mainf. but no period N/A\r
+ * Com Have mainf. but no period No*3\r
+ * ComM ComMMainFunctionPeriod Yes Accessible in struct.. not as define\r
+ * Dcm Have MainF. DcmTaskTime Yes DCM_MAIN_FUNCTION_PERIOD_TIME_MS\r
+ * Dem Have MainF. DemTaskTime No\r
+ * EcuM Have MainF.EcuMMainFunctionPeriod Yes ECUM_MAIN_FUNCTION_PERIOD\r
+ * Ea Have MainF. ON_PRE_CONDITION (ie not cyclic)\r
+ * Eep Have MainF. VARIABLE_CYCLIC\r
+ * Fee Have MainF. ON_PRE_CONDITION\r
+ * Fls Have MainF. FIXED_CYCLIC\r
+ * IoHwAb Have no mainfunction\r
+ * ..\r
+ * Nm Have MainF. FIXED_CYCLIC , No\r
+ * NmCycletimeMainFunction\r
+ * NvM Have MainF. VARIABLE_CYCLIC No\r
+ * PduR Have no MainF.\r
+ * Spi Have MainF. FIXED_CYCLIC, no period\r
+ * WdgM Have MainF. WdgMTriggerCycle *4\r
+ *\r
+ * *1 No MainFunction\r
+ * *2 What is it used for?\r
+ * *3 Com have lots of timing... it's related to what? (reads timer?)\r
+ * *4 Probably not.\r
+ *\r
+ * ----->>>>\r
+ *\r
+ * Conclusion:\r
+ * * Support in generator is extremely limited.\r
+ * * Support in specification is limited\r
+ * * Support in studio is limited\r
+ *\r
+ * Write scheduling information directly in the SchM_<mod>.h files.\r
+ * OR\r
+ * Write scheduling information in SchM_cfg.h....better (keeps information in one place)\r
+ *\r
+ * #if defined(USE_SCHM)\r
+ * assert( SCHM_TIMER(x) == <period> )\r
+ * #endif\r
+ *\r
+ * It seems it's mandatory to include SchM_<mod>.h for each BSW module.\r
+ * So,\r
+ * - <mod>.c ALWAYS include SchM_<mod.h>\r
+ * - SchM.c have condidional include on SchM_<mod>.h, e.g must define it's MainFunctions.\r
+ *\r
+ *\r
+ *\r
+ */\r
\r
+#include "SchM.h"\r
+#include "SchM_cfg.h"\r
\r
\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#include "SchM_Can.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_CAN_WRITE()\r
+#define SCHM_MAINFUNCTION_CAN_READ()\r
+#define SCHM_MAINFUNCTION_CAN_BUSOFF()\r
+#define SCHM_MAINFUNCTION_CAN_ERROR()\r
+#define SCHM_MAINFUNCTION_CAN_WAKEUP()\r
+#endif\r
\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#include "SchM_CanIf.h"\r
+#endif\r
\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#include "SchM_PduR.h"\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#include "SchM_Com.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_COMRX()\r
+#define SCHM_MAINFUNCTION_COMTX()\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#include "SchM_CanTp.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_CANTP()\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#include "SchM_J1939TP.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_J1939TP()\r
+#endif\r
+\r
+\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#include "SchM_Dcm.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_DCM()\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#include "SchM_Dem.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_DEM()\r
+#endif\r
+\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#include "SchM_Pwm.h"\r
+#endif\r
+\r
+\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#include "SchM_IoHwAb.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_IOWHAB()\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#include "SchM_Fls.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_FLS()\r
+#endif\r
+\r
+#if defined(USE_ECUM)\r
+#include "EcuM.h"\r
+#include "SchM_EcuM.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_ECUM()\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#include "SchM_Fls.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_EEP()\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#include "SchM_Fee.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_FEE()\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#include "SchM_Ea.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_EA()\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#include "SchM_NvM.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_NVM()\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#include "SchM_ComM.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_COMM()\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#include "SchM_Nm.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_NM()\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#include "SchM_CanNm.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_CANNM()\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#include "SchM_CanSM.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_CANSM()\r
+#endif\r
+\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#include "SchM_Spi.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_SPI()\r
+#endif\r
+\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#include "SchM_WdgM.h"\r
+#else\r
+#define SCHM_MAINFUNCTION_WDMG()\r
+#endif\r
+\r
+SCHM_DECLARE(CAN_WRITE);\r
+SCHM_DECLARE(CAN_READ);\r
+SCHM_DECLARE(CAN_BUSOFF);\r
+SCHM_DECLARE(CAN_WAKEUP);\r
+SCHM_DECLARE(CAN_ERROR);\r
+SCHM_DECLARE(COMRX);\r
+SCHM_DECLARE(COMTX);\r
+SCHM_DECLARE(CANTP);\r
+SCHM_DECLARE(CANNM);\r
+SCHM_DECLARE(DCM);\r
+SCHM_DECLARE(DEM);\r
+SCHM_DECLARE(COMM);\r
+SCHM_DECLARE(NM);\r
+SCHM_DECLARE(CANSM);\r
+SCHM_DECLARE(ECUM);\r
+SCHM_DECLARE(NVM);\r
+SCHM_DECLARE(FEE);\r
+SCHM_DECLARE(EA);\r
+SCHM_DECLARE(FLS);\r
+SCHM_DECLARE(WDGM_TRIGGER);\r
+SCHM_DECLARE(WDGM_ALIVESUPERVISION);\r
\r
-#include "SchM.h"\r
\r
\r
void SchM_Init( void ) {\r
- \r
+\r
}\r
+\r
void SchM_Deinit( void ) {\r
- \r
+\r
}\r
\r
void SchM_GetVersionInfo( Std_VersionInfoType *versionInfo ) {\r
- \r
+\r
+}\r
+\r
+\r
+static void runMemory( void ) {\r
+ SCHM_MAINFUNCTION_NVM();\r
+ SCHM_MAINFUNCTION_EA();\r
+ SCHM_MAINFUNCTION_FEE();\r
+ SCHM_MAINFUNCTION_EEP();\r
+ SCHM_MAINFUNCTION_FLS();\r
+ SCHM_MAINFUNCTION_SPI();\r
}\r
\r
-/* \r
- * Implement\r
+/**\r
+ * Startup task.\r
*/\r
-// Critical sections\r
-// void SchM_Enter_<ModulePrefix>( uint8 instance, uint8 exclusiveArea )\r
-// void SchM_Exit_<ModulePrefix>( uint8 instance, uint8 exclusiveArea )\r
-\r
-// Triggers\r
-// SchM_ReturnType SchM_ActMainFunction_<ModulePrefix>( uint8 instance, uint8 activationPoint );\r
-// SchM_ReturnType SchM_CancelMainFunction_<ModulePrefix>( uint8 instance, uint8 activationPoint );\r
-\r
-/* \r
- * Callable functions in the <ModulePrefix>\r
- */ \r
-// <ModulePrefix>_MainFunction_<name>()\r
-// <ModulePrefix>_MainFunction_<name>()\r
+TASK(SchM_Startup){\r
+\r
+ /* At this point EcuM == ECUM_STATE_STARTUP_ONE */\r
+\r
+ /* Set events on TASK_ID_BswService_Mem */\r
+ SetRelAlarm(ALARM_ID_Alarm_BswService, 10, 2);\r
+\r
+ /*\r
+ * Call EcuM_StartupTwo that do:\r
+ * - Startup RTE,\r
+ * - Wait for Nvm to complete\r
+ * - Call EcuM_AL_DriverInitThree() to initiate Nvm dependent modules.\r
+ */\r
+ EcuM_StartupTwo();\r
+\r
+ /* Start to schedule BSW parts */\r
+ CancelAlarm(ALARM_ID_Alarm_BswService);\r
+ SetRelAlarm(ALARM_ID_Alarm_BswService, 10, 5);\r
+\r
+ EcuM_RequestRUN(ECUM_USER_User_1);\r
+\r
+ ActivateTask(TASK_ID_Application);\r
+\r
+ TerminateTask();\r
+\r
+}\r
+\r
+\r
+TASK(SchM_BswService) {\r
+ EcuM_StateType state;\r
+\r
+ EcuM_GetState(&state);\r
+\r
+ switch( state ) {\r
+ case ECUM_STATE_STARTUP_ONE:\r
+ /* Nothing to schedule */\r
+ break;\r
+ case ECUM_STATE_STARTUP_TWO:\r
+ runMemory();\r
+ break;\r
+ default:\r
+ runMemory();\r
+\r
+ SCHM_MAINFUNCTION_ECUM();\r
+\r
+ SCHM_MAINFUNCTION_CAN_WRITE();\r
+ SCHM_MAINFUNCTION_CAN_READ();\r
+ SCHM_MAINFUNCTION_CAN_BUSOFF();\r
+ SCHM_MAINFUNCTION_CAN_ERROR();\r
+ SCHM_MAINFUNCTION_CAN_WAKEUP();\r
+\r
+\r
+ SCHM_MAINFUNCTION_COMRX();\r
+ SCHM_MAINFUNCTION_COMTX();\r
+\r
+ SCHM_MAINFUNCTION_CANTP();\r
+ SCHM_MAINFUNCTION_J1939TP();\r
+ SCHM_MAINFUNCTION_DCM();\r
+ SCHM_MAINFUNCTION_DEM();\r
+\r
+ SCHM_MAINFUNCTION_IOWHAB();\r
+ SCHM_MAINFUNCTION_COMM();\r
+ SCHM_MAINFUNCTION_NM();\r
+ SCHM_MAINFUNCTION_CANNM();\r
+ SCHM_MAINFUNCTION_CANSM();\r
+ SCHM_MAINFUNCTION_WDGM_TRIGGER();\r
+ SCHM_MAINFUNCTION_WDGM_ALIVESUPERVISION();\r
+ break;\r
+ }\r
+\r
+ TerminateTask();\r
+}\r
+\r
+void SchM_MainFunction( void ) {\r
+\r
+}\r
\r
\r
\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
#ifndef SCHM_H_\r
#define SCHM_H_\r
\r
void SchM_Deinit( void );\r
void SchM_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
\r
+#define SchM_Enter( _module, _exc_area ) \\r
+ SchM_Enter_EcuM ## _module ## _exc_area\r
+\r
+#define SchM_Exit( _module, _exc_area ) \\r
+ SchM_Enter_EcuM ## _module ## _exc_area\r
+\r
+\r
+#define CONCAT_(_x,_y) _x##_y\r
+\r
+\r
+typedef struct {\r
+ uint32 timer;\r
+} SchM_InfoType;\r
+\r
+#define SCHM_DECLARE(_mod) \\r
+ SchM_InfoType SchM_Info_ ## _mod\r
+\r
+#define SCHM_MAINFUNCTION(_mod,_func) \\r
+ if( (++SchM_Info_ ## _mod.timer % SCHM_MAINFUNCTION_CYCLE_ ## _mod )== 0 ) { \\r
+ _func; \\r
+ SchM_Info_ ## _mod.timer = 0; \\r
+ }\r
+\r
+\r
+\r
#endif /*SCHM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SCHM_CAN_H_\r
+#define SCHM_CAN_H_\r
+\r
+#define SCHM_MAINFUNCTION_CAN_WRITE() SCHM_MAINFUNCTION(CAN_WRITE,Can_MainFunction_Write())\r
+#define SCHM_MAINFUNCTION_CAN_READ() SCHM_MAINFUNCTION(CAN_READ,Can_MainFunction_Read())\r
+#define SCHM_MAINFUNCTION_CAN_BUSOFF() SCHM_MAINFUNCTION(CAN_BUSOFF,Can_MainFunction_BusOff())\r
+#define SCHM_MAINFUNCTION_CAN_WAKEUP() SCHM_MAINFUNCTION(CAN_WAKEUP,Can_MainFunction_Wakeup())\r
+#define SCHM_MAINFUNCTION_CAN_ERROR() SCHM_MAINFUNCTION(CAN_ERROR,Can_MainFunction_Error())\r
+\r
+#endif /* SCHM_CAN_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SCHM_CANIF_H_\r
+#define SCHM_CANIF_H_\r
+\r
+\r
+#endif /* SCHM_CANIF_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SCHM_CANNM_H_\r
+#define SCHM_CANNM_H_\r
+\r
+#define SCHM_MAINFUNCTION_CANNM() SCHM_MAINFUNCTION(CANNM,CanNm_MainFunction())\r
+\r
+\r
+#endif /* SCHM_CANNM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_CANSM_H_\r
+#define SCHM_CANSM_H_\r
+\r
+#define SCHM_MAINFUNCTION_CANSM() SCHM_MAINFUNCTION(CANSM,CanSM_MainFunction())\r
+\r
+#endif /* SCHM_CANSM_H_ */\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-\r
-\r
-/** @addtogroup TBD\r
- * @{ */\r
-\r
-/** @file schM_CanTp.h\r
- * TBD.\r
- */\r
-\r
-\r
#ifndef SCHM_CANTP_H_\r
#define SCHM_CANTP_H_\r
\r
+#define SCHM_MAINFUNCTION_CANTP() SCHM_MAINFUNCTION(CANTP,CanTp_MainFunction())\r
\r
#endif /* SCHM_CANTP_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_COM_H_\r
+#define SCHM_COM_H_\r
+\r
+#define SCHM_MAINFUNCTION_COMRX() SCHM_MAINFUNCTION(COMRX,Com_MainFunctionRx())\r
+#define SCHM_MAINFUNCTION_COMTX() SCHM_MAINFUNCTION(COMTX,Com_MainFunctionTx())\r
+\r
+#endif /* SCHM_COM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_COMM_H_\r
+#define SCHM_COMM_H_\r
+\r
+#define SCHM_MAINFUNCTION_COMM() SCHM_MAINFUNCTION(COMM,ComM_MainFunction())\r
+\r
+#endif /* SCHM_COMM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_DCM_H_\r
+#define SCHM_DCM_H_\r
+\r
+#define SCHM_MAINFUNCTION_DCM() SCHM_MAINFUNCTION(DCM,Dcm_MainFunction())\r
+\r
+#endif /* SCHM_DCM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_DEM_H_\r
+#define SCHM_DEM_H_\r
+\r
+#define SCHM_MAINFUNCTION_DEM() SCHM_MAINFUNCTION(DEM,Dem_MainFunction())\r
+\r
+#endif /* SCHM_DEM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_ECUM_H_\r
+#define SCHM_ECUM_H_\r
+\r
+/*\r
+ * "Prototypes"\r
+ */\r
+#define SchM_Enter_EcuM(_area) CONCAT_(SchM_Enter_EcuM_,_area)\r
+#define SchM_Exit_EcuM(_area) CONCAT_(SchM_Exit_EcuM_,_area)\r
+\r
+/*\r
+ * Exclusive Areas\r
+ */\r
+\r
+/* Lock interrupts */\r
+#define EXCLUSIVE_AREA_0 0\r
+\r
+#define SchM_Enter_EcuM_0 DisableAllInterrupts\r
+#define SchM_Exit_EcuM_0 ResumeAllInterrupts\r
+\r
+#define SCHM_MAINFUNCTION_ECUM() SCHM_MAINFUNCTION(ECUM,EcuM_MainFunction())\r
+\r
+\r
+/* Skip "instance", req INTEGR058 */\r
+#if 0\r
+#define SchM_Enter_EcuM(uint8 exclusiveArea )\r
+#define SchM_Exit_EcuM(uint8 exclusiveArea )\r
+#define SchM_ActMainFunction_EcuM(uint8 exclusiveArea )\r
+#define SchM_CancelMainFunction_EcuM( uint8 exclusiveArea )\r
+#endif\r
+\r
+#endif /* SCHM_ECUM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef SCHM_FEE_H_\r
+#define SCHM_FEE_H_\r
+\r
+#define SCHM_MAINFUNCTION_FEE() SCHM_MAINFUNCTION(FEE,Fee_MainFunction())\r
+\r
+#endif /* SCHM_FEE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef SCHM_FLS_H_\r
+#define SCHM_FLS_H_\r
+\r
+#define SCHM_MAINFUNCTION_FLS() SCHM_MAINFUNCTION(FLS,Fls_MainFunction())\r
+\r
+#endif /* SCHM_FLS_H_ */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef SCHM_NM_H_\r
+#define SCHM_NM_H_\r
\r
-/** @addtogroup SchM\r
- * @{ */\r
+#define SCHM_MAINFUNCTION_NM() SCHM_MAINFUNCTION(NM,Nm_MainFunction())\r
\r
-/** @file SchM_EcuM.h\r
- */\r
-\r
-\r
-#ifndef SCHM_ECUM_H_\r
-#define SCHM_ECUM_H_\r
-\r
-\r
-#endif /* SCHM_ECUM_H_ */\r
+#endif /* SCHM_NM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_NVM_H_\r
+#define SCHM_NVM_H_\r
+\r
+#define SCHM_MAINFUNCTION_NVM() SCHM_MAINFUNCTION(NVM,NvM_MainFunction())\r
+\r
+#endif /* SCHM_NVM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SCHM_PDUR_H_\r
+#define SCHM_PDUR_H_\r
+\r
+\r
+\r
+#endif /* SCHM_PDUR_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SCHM_PWM_H_\r
+#define SCHM_PWM_H_\r
+\r
+\r
+\r
+#endif /* SCHM_PWM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef SCHM_WDGM_H_\r
+#define SCHM_WDGM_H_\r
+\r
+#define SCHM_MAINFUNCTION_WDGM_TRIGGER() SCHM_MAINFUNCTION(WDGM_TRIGGER,WdgM_MainFunction_Trigger())\r
+#define SCHM_MAINFUNCTION_WDGM_ALIVESUPERVISION() SCHM_MAINFUNCTION(WDGM_ALIVESUPERVISION,WdgM_MainFunction_AliveSupervision())\r
+\r
+#define SCHM_MAINFUNCTION_WDGM() SCHM_MAINFUNCTION(WDGM,Dcm_MainFunction())\r
+\r
+#endif /* SCHM_WDGM_H_ */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef SCHM_CFG_H_\r
+#define SCHM_CFG_H_\r
\r
\r
+#define SCHM_MF_MEM_PERIOD 20\r
\r
+/*\r
+ * Scheduling BSW\r
+ */\r
+#define SCHM_CYCLE_MAIN (5)\r
\r
+#define SCHM_MAINFUNCTION_CYCLE_ADC SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CAN_WRITE SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CAN_READ SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CAN_BUSOFF SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CAN_WAKEUP SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CAN_ERROR SCHM_CYCLE_MAIN\r
\r
+#define SCHM_MAINFUNCTION_CYCLE_CANNM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CANSM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CANTP SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_CANTRCV SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_COMRX SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_COMTX SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_COMM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_DCM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_DEM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_ECUM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_EA SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_EEP SCHM_CYCLE_MAIN\r
+//#define SCHM_MAINFUNCTION_CYCLE_FEE SCHM_CYCLE_MAIN\r
+//#define SCHM_MAINFUNCTION_CYCLE_FLS SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_IOHWAB SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_NM SCHM_CYCLE_MAIN\r
+//#define SCHM_MAINFUNCTION_CYCLE_NvM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_PDUR SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_SPI SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_WDGM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_WDGM_TRIGGER SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_WDGM_ALIVESUPERVISION SCHM_CYCLE_MAIN\r
+\r
+/*\r
+ * Schedule BSW memory\r
+ */\r
+\r
+#define SCHM_MAINFUNCTION_CYCLE_NVM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_FEE SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_FLS SCHM_CYCLE_MAIN\r
\r
-#ifndef SCHM_CFG_H_\r
-#define SCHM_CFG_H_\r
\r
#endif /*SCHM_CFG_H_*/\r
projects / arc.git / commitdiff