1 /****************************************************************************
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4 * FILE : MPC5607B_2.01.h
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6 * DESCRIPTION : This is the header file describing the register
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9 * COPYRIGHT :(c) 2011, Freescale
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14 * HISTORY : Based Upon Bolero 1M; Version 0.03 header file
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15 * Updated and corrected errors present on B1.5M 01.04.1
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16 * and have brought up to date and format with B3M. Corrected
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20 * Example instantiation and use:
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22 * <MODULE>.<REGISTER>.B.<BIT> = 1;
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23 * <MODULE>.<REGISTER>.R = 0x10000000;
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25 *****************************************************************************/
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30 #include "typedefs.h"
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38 #pragma ANSI_strict off
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42 /****************************************************************************/
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44 /****************************************************************************/
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47 union { /* ADC0 Main Configuration Register (Base+0x0000) */
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62 vuint32_t ADCLKSEL:1;
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63 vuint32_t ABORTCHAIN:1;
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71 union { /* ADC0 Main Status Register (Base+0x0004) */
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80 vuint32_t CTUSTART:1;
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85 vuint32_t ADCSTATUS:3;
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89 vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
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91 union { /* ADC0 Interrupt Status (Base+0x0010) */
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104 union { /* ADC0 Channel Pending 0 (Base+0x0014) */
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105 vuint32_t R; /* (For precision channels) */
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107 vuint32_t EOC_CH31:1;
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108 vuint32_t EOC_CH30:1;
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109 vuint32_t EOC_CH29:1;
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110 vuint32_t EOC_CH28:1;
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111 vuint32_t EOC_CH27:1;
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112 vuint32_t EOC_CH26:1;
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113 vuint32_t EOC_CH25:1;
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114 vuint32_t EOC_CH24:1;
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115 vuint32_t EOC_CH23:1;
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116 vuint32_t EOC_CH22:1;
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117 vuint32_t EOC_CH21:1;
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118 vuint32_t EOC_CH20:1;
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119 vuint32_t EOC_CH19:1;
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120 vuint32_t EOC_CH18:1;
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121 vuint32_t EOC_CH17:1;
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122 vuint32_t EOC_CH16:1;
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123 vuint32_t EOC_CH15:1;
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124 vuint32_t EOC_CH14:1;
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125 vuint32_t EOC_CH13:1;
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126 vuint32_t EOC_CH12:1;
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127 vuint32_t EOC_CH11:1;
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128 vuint32_t EOC_CH10:1;
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129 vuint32_t EOC_CH9:1;
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130 vuint32_t EOC_CH8:1;
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131 vuint32_t EOC_CH7:1;
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132 vuint32_t EOC_CH6:1;
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133 vuint32_t EOC_CH5:1;
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134 vuint32_t EOC_CH4:1;
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135 vuint32_t EOC_CH3:1;
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136 vuint32_t EOC_CH2:1;
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137 vuint32_t EOC_CH1:1;
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138 vuint32_t EOC_CH0:1;
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143 union { /* ADC0 Channel Pending Register 1 (Base+0x0018)*/
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146 vuint32_t EOC_CH63:1;
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147 vuint32_t EOC_CH62:1;
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148 vuint32_t EOC_CH61:1;
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149 vuint32_t EOC_CH60:1;
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150 vuint32_t EOC_CH59:1;
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151 vuint32_t EOC_CH58:1;
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152 vuint32_t EOC_CH57:1;
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153 vuint32_t EOC_CH56:1;
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154 vuint32_t EOC_CH55:1;
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155 vuint32_t EOC_CH54:1;
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156 vuint32_t EOC_CH53:1;
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157 vuint32_t EOC_CH52:1;
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158 vuint32_t EOC_CH51:1;
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159 vuint32_t EOC_CH50:1;
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160 vuint32_t EOC_CH49:1;
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161 vuint32_t EOC_CH48:1;
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162 vuint32_t EOC_CH47:1;
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163 vuint32_t EOC_CH46:1;
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164 vuint32_t EOC_CH45:1;
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165 vuint32_t EOC_CH44:1;
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166 vuint32_t EOC_CH43:1;
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167 vuint32_t EOC_CH42:1;
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168 vuint32_t EOC_CH41:1;
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169 vuint32_t EOC_CH40:1;
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170 vuint32_t EOC_CH39:1;
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171 vuint32_t EOC_CH38:1;
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172 vuint32_t EOC_CH37:1;
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173 vuint32_t EOC_CH36:1;
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174 vuint32_t EOC_CH35:1;
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175 vuint32_t EOC_CH34:1;
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176 vuint32_t EOC_CH33:1;
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177 vuint32_t EOC_CH32:1;
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181 union { /* ADC0 Channel Pending 2 (Base+0x001C) */
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182 vuint32_t R; /* (For external mux'd Channels) */
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184 vuint32_t EOC_CH95:1;
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185 vuint32_t EOC_CH94:1;
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186 vuint32_t EOC_CH93:1;
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187 vuint32_t EOC_CH92:1;
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188 vuint32_t EOC_CH91:1;
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189 vuint32_t EOC_CH90:1;
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190 vuint32_t EOC_CH89:1;
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191 vuint32_t EOC_CH88:1;
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192 vuint32_t EOC_CH87:1;
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193 vuint32_t EOC_CH86:1;
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194 vuint32_t EOC_CH85:1;
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195 vuint32_t EOC_CH84:1;
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196 vuint32_t EOC_CH83:1;
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197 vuint32_t EOC_CH82:1;
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198 vuint32_t EOC_CH81:1;
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199 vuint32_t EOC_CH80:1;
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200 vuint32_t EOC_CH79:1;
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201 vuint32_t EOC_CH78:1;
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202 vuint32_t EOC_CH77:1;
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203 vuint32_t EOC_CH76:1;
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204 vuint32_t EOC_CH75:1;
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205 vuint32_t EOC_CH74:1;
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206 vuint32_t EOC_CH73:1;
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207 vuint32_t EOC_CH72:1;
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208 vuint32_t EOC_CH71:1;
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209 vuint32_t EOC_CH70:1;
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210 vuint32_t EOC_CH69:1;
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211 vuint32_t EOC_CH68:1;
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212 vuint32_t EOC_CH67:1;
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213 vuint32_t EOC_CH66:1;
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214 vuint32_t EOC_CH65:1;
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215 vuint32_t EOC_CH64:1;
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220 union { /* ADC0 Interrupt Mask (Base+0020) */
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224 vuint32_t MSKEOCTU:1;
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225 vuint32_t MSKJEOC:1;
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226 vuint32_t MSKJECH:1;
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227 vuint32_t MSKEOC:1;
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228 vuint32_t MSKECH:1;
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234 union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */
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235 vuint32_t R; /* (For Precision Channels) */
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257 union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */
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258 vuint32_t R; /* (For Standard Channels) */
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295 union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */
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296 vuint32_t R; /* (For PExternal Mux'd Channels) */
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333 union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/
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337 vuint32_t WDG5H:1;
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338 vuint32_t WDG5L:1;
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339 vuint32_t WDG4H:1;
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340 vuint32_t WDG4L:1;
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341 vuint32_t WDG3H:1;
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342 vuint32_t WDG3L:1;
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343 vuint32_t WDG2H:1;
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344 vuint32_t WDG2L:1;
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346 vuint32_t WDG1L:1;
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347 vuint32_t WDG0H:1;
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348 vuint32_t WDG0L:1;
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352 union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */
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356 vuint32_t MSKWDG5H:1;
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357 vuint32_t MSKWDG5L:1;
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358 vuint32_t MSKWDG4H:1;
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359 vuint32_t MSKWDG4L:1;
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360 vuint32_t MSKWDG3H:1;
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361 vuint32_t MSKWDG2H:1;
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362 vuint32_t MSKWDG1H:1;
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363 vuint32_t MSKWDG0H:1;
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364 vuint32_t MSKWDG3L:1;
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365 vuint32_t MSKWDG2L:1;
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366 vuint32_t MSKWDG1L:1;
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367 vuint32_t MSKWDG0L:1;
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371 vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
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373 union { /* ADC0 DMA Enable (Base+0x0040) */
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382 union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */
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383 vuint32_t R; /* (for precision channels) */
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405 union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */
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406 vuint32_t R; /* (for standard channels) */
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443 union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */
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444 vuint32_t R; /* (for external mux'd channels) */
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481 vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */
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484 /*Note the threshold registers are split [0..3] then [4..5]. For this
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485 reason thay are NOT implemented as an array in order to maintain
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486 concistency through all THRHLR registers */
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488 union { /* ADC0 Threshold 0 (Base+0x0060) */
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498 union { /* ADC0 Threshold 1 (Base+0x0064) */
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508 union { /* ADC0 Threshold 2 (Base+0x0068) */
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518 union { /* ADC0 Threshold 3 (Base+0x006C) */
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529 vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */
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531 union { /* ADC0 Presampling Control (Base+0x0080) */
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535 vuint32_t PREVAL2:2;
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536 vuint32_t PREVAL1:2;
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537 vuint32_t PREVAL0:2;
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538 vuint32_t PRECONV:1;
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543 union { /* ADC0 Presampling 0 (Base+0x0084) */
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544 vuint32_t R; /* (precision channels) */
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546 vuint32_t PRES31:1;
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547 vuint32_t PRES30:1;
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548 vuint32_t PRES29:1;
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549 vuint32_t PRES28:1;
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550 vuint32_t PRES27:1;
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551 vuint32_t PRES26:1;
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552 vuint32_t PRES25:1;
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553 vuint32_t PRES24:1;
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554 vuint32_t PRES23:1;
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555 vuint32_t PRES22:1;
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556 vuint32_t PRES21:1;
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557 vuint32_t PRES20:1;
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558 vuint32_t PRES19:1;
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559 vuint32_t PRES18:1;
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560 vuint32_t PRES17:1;
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561 vuint32_t PRES16:1;
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562 vuint32_t PRES15:1;
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563 vuint32_t PRES14:1;
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564 vuint32_t PRES13:1;
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565 vuint32_t PRES12:1;
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566 vuint32_t PRES11:1;
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567 vuint32_t PRES10:1;
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581 union { /* ADC0 Presampling 1 (Base+0x0088) */
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582 vuint32_t R; /* (standard channels) */
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584 vuint32_t PRES63:1;
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585 vuint32_t PRES62:1;
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586 vuint32_t PRES61:1;
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587 vuint32_t PRES60:1;
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588 vuint32_t PRES59:1;
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589 vuint32_t PRES58:1;
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590 vuint32_t PRES57:1;
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591 vuint32_t PRES56:1;
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592 vuint32_t PRES55:1;
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593 vuint32_t PRES54:1;
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594 vuint32_t PRES53:1;
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595 vuint32_t PRES52:1;
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596 vuint32_t PRES51:1;
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597 vuint32_t PRES50:1;
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598 vuint32_t PRES49:1;
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599 vuint32_t PRES48:1;
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600 vuint32_t PRES47:1;
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601 vuint32_t PRES46:1;
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602 vuint32_t PRES45:1;
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603 vuint32_t PRES44:1;
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604 vuint32_t PRES43:1;
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605 vuint32_t PRES42:1;
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606 vuint32_t PRES41:1;
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607 vuint32_t PRES40:1;
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608 vuint32_t PRES39:1;
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609 vuint32_t PRES38:1;
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610 vuint32_t PRES37:1;
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611 vuint32_t PRES36:1;
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612 vuint32_t PRES35:1;
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613 vuint32_t PRES34:1;
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614 vuint32_t PRES33:1;
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615 vuint32_t PRES32:1;
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619 union { /* ADC0 Presampling 2 (Base+0x008C) */
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620 vuint32_t R; /* (external mux'd channels) */
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622 vuint32_t PRES95:1;
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623 vuint32_t PRES94:1;
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624 vuint32_t PRES93:1;
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625 vuint32_t PRES92:1;
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626 vuint32_t PRES91:1;
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627 vuint32_t PRES90:1;
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628 vuint32_t PRES89:1;
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629 vuint32_t PRES88:1;
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630 vuint32_t PRES87:1;
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631 vuint32_t PRES86:1;
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632 vuint32_t PRES85:1;
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633 vuint32_t PRES84:1;
\r
634 vuint32_t PRES83:1;
\r
635 vuint32_t PRES82:1;
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636 vuint32_t PRES81:1;
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637 vuint32_t PRES80:1;
\r
638 vuint32_t PRES79:1;
\r
639 vuint32_t PRES78:1;
\r
640 vuint32_t PRES77:1;
\r
641 vuint32_t PRES76:1;
\r
642 vuint32_t PRES75:1;
\r
643 vuint32_t PRES74:1;
\r
644 vuint32_t PRES73:1;
\r
645 vuint32_t PRES72:1;
\r
646 vuint32_t PRES71:1;
\r
647 vuint32_t PRES70:1;
\r
648 vuint32_t PRES69:1;
\r
649 vuint32_t PRES68:1;
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650 vuint32_t PRES67:1;
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651 vuint32_t PRES66:1;
\r
652 vuint32_t PRES65:1;
\r
653 vuint32_t PRES64:1;
\r
657 vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
\r
661 /* Note the following CTR registers are NOT implemented as an array to */
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662 /* try and maintain some concistency through the header file */
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663 /* (The registers are however identical) */
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665 union { /* ADC0 Conversion Timing 0 (Base+0x0094) */
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666 vuint32_t R; /* (precision channels) */
\r
669 vuint32_t INPLATCH:1;
\r
671 vuint32_t OFFSHIFT:2;
\r
673 vuint32_t INPCMP:2;
\r
675 vuint32_t INPSAMP:8;
\r
679 union { /* ADC0 Conversion Timing 1 (Base+0x0098) */
\r
680 vuint32_t R; /* (standard channels) */
\r
683 vuint32_t INPLATCH:1;
\r
685 vuint32_t OFFSHIFT:2;
\r
687 vuint32_t INPCMP:2;
\r
689 vuint32_t INPSAMP:8;
\r
693 union { /* ADC0 Conversion Timing 2 (Base+0x009C) */
\r
694 vuint32_t R; /* (precision channels) */
\r
697 vuint32_t INPLATCH:1;
\r
699 vuint32_t OFFSHIFT:2;
\r
701 vuint32_t INPCMP:2;
\r
703 vuint32_t INPSAMP:8;
\r
707 vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */
\r
710 union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */
\r
711 vuint32_t R; /* (precision channels) */
\r
733 union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */
\r
734 vuint32_t R; /* (standard channels) */
\r
768 union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */
\r
769 vuint32_t R; /* (For external mux'd channels) */
\r
806 vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */
\r
809 union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */
\r
810 vuint32_t R; /* (precision channels) */
\r
832 union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */
\r
833 vuint32_t R; /* (standard channels) */
\r
867 union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */
\r
868 vuint32_t R; /* (external mux'd channels) */
\r
906 vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */
\r
908 union { /* ADC0 Decode Signals Delay (Base+0x00C4) */
\r
916 union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */
\r
925 vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
\r
927 union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */
\r
928 vuint32_t R; /* Note CDR[16..31] and CDR[60..63] are reserved */
\r
933 vuint32_t RESULT:2;
\r
935 vuint32_t CDATA:10;
\r
939 union { /* ADC0 Threshold 4 (Base+0x0280) */
\r
949 union { /* ADC0 Threshold 5 (Base+0x0284) */
\r
959 vuint8_t ADC0_reserved9[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */
\r
962 union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */
\r
963 vuint32_t R; /* (precision channels) */
\r
966 vuint32_t WSEL_CH7:3;
\r
968 vuint32_t WSEL_CH6:3;
\r
970 vuint32_t WSEL_CH5:3;
\r
972 vuint32_t WSEL_CH4:3;
\r
974 vuint32_t WSEL_CH3:3;
\r
976 vuint32_t WSEL_CH2:3;
\r
978 vuint32_t WSEL_CH1:3;
\r
980 vuint32_t WSEL_CH0:3;
\r
984 union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */
\r
985 vuint32_t R; /* (precision channels) */
\r
988 vuint32_t WSEL_CH15:3;
\r
990 vuint32_t WSEL_CH14:3;
\r
992 vuint32_t WSEL_CH13:3;
\r
994 vuint32_t WSEL_CH12:3;
\r
996 vuint32_t WSEL_CH11:3;
\r
998 vuint32_t WSEL_CH10:3;
\r
1000 vuint32_t WSEL_CH9:3;
\r
1002 vuint32_t WSEL_CH8:3;
\r
1006 vuint8_t ADC0_reserved10[8]; /* Reserved 4 bytes (Base+0x02B8-0x02BF) */
\r
1008 union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */
\r
1009 vuint32_t R; /* (standard channels) */
\r
1012 vuint32_t WSEL_CH39:3;
\r
1014 vuint32_t WSEL_CH38:3;
\r
1016 vuint32_t WSEL_CH37:3;
\r
1018 vuint32_t WSEL_CH36:3;
\r
1020 vuint32_t WSEL_CH35:3;
\r
1022 vuint32_t WSEL_CH34:3;
\r
1024 vuint32_t WSEL_CH33:3;
\r
1026 vuint32_t WSEL_CH32:3;
\r
1030 union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */
\r
1031 vuint32_t R; /* (standard channels) */
\r
1034 vuint32_t WSEL_CH47:3;
\r
1036 vuint32_t WSEL_CH46:3;
\r
1038 vuint32_t WSEL_CH45:3;
\r
1040 vuint32_t WSEL_CH44:3;
\r
1042 vuint32_t WSEL_CH43:3;
\r
1044 vuint32_t WSEL_CH42:3;
\r
1046 vuint32_t WSEL_CH41:3;
\r
1048 vuint32_t WSEL_CH40:3;
\r
1052 union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */
\r
1053 vuint32_t R; /* (standard channels) */
\r
1056 vuint32_t WSEL_CH55:3;
\r
1058 vuint32_t WSEL_CH54:3;
\r
1060 vuint32_t WSEL_CH53:3;
\r
1062 vuint32_t WSEL_CH52:3;
\r
1064 vuint32_t WSEL_CH51:3;
\r
1066 vuint32_t WSEL_CH50:3;
\r
1068 vuint32_t WSEL_CH49:3;
\r
1070 vuint32_t WSEL_CH48:3;
\r
1074 union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */
\r
1075 vuint32_t R; /* (standard channels) */
\r
1078 vuint32_t WSEL_CH63:3;
\r
1080 vuint32_t WSEL_CH62:3;
\r
1082 vuint32_t WSEL_CH61:3;
\r
1084 vuint32_t WSEL_CH60:3;
\r
1086 vuint32_t WSEL_CH59:3;
\r
1091 union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */
\r
1092 vuint32_t R; /* (external mux'd channels) */
\r
1095 vuint32_t WSEL_CH71:3;
\r
1097 vuint32_t WSEL_CH70:3;
\r
1099 vuint32_t WSEL_CH69:3;
\r
1101 vuint32_t WSEL_CH68:3;
\r
1103 vuint32_t WSEL_CH67:3;
\r
1105 vuint32_t WSEL_CH66:3;
\r
1107 vuint32_t WSEL_CH65:3;
\r
1109 vuint32_t WSEL_CH64:3;
\r
1113 union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */
\r
1114 vuint32_t R; /* (external mux'd channels) */
\r
1117 vuint32_t WSEL_CH79:3;
\r
1119 vuint32_t WSEL_CH78:3;
\r
1121 vuint32_t WSEL_CH77:3;
\r
1123 vuint32_t WSEL_CH76:3;
\r
1125 vuint32_t WSEL_CH75:3;
\r
1127 vuint32_t WSEL_CH74:3;
\r
1129 vuint32_t WSEL_CH73:3;
\r
1131 vuint32_t WSEL_CH72:3;
\r
1135 union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/
\r
1136 vuint32_t R; /* (external mux'd channels) */
\r
1139 vuint32_t WSEL_CH87:3;
\r
1141 vuint32_t WSEL_CH86:3;
\r
1143 vuint32_t WSEL_CH85:3;
\r
1145 vuint32_t WSEL_CH84:3;
\r
1147 vuint32_t WSEL_CH83:3;
\r
1149 vuint32_t WSEL_CH82:3;
\r
1151 vuint32_t WSEL_CH81:3;
\r
1153 vuint32_t WSEL_CH80:3;
\r
1157 union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/
\r
1158 vuint32_t R; /* (external mux'd channels) */
\r
1161 vuint32_t WSEL_CH95:3;
\r
1163 vuint32_t WSEL_CH94:3;
\r
1165 vuint32_t WSEL_CH93:3;
\r
1167 vuint32_t WSEL_CH92:3;
\r
1169 vuint32_t WSEL_CH91:3;
\r
1171 vuint32_t WSEL_CH90:3;
\r
1173 vuint32_t WSEL_CH89:3;
\r
1175 vuint32_t WSEL_CH88:3;
\r
1179 union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */
\r
1180 vuint32_t R; /* (precision channels) */
\r
1183 vuint32_t CWEN15:1;
\r
1184 vuint32_t CWEN14:1;
\r
1185 vuint32_t CWEN13:1;
\r
1186 vuint32_t CWEN12:1;
\r
1187 vuint32_t CWEN11:1;
\r
1188 vuint32_t CWEN10:1;
\r
1189 vuint32_t CWEN9:1;
\r
1190 vuint32_t CWEN8:1;
\r
1191 vuint32_t CWEN7:1;
\r
1192 vuint32_t CWEN6:1;
\r
1193 vuint32_t CWEN5:1;
\r
1194 vuint32_t CWEN4:1;
\r
1195 vuint32_t CWEN3:1;
\r
1196 vuint32_t CWEN2:1;
\r
1197 vuint32_t CWEN1:1;
\r
1198 vuint32_t CWEN0:1;
\r
1202 union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */
\r
1203 vuint32_t R; /* (standard channels) */
\r
1206 vuint32_t CWEN59:1;
\r
1207 vuint32_t CWEN58:1;
\r
1208 vuint32_t CWEN57:1;
\r
1209 vuint32_t CWEN56:1;
\r
1210 vuint32_t CWEN55:1;
\r
1211 vuint32_t CWEN54:1;
\r
1212 vuint32_t CWEN53:1;
\r
1213 vuint32_t CWEN52:1;
\r
1214 vuint32_t CWEN51:1;
\r
1215 vuint32_t CWEN50:1;
\r
1216 vuint32_t CWEN49:1;
\r
1217 vuint32_t CWEN48:1;
\r
1218 vuint32_t CWEN47:1;
\r
1219 vuint32_t CWEN46:1;
\r
1220 vuint32_t CWEN45:1;
\r
1221 vuint32_t CWEN44:1;
\r
1222 vuint32_t CWEN43:1;
\r
1223 vuint32_t CWEN42:1;
\r
1224 vuint32_t CWEN41:1;
\r
1225 vuint32_t CWEN40:1;
\r
1226 vuint32_t CWEN39:1;
\r
1227 vuint32_t CWEN38:1;
\r
1228 vuint32_t CWEN37:1;
\r
1229 vuint32_t CWEN36:1;
\r
1230 vuint32_t CWEN35:1;
\r
1231 vuint32_t CWEN34:1;
\r
1232 vuint32_t CWEN33:1;
\r
1233 vuint32_t CWEN32:1;
\r
1237 union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */
\r
1238 vuint32_t R; /* (external mux'd channels) */
\r
1240 vuint32_t CWEN95:1;
\r
1241 vuint32_t CWEN94:1;
\r
1242 vuint32_t CWEN93:1;
\r
1243 vuint32_t CWEN92:1;
\r
1244 vuint32_t CWEN91:1;
\r
1245 vuint32_t CWEN90:1;
\r
1246 vuint32_t CWEN89:1;
\r
1247 vuint32_t CWEN88:1;
\r
1248 vuint32_t CWEN87:1;
\r
1249 vuint32_t CWEN86:1;
\r
1250 vuint32_t CWEN85:1;
\r
1251 vuint32_t CWEN84:1;
\r
1252 vuint32_t CWEN83:1;
\r
1253 vuint32_t CWEN82:1;
\r
1254 vuint32_t CWEN81:1;
\r
1255 vuint32_t CWEN80:1;
\r
1256 vuint32_t CWEN79:1;
\r
1257 vuint32_t CWEN78:1;
\r
1258 vuint32_t CWEN77:1;
\r
1259 vuint32_t CWEN76:1;
\r
1260 vuint32_t CWEN75:1;
\r
1261 vuint32_t CWEN74:1;
\r
1262 vuint32_t CWEN73:1;
\r
1263 vuint32_t CWEN72:1;
\r
1264 vuint32_t CWEN71:1;
\r
1265 vuint32_t CWEN70:1;
\r
1266 vuint32_t CWEN69:1;
\r
1267 vuint32_t CWEN68:1;
\r
1268 vuint32_t CWEN67:1;
\r
1269 vuint32_t CWEN66:1;
\r
1270 vuint32_t CWEN65:1;
\r
1271 vuint32_t CWEN64:1;
\r
1275 vuint8_t ADC0_reserved11[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */
\r
1277 union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */
\r
1281 vuint32_t AWORR_CH15:1;
\r
1282 vuint32_t AWORR_CH14:1;
\r
1283 vuint32_t AWORR_CH13:1;
\r
1284 vuint32_t AWORR_CH12:1;
\r
1285 vuint32_t AWORR_CH11:1;
\r
1286 vuint32_t AWORR_CH10:1;
\r
1287 vuint32_t AWORR_CH9:1;
\r
1288 vuint32_t AWORR_CH8:1;
\r
1289 vuint32_t AWORR_CH7:1;
\r
1290 vuint32_t AWORR_CH6:1;
\r
1291 vuint32_t AWORR_CH5:1;
\r
1292 vuint32_t AWORR_CH4:1;
\r
1293 vuint32_t AWORR_CH3:1;
\r
1294 vuint32_t AWORR_CH2:1;
\r
1295 vuint32_t AWORR_CH1:1;
\r
1296 vuint32_t AWORR_CH0:1;
\r
1300 union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */
\r
1304 vuint32_t AWORR_CH59:1;
\r
1305 vuint32_t AWORR_CH58:1;
\r
1306 vuint32_t AWORR_CH57:1;
\r
1307 vuint32_t AWORR_CH56:1;
\r
1308 vuint32_t AWORR_CH55:1;
\r
1309 vuint32_t AWORR_CH54:1;
\r
1310 vuint32_t AWORR_CH53:1;
\r
1311 vuint32_t AWORR_CH52:1;
\r
1312 vuint32_t AWORR_CH51:1;
\r
1313 vuint32_t AWORR_CH50:1;
\r
1314 vuint32_t AWORR_CH49:1;
\r
1315 vuint32_t AWORR_CH48:1;
\r
1316 vuint32_t AWORR_CH47:1;
\r
1317 vuint32_t AWORR_CH46:1;
\r
1318 vuint32_t AWORR_CH45:1;
\r
1319 vuint32_t AWORR_CH44:1;
\r
1320 vuint32_t AWORR_CH43:1;
\r
1321 vuint32_t AWORR_CH42:1;
\r
1322 vuint32_t AWORR_CH41:1;
\r
1323 vuint32_t AWORR_CH40:1;
\r
1324 vuint32_t AWORR_CH39:1;
\r
1325 vuint32_t AWORR_CH38:1;
\r
1326 vuint32_t AWORR_CH37:1;
\r
1327 vuint32_t AWORR_CH36:1;
\r
1328 vuint32_t AWORR_CH35:1;
\r
1329 vuint32_t AWORR_CH34:1;
\r
1330 vuint32_t AWORR_CH33:1;
\r
1331 vuint32_t AWORR_CH32:1;
\r
1335 union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */
\r
1338 vuint32_t AWORR_CH95:1;
\r
1339 vuint32_t AWORR_CH94:1;
\r
1340 vuint32_t AWORR_CH93:1;
\r
1341 vuint32_t AWORR_CH92:1;
\r
1342 vuint32_t AWORR_CH91:1;
\r
1343 vuint32_t AWORR_CH90:1;
\r
1344 vuint32_t AWORR_CH89:1;
\r
1345 vuint32_t AWORR_CH88:1;
\r
1346 vuint32_t AWORR_CH87:1;
\r
1347 vuint32_t AWORR_CH86:1;
\r
1348 vuint32_t AWORR_CH85:1;
\r
1349 vuint32_t AWORR_CH84:1;
\r
1350 vuint32_t AWORR_CH83:1;
\r
1351 vuint32_t AWORR_CH82:1;
\r
1352 vuint32_t AWORR_CH81:1;
\r
1353 vuint32_t AWORR_CH80:1;
\r
1354 vuint32_t AWORR_CH79:1;
\r
1355 vuint32_t AWORR_CH78:1;
\r
1356 vuint32_t AWORR_CH77:1;
\r
1357 vuint32_t AWORR_CH76:1;
\r
1358 vuint32_t AWORR_CH75:1;
\r
1359 vuint32_t AWORR_CH74:1;
\r
1360 vuint32_t AWORR_CH73:1;
\r
1361 vuint32_t AWORR_CH72:1;
\r
1362 vuint32_t AWORR_CH71:1;
\r
1363 vuint32_t AWORR_CH70:1;
\r
1364 vuint32_t AWORR_CH69:1;
\r
1365 vuint32_t AWORR_CH68:1;
\r
1366 vuint32_t AWORR_CH67:1;
\r
1367 vuint32_t AWORR_CH66:1;
\r
1368 vuint32_t AWORR_CH65:1;
\r
1369 vuint32_t AWORR_CH64:1;
\r
1373 //vuint8_t ADC0_reserved12[15620]; /* Reserved 15620 bytes (Base+0x02FC-0x3FFF) */
\r
1375 }; /* end of ADC0_tag */
\r
1377 /****************************************************************************/
\r
1378 /* MODULE : ADC1 (12 Bit) */
\r
1379 /****************************************************************************/
\r
1382 union { /* ADC1 Main Configuration (Base+0x0000) */
\r
1385 vuint32_t OWREN:1;
\r
1386 vuint32_t WLSIDE:1;
\r
1389 vuint32_t NSTART:1;
\r
1391 vuint32_t JTRGEN:1;
\r
1392 vuint32_t JEDGE:1;
\r
1393 vuint32_t JSTART:1;
\r
1395 vuint32_t CTUEN:1;
\r
1397 vuint32_t ADCLKSEL:1;
\r
1398 vuint32_t ABORT_CHAIN:1;
\r
1399 vuint32_t ABORT:1;
\r
1407 union { /* ADC1 Main Status (Base+0x0004) */
\r
1411 vuint32_t NSTART:1;
\r
1412 vuint32_t JABORT:1;
\r
1414 vuint32_t JSTART:1;
\r
1416 vuint32_t CTUSTART:1;
\r
1417 vuint32_t CHADDR:7;
\r
1421 vuint32_t ADCSTATUS:3;
\r
1425 vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
\r
1427 union { /* ADC1 Interrupt Status (Base+0x0010) */
\r
1431 vuint32_t EOCTU:1;
\r
1439 union { /* ADC1 Channel Pending 0 (Base+0x0014) */
\r
1440 vuint32_t R; /* (For precision channels) */
\r
1443 vuint32_t EOC_CH15:1;
\r
1444 vuint32_t EOC_CH14:1;
\r
1445 vuint32_t EOC_CH13:1;
\r
1446 vuint32_t EOC_CH12:1;
\r
1447 vuint32_t EOC_CH11:1;
\r
1448 vuint32_t EOC_CH10:1;
\r
1449 vuint32_t EOC_CH9:1;
\r
1450 vuint32_t EOC_CH8:1;
\r
1451 vuint32_t EOC_CH7:1;
\r
1452 vuint32_t EOC_CH6:1;
\r
1453 vuint32_t EOC_CH5:1;
\r
1454 vuint32_t EOC_CH4:1;
\r
1455 vuint32_t EOC_CH3:1;
\r
1456 vuint32_t EOC_CH2:1;
\r
1457 vuint32_t EOC_CH1:1;
\r
1458 vuint32_t EOC_CH0:1;
\r
1462 union { /* ADC1 Channel Pending 1 (Base+0x0018) */
\r
1463 vuint32_t R; /* (For standard Channels) */
\r
1466 vuint32_t EOC_CH39:1;
\r
1467 vuint32_t EOC_CH38:1;
\r
1468 vuint32_t EOC_CH37:1;
\r
1469 vuint32_t EOC_CH36:1;
\r
1470 vuint32_t EOC_CH35:1;
\r
1471 vuint32_t EOC_CH34:1;
\r
1472 vuint32_t EOC_CH33:1;
\r
1473 vuint32_t EOC_CH32:1;
\r
1477 vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */
\r
1479 union { /* ADC1 Interrupt Mask (Base+0020) */
\r
1483 vuint32_t MSKEOCTU:1;
\r
1484 vuint32_t MSKJEOC:1;
\r
1485 vuint32_t MSKJECH:1;
\r
1486 vuint32_t MSKEOC:1;
\r
1487 vuint32_t MSKECH:1;
\r
1491 union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
\r
1492 vuint32_t R; /* (For Precision Channels) */
\r
1495 vuint32_t CIM15:1;
\r
1496 vuint32_t CIM14:1;
\r
1497 vuint32_t CIM13:1;
\r
1498 vuint32_t CIM12:1;
\r
1499 vuint32_t CIM11:1;
\r
1500 vuint32_t CIM10:1;
\r
1514 union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
\r
1515 vuint32_t R; /* (For Standard Channels) */
\r
1518 vuint32_t CIM39:1;
\r
1519 vuint32_t CIM38:1;
\r
1520 vuint32_t CIM37:1;
\r
1521 vuint32_t CIM36:1;
\r
1522 vuint32_t CIM35:1;
\r
1523 vuint32_t CIM34:1;
\r
1524 vuint32_t CIM33:1;
\r
1525 vuint32_t CIM32:1;
\r
1529 vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */
\r
1531 union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
\r
1535 vuint32_t WDG2H:1;
\r
1536 vuint32_t WDG2L:1;
\r
1537 vuint32_t WDG1H:1;
\r
1538 vuint32_t WDG1L:1;
\r
1539 vuint32_t WDG0H:1;
\r
1540 vuint32_t WDG0L:1;
\r
1544 union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
\r
1548 vuint32_t MSKWDG2H:1;
\r
1549 vuint32_t MSKWDG2L:1;
\r
1550 vuint32_t MSKWDG1H:1;
\r
1551 vuint32_t MSKWDG1L:1;
\r
1552 vuint32_t MSKWDG0H:1;
\r
1553 vuint32_t MSKWDG0L:1;
\r
1557 vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
\r
1559 union { /* ADC1 DMA Enable (Base+0x0040) */
\r
1564 vuint32_t DMAEN:1;
\r
1568 union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
\r
1569 vuint32_t R; /* (for precision channels) */
\r
1572 vuint32_t DMA15:1;
\r
1573 vuint32_t DMA14:1;
\r
1574 vuint32_t DMA13:1;
\r
1575 vuint32_t DMA12:1;
\r
1576 vuint32_t DMA11:1;
\r
1577 vuint32_t DMA10:1;
\r
1591 union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
\r
1592 vuint32_t R; /* (for standard channels) */
\r
1595 vuint32_t DMA39:1;
\r
1596 vuint32_t DMA38:1;
\r
1597 vuint32_t DMA37:1;
\r
1598 vuint32_t DMA36:1;
\r
1599 vuint32_t DMA35:1;
\r
1600 vuint32_t DMA34:1;
\r
1601 vuint32_t DMA33:1;
\r
1602 vuint32_t DMA32:1;
\r
1606 vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */
\r
1608 /* Note the threshold registers are not implemented as an array for */
\r
1609 /* concistency with ADC0 header section */
\r
1611 union { /* ADC1 Threshold 0 (Base+0x0060) */
\r
1615 vuint32_t THRH:12;
\r
1617 vuint32_t THRL:12;
\r
1621 union { /* ADC1 Threshold 1 (Base+0x0064) */
\r
1625 vuint32_t THRH:12;
\r
1627 vuint32_t THRL:12;
\r
1631 union { /* ADC1 Threshold 2 (Base+0x0068) */
\r
1635 vuint32_t THRH:12;
\r
1637 vuint32_t THRL:12;
\r
1641 vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
\r
1643 union { /* ADC1 Presampling Control (Base+0x0080) */
\r
1647 vuint32_t PREVAL2:2;
\r
1648 vuint32_t PREVAL1:2;
\r
1649 vuint32_t PREVAL0:2;
\r
1650 vuint32_t PRECONV:1;
\r
1654 union { /* ADC1 Presampling 0 (Base+0x0084) */
\r
1655 vuint32_t R; /* (precision channels) */
\r
1658 vuint32_t PRES15:1;
\r
1659 vuint32_t PRES14:1;
\r
1660 vuint32_t PRES13:1;
\r
1661 vuint32_t PRES12:1;
\r
1662 vuint32_t PRES11:1;
\r
1663 vuint32_t PRES10:1;
\r
1664 vuint32_t PRES9:1;
\r
1665 vuint32_t PRES8:1;
\r
1666 vuint32_t PRES7:1;
\r
1667 vuint32_t PRES6:1;
\r
1668 vuint32_t PRES5:1;
\r
1669 vuint32_t PRES4:1;
\r
1670 vuint32_t PRES3:1;
\r
1671 vuint32_t PRES2:1;
\r
1672 vuint32_t PRES1:1;
\r
1673 vuint32_t PRES0:1;
\r
1677 union { /* ADC1 Presampling 1 (Base+0x0088) */
\r
1678 vuint32_t R; /* (standard channels) */
\r
1681 vuint32_t PRES39:1;
\r
1682 vuint32_t PRES38:1;
\r
1683 vuint32_t PRES37:1;
\r
1684 vuint32_t PRES36:1;
\r
1685 vuint32_t PRES35:1;
\r
1686 vuint32_t PRES34:1;
\r
1687 vuint32_t PRES33:1;
\r
1688 vuint32_t PRES32:1;
\r
1692 vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */
\r
1694 /* Note the following CTR registers are NOT implemented as an array to */
\r
1695 /* try and maintain some concistency through the header file */
\r
1696 /* (The registers are however identical) */
\r
1698 union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
\r
1699 vuint32_t R; /* (precision channels) */
\r
1702 vuint32_t INPLATCH:1;
\r
1704 vuint32_t OFFSHIFT:2;
\r
1706 vuint32_t INPCMP:2;
\r
1708 vuint32_t INPSAMP:8;
\r
1712 union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
\r
1713 vuint32_t R; /* (standard channels) */
\r
1716 vuint32_t INPLATCH:1;
\r
1718 vuint32_t OFFSHIFT:2;
\r
1720 vuint32_t INPCMP:2;
\r
1722 vuint32_t INPSAMP:8;
\r
1726 vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */
\r
1728 union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
\r
1729 vuint32_t R; /* (precision channels) */
\r
1751 union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
\r
1752 vuint32_t R; /* (standard channels) */
\r
1766 vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */
\r
1768 union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
\r
1769 vuint32_t R; /* (precision channels) */
\r
1791 union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
\r
1792 vuint32_t R; /* (standard channels) */
\r
1806 vuint8_t ADC1_reserved9[12]; /* Reserved 12 bytes (Base+0x00BC-0x00C7) */
\r
1808 union { /* Power Down Exit Delay Register (base+0x00C8)*/
\r
1816 vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
\r
1818 union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */
\r
1819 vuint32_t R; /* Note CDR[16..31] are reserved 0x0140-0x017F */
\r
1822 vuint32_t VALID:1;
\r
1823 vuint32_t OVERW:1;
\r
1824 vuint32_t RESULT:2;
\r
1826 vuint32_t CDATA:12;
\r
1830 vuint8_t ADC1_reserved11[272]; /* Reserved 252 bytes (Base+0x01A0-0x002AF) */
\r
1832 union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
\r
1833 vuint32_t R; /* (precision channels) */
\r
1836 vuint32_t WSEL_CH7:2;
\r
1838 vuint32_t WSEL_CH6:2;
\r
1840 vuint32_t WSEL_CH5:2;
\r
1842 vuint32_t WSEL_CH4:2;
\r
1844 vuint32_t WSEL_CH3:2;
\r
1846 vuint32_t WSEL_CH2:2;
\r
1848 vuint32_t WSEL_CH1:2;
\r
1850 vuint32_t WSEL_CH0:2;
\r
1854 union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
\r
1855 vuint32_t R; /* (precision channels) */
\r
1858 vuint32_t WSEL_CH15:2;
\r
1860 vuint32_t WSEL_CH14:2;
\r
1862 vuint32_t WSEL_CH13:2;
\r
1864 vuint32_t WSEL_CH12:2;
\r
1866 vuint32_t WSEL_CH11:2;
\r
1868 vuint32_t WSEL_CH10:2;
\r
1870 vuint32_t WSEL_CH9:2;
\r
1872 vuint32_t WSEL_CH8:2;
\r
1876 vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
\r
1878 union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
\r
1879 vuint32_t R; /* (standard channels) */
\r
1882 vuint32_t WSEL_CH39:2;
\r
1884 vuint32_t WSEL_CH38:2;
\r
1886 vuint32_t WSEL_CH37:2;
\r
1888 vuint32_t WSEL_CH36:2;
\r
1890 vuint32_t WSEL_CH35:2;
\r
1892 vuint32_t WSEL_CH34:2;
\r
1894 vuint32_t WSEL_CH33:2;
\r
1896 vuint32_t WSEL_CH32:2;
\r
1900 union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
\r
1901 vuint32_t R; /* (standard channels) */
\r
1904 vuint32_t WSEL_CH44:2;
\r
1906 vuint32_t WSEL_CH43:2;
\r
1908 vuint32_t WSEL_CH42:2;
\r
1910 vuint32_t WSEL_CH41:2;
\r
1912 vuint32_t WSEL_CH40:2;
\r
1916 vuint8_t ADC1_reserved13[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */
\r
1918 union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */
\r
1919 vuint32_t R; /* (precision channels) */
\r
1922 vuint32_t CWEN15:1;
\r
1923 vuint32_t CWEN14:1;
\r
1924 vuint32_t CWEN13:1;
\r
1925 vuint32_t CWEN12:1;
\r
1926 vuint32_t CWEN11:1;
\r
1927 vuint32_t CWEN10:1;
\r
1928 vuint32_t CWEN9:1;
\r
1929 vuint32_t CWEN8:1;
\r
1930 vuint32_t CWEN7:1;
\r
1931 vuint32_t CWEN6:1;
\r
1932 vuint32_t CWEN5:1;
\r
1933 vuint32_t CWEN4:1;
\r
1934 vuint32_t CWEN3:1;
\r
1935 vuint32_t CWEN2:1;
\r
1936 vuint32_t CWEN1:1;
\r
1937 vuint32_t CWEN0:1;
\r
1941 union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */
\r
1942 vuint32_t R; /* (standard channels) */
\r
1945 vuint32_t CWEN39:1;
\r
1946 vuint32_t CWEN38:1;
\r
1947 vuint32_t CWEN37:1;
\r
1948 vuint32_t CWEN36:1;
\r
1949 vuint32_t CWEN35:1;
\r
1950 vuint32_t CWEN34:1;
\r
1951 vuint32_t CWEN33:1;
\r
1952 vuint32_t CWEN32:1;
\r
1956 vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */
\r
1958 union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
\r
1962 vuint32_t AWORR_CH15:1;
\r
1963 vuint32_t AWORR_CH14:1;
\r
1964 vuint32_t AWORR_CH13:1;
\r
1965 vuint32_t AWORR_CH12:1;
\r
1966 vuint32_t AWORR_CH11:1;
\r
1967 vuint32_t AWORR_CH10:1;
\r
1968 vuint32_t AWORR_CH9:1;
\r
1969 vuint32_t AWORR_CH8:1;
\r
1970 vuint32_t AWORR_CH7:1;
\r
1971 vuint32_t AWORR_CH6:1;
\r
1972 vuint32_t AWORR_CH5:1;
\r
1973 vuint32_t AWORR_CH4:1;
\r
1974 vuint32_t AWORR_CH3:1;
\r
1975 vuint32_t AWORR_CH2:1;
\r
1976 vuint32_t AWORR_CH1:1;
\r
1977 vuint32_t AWORR_CH0:1;
\r
1981 union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
\r
1985 vuint32_t AWORR_CH39:1;
\r
1986 vuint32_t AWORR_CH38:1;
\r
1987 vuint32_t AWORR_CH37:1;
\r
1988 vuint32_t AWORR_CH36:1;
\r
1989 vuint32_t AWORR_CH35:1;
\r
1990 vuint32_t AWORR_CH34:1;
\r
1991 vuint32_t AWORR_CH33:1;
\r
1992 vuint32_t AWORR_CH32:1;
\r
1996 vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
\r
1998 }; /* end of ADC1_tag */
\r
1999 /****************************************************************************/
\r
2000 /* MODULE : CANSP */
\r
2001 /****************************************************************************/
\r
2002 struct CANSP_tag {
\r
2004 union { /* CANSP Control Reg (Base+0x0000) */
\r
2008 vuint32_t RX_COMPLETE:1;
\r
2010 vuint32_t ACTIVE_CK:1;
\r
2013 vuint32_t CAN_RX_SEL:3;
\r
2015 vuint32_t CAN_SMPLR_EN:1;
\r
2019 union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/
\r
2023 }; /* end of CANSP_tag */
\r
2024 /****************************************************************************/
\r
2025 /* MODULE : ECSM */
\r
2026 /****************************************************************************/
\r
2029 union { /* ECSM Processor Core Type (Base+0x0000) */
\r
2033 union { /* ECSM Revision (Base+0x0002) */
\r
2037 vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
\r
2039 union { /* ECSM IPS Module Configuration (Base+0x0008) */
\r
2043 vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */
\r
2045 union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */
\r
2048 vuint8_t ENBWCR:1;
\r
2050 vuint8_t PRILVL:4;
\r
2054 vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */
\r
2056 union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
\r
2067 vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
\r
2069 union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
\r
2071 } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
\r
2073 vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
\r
2075 union { /* ECSM ECC Configuration (Base+0x0043) */
\r
2087 vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
\r
2089 union { /* ECSM ECC Status (Base+0x0047) */
\r
2101 vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
\r
2103 union { /* ECSM ECC Error Generation (Base+0x004A) */
\r
2107 vuint16_t FRC1BI:1;
\r
2108 vuint16_t FR11BI:1;
\r
2110 vuint16_t FRCNCI:1;
\r
2111 vuint16_t FR1NCI:1;
\r
2113 vuint16_t ERRBIT:7;
\r
2117 vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
\r
2119 union { /* ECSM Flash ECC Address(Base+0x0050) */
\r
2123 vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
\r
2125 union { /* ECSM Flash ECC Master Number (Base+0x0056) */
\r
2133 union { /* ECSM Flash ECC Attributes (Base+0x0057) */
\r
2138 vuint8_t PROTECTION:4;
\r
2142 vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
\r
2144 union { /* ECSM Flash ECC Data (Base+0x005C) */
\r
2148 union { /* ECSM RAM ECC Address (Base+0x0060) */
\r
2152 vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
\r
2154 union { /* ECSM RAM ECC Address (Base+0x0065) */
\r
2158 union { /* ECSM RAM ECC Master Number (Base+0x0066) */
\r
2166 union { /* ECSM RAM ECC Attributes (Base+0x0067) */
\r
2171 vuint8_t PROTECTION:4;
\r
2175 vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
\r
2177 union { /* ECSM RAM ECC Data (Base+0x006C) */
\r
2181 }; /* end of ECSM_tag */
\r
2183 /****************************************************************************/
\r
2184 /* MODULE : RTC/API */
\r
2185 /****************************************************************************/
\r
2188 union { /* RTC Supervisor Control (Base+0x0000) */
\r
2196 union { /* RTC Control (Base+0x0004) */
\r
2199 vuint32_t CNTEN:1;
\r
2200 vuint32_t RTCIE:1;
\r
2201 vuint32_t FRZEN:1;
\r
2202 vuint32_t ROVREN:1;
\r
2203 vuint32_t RTCVAL:12;
\r
2204 vuint32_t APIEN:1;
\r
2205 vuint32_t APIIE:1;
\r
2206 vuint32_t CLKSEL:2;
\r
2207 vuint32_t DIV512EN:1;
\r
2208 vuint32_t DIV32EN:1;
\r
2209 vuint32_t APIVAL:10;
\r
2213 union { /* RTC Status (Base+0x0008) */
\r
2221 vuint32_t ROVRF:1;
\r
2226 union { /* RTC Counter (Base+0x000C) */
\r
2229 vuint32_t RTCCNT:32;
\r
2233 }; /* end of RTC_tag */
\r
2235 /****************************************************************************/
\r
2236 /* MODULE : SIU Lite (tagged as SIU for compatibility) */
\r
2237 /****************************************************************************/
\r
2240 vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
\r
2242 union { /* MCU ID1 (Base+0x0004) */
\r
2245 vuint32_t PARTNUM:16;
\r
2249 vuint32_t MAJOR_MASK:4;
\r
2250 vuint32_t MINOR_MASK:4;
\r
2254 union { /* MCU ID2 (Base+0x0008) */
\r
2258 vuint32_t FLASH_SIZE_1:4;
\r
2259 vuint32_t FLASH_SIZE_2:4;
\r
2261 vuint32_t PARTNUM:8;
\r
2269 vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
\r
2271 union { /* Interrupt Status Flag (Base+0x0014)*/
\r
2275 vuint32_t EIF23:1;
\r
2276 vuint32_t EIF22:1;
\r
2277 vuint32_t EIF21:1;
\r
2278 vuint32_t EIF20:1;
\r
2279 vuint32_t EIF19:1;
\r
2280 vuint32_t EIF18:1;
\r
2281 vuint32_t EIF17:1;
\r
2282 vuint32_t EIF16:1;
\r
2283 vuint32_t EIF15:1;
\r
2284 vuint32_t EIF14:1;
\r
2285 vuint32_t EIF13:1;
\r
2286 vuint32_t EIF12:1;
\r
2287 vuint32_t EIF11:1;
\r
2288 vuint32_t EIF10:1;
\r
2302 union { /* Interrupt Request Enable (Base+0x0018) */
\r
2306 vuint32_t IRE23:1;
\r
2307 vuint32_t IRE22:1;
\r
2308 vuint32_t IRE21:1;
\r
2309 vuint32_t IRE20:1;
\r
2310 vuint32_t IRE19:1;
\r
2311 vuint32_t IRE18:1;
\r
2312 vuint32_t IRE17:1;
\r
2313 vuint32_t IRE16:1;
\r
2314 vuint32_t IRE15:1;
\r
2315 vuint32_t IRE14:1;
\r
2316 vuint32_t IRE13:1;
\r
2317 vuint32_t IRE12:1;
\r
2318 vuint32_t IRE11:1;
\r
2319 vuint32_t IRE10:1;
\r
2333 vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
\r
2335 union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
\r
2339 vuint32_t IREE23:1;
\r
2340 vuint32_t IREE22:1;
\r
2341 vuint32_t IREE21:1;
\r
2342 vuint32_t IREE20:1;
\r
2343 vuint32_t IREE19:1;
\r
2344 vuint32_t IREE18:1;
\r
2345 vuint32_t IREE17:1;
\r
2346 vuint32_t IREE16:1;
\r
2347 vuint32_t IREE15:1;
\r
2348 vuint32_t IREE14:1;
\r
2349 vuint32_t IREE13:1;
\r
2350 vuint32_t IREE12:1;
\r
2351 vuint32_t IREE11:1;
\r
2352 vuint32_t IREE10:1;
\r
2353 vuint32_t IREE9:1;
\r
2354 vuint32_t IREE8:1;
\r
2355 vuint32_t IREE7:1;
\r
2356 vuint32_t IREE6:1;
\r
2357 vuint32_t IREE5:1;
\r
2358 vuint32_t IREE4:1;
\r
2359 vuint32_t IREE3:1;
\r
2360 vuint32_t IREE2:1;
\r
2361 vuint32_t IREE1:1;
\r
2362 vuint32_t IREE0:1;
\r
2366 union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
\r
2370 vuint32_t IFEE23:1;
\r
2371 vuint32_t IFEE22:1;
\r
2372 vuint32_t IFEE21:1;
\r
2373 vuint32_t IFEE20:1;
\r
2374 vuint32_t IFEE19:1;
\r
2375 vuint32_t IFEE18:1;
\r
2376 vuint32_t IFEE17:1;
\r
2377 vuint32_t IFEE16:1;
\r
2378 vuint32_t IFEE15:1;
\r
2379 vuint32_t IFEE14:1;
\r
2380 vuint32_t IFEE13:1;
\r
2381 vuint32_t IFEE12:1;
\r
2382 vuint32_t IFEE11:1;
\r
2383 vuint32_t IFEE10:1;
\r
2384 vuint32_t IFEE9:1;
\r
2385 vuint32_t IFEE8:1;
\r
2386 vuint32_t IFEE7:1;
\r
2387 vuint32_t IFEE6:1;
\r
2388 vuint32_t IFEE5:1;
\r
2389 vuint32_t IFEE4:1;
\r
2390 vuint32_t IFEE3:1;
\r
2391 vuint32_t IFEE2:1;
\r
2392 vuint32_t IFEE1:1;
\r
2393 vuint32_t IFEE0:1;
\r
2397 union { /* Interrupt Filter Enable (Base+0x0030) */
\r
2401 vuint32_t IFE23:1;
\r
2402 vuint32_t IFE22:1;
\r
2403 vuint32_t IFE21:1;
\r
2404 vuint32_t IFE20:1;
\r
2405 vuint32_t IFE19:1;
\r
2406 vuint32_t IFE18:1;
\r
2407 vuint32_t IFE17:1;
\r
2408 vuint32_t IFE16:1;
\r
2409 vuint32_t IFE15:1;
\r
2410 vuint32_t IFE14:1;
\r
2411 vuint32_t IFE13:1;
\r
2412 vuint32_t IFE12:1;
\r
2413 vuint32_t IFE11:1;
\r
2414 vuint32_t IFE10:1;
\r
2428 vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
\r
2430 union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/
\r
2449 vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */
\r
2451 union { /* Pad Selection for Mux Input (0x0500-0x53C) */
\r
2455 vuint8_t PADSEL:4;
\r
2459 vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */
\r
2461 union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */
\r
2469 vuint8_t SIU_reserved6[348]; /*Reserved 348 Bytes (Base+0x06A4-0x07FF) */
\r
2471 union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */
\r
2479 vuint8_t SIU_reserved7[860]; /*Reserved 860 Bytes (Base+0x08A4-0x0BFF) */
\r
2481 union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */
\r
2484 vuint32_t PPD0:32;
\r
2488 vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */
\r
2490 union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */
\r
2493 vuint32_t PPDI:32;
\r
2497 vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */
\r
2499 union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */
\r
2502 vuint32_t MASK:16;
\r
2503 vuint32_t MPPDO:16;
\r
2507 vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/
\r
2509 union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
\r
2513 vuint32_t MAXCNT:4;
\r
2517 vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/
\r
2519 union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
\r
2527 vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/
\r
2529 }; /* end of SIU_tag */
\r
2530 /****************************************************************************/
\r
2531 /* MODULE : SSCM */
\r
2532 /****************************************************************************/
\r
2535 union { /* Status (Base+0x0000) */
\r
2541 vuint16_t BMODE:3;
\r
2548 union { /* System Memory Configuration (Base+0x002) */
\r
2559 vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
\r
2561 union { /* Error Configuration (Base+0x0006) */
\r
2570 union { /* Debug Status Port (Base+0x0008) */
\r
2574 vuint16_t DEBUG_MODE:3;
\r
2578 vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
\r
2580 union { /* Password Comparison High Word (Base+0x000C) */
\r
2583 vuint32_t PWD_HI:32;
\r
2587 union { /* Password Comparison Low Word (Base+0x0010)*/
\r
2590 vuint32_t PWD_LO:32;
\r
2594 }; /* end of SSCM_tag */
\r
2595 /****************************************************************************/
\r
2596 /* MODULE : STM */
\r
2597 /****************************************************************************/
\r
2598 struct STM_CHANNEL_tag{
\r
2600 union { /* STM Channel Control 0..3 */
\r
2608 union { /* STM Channel Interrupt 0..3 */
\r
2616 union { /* STM Channel Compare 0..3 */
\r
2623 vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */
\r
2625 }; /* end of STM_CHANNEL_tag */
\r
2630 union { /* STM Control (Base+0x0000) */
\r
2641 union { /* STM Count (Base+0x0004) */
\r
2645 vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
\r
2647 struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
\r
2649 }; /* end of STM_tag */
\r
2650 /****************************************************************************/
\r
2651 /* MODULE : SWT */
\r
2652 /****************************************************************************/
\r
2655 union { /* SWT Control (Base+0x0000) */
\r
2680 union { /* SWT Interrupt (Base+0x0004) */
\r
2688 union { /* SWT Time-Out (Base+0x0008) */
\r
2695 union { /* SWT Window (Base+0x000C) */
\r
2702 union { /* SWT Service (Base+0x0010) */
\r
2710 union { /* SWT Counter Output (Base+0x0014) */
\r
2717 }; /* end of SWT_tag */
\r
2718 /****************************************************************************/
\r
2719 /* MODULE : WKUP */
\r
2720 /****************************************************************************/
\r
2723 union { /* NMI Status Flag (Base+0x0000) */
\r
2726 vuint32_t NIF0:1;
\r
2727 vuint32_t NOVF0:1;
\r
2732 vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
\r
2734 union { /* NMI Configuration (Base+0x0008) */
\r
2737 vuint32_t NLOCK0:1;
\r
2738 vuint32_t NDSS0:2;
\r
2739 vuint32_t NWRE0:1;
\r
2741 vuint32_t NREE0:1;
\r
2742 vuint32_t NFEE0:1;
\r
2748 vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
\r
2750 union { /* Wakeup/Interrup status flag (Base+0x0014) */
\r
2758 union { /* Interrupt Request Enable (Base+0x0018) */
\r
2762 vuint32_t EIRE:29;
\r
2766 union { /* Wakeup Request Enable (Base+0x001C) */
\r
2774 vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
\r
2776 union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
\r
2780 vuint32_t IREE:29;
\r
2784 union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
\r
2788 vuint32_t IFEE:29;
\r
2792 union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
\r
2800 union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
\r
2804 vuint32_t IPUE:29;
\r
2806 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
\r
2808 vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
\r
2810 }; /* end of WKUP_tag */
\r
2811 /****************************************************************************/
\r
2812 /* MODULE : LINFLEX */
\r
2813 /****************************************************************************/
\r
2814 struct LINFLEX_tag {
\r
2816 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
\r
2831 vuint32_t SLEEP:1;
\r
2836 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
\r
2850 vuint32_t DBFIE:1;
\r
2851 vuint32_t DBEIE:1;
\r
2858 union { /* LINFLEX LIN Status (Base+0x0008) */
\r
2877 union { /* LINFLEX LIN Error Status (Base+0x000C) */
\r
2887 vuint32_t IDPEF:1;
\r
2895 union { /* LINFLEX UART Mode Control (Base+0x0010) */
\r
2913 union { /* LINFLEX UART Mode Status (Base+0x0014) */
\r
2919 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
\r
2932 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
\r
2944 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
\r
2953 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
\r
2963 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
\r
2967 vuint32_t DIV_F:4;
\r
2971 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
\r
2975 vuint32_t DIV_M:13;
\r
2979 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
\r
2987 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
\r
3002 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
\r
3014 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
\r
3017 vuint32_t DATA3:8;
\r
3018 vuint32_t DATA2:8;
\r
3019 vuint32_t DATA1:8;
\r
3020 vuint32_t DATA0:8;
\r
3024 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
\r
3027 vuint32_t DATA7:8;
\r
3028 vuint32_t DATA6:8;
\r
3029 vuint32_t DATA5:8;
\r
3030 vuint32_t DATA4:8;
\r
3034 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
\r
3042 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
\r
3050 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
\r
3058 union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
\r
3062 vuint32_t:3; /* for LINflexD no reseve here*/
\r
3063 vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */
\r
3072 }; /* end of LINFLEX_tag */
\r
3075 /****************************************************************************/
\r
3076 /* MODULE : LINFLEXD0 */
\r
3077 /****************************************************************************/
\r
3078 struct LINFLEXD0_tag {
\r
3080 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
\r
3095 vuint32_t SLEEP:1;
\r
3100 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
\r
3114 vuint32_t DBFIE:1;
\r
3115 vuint32_t DBEIE:1;
\r
3122 union { /* LINFLEX LIN Status (Base+0x0008) */
\r
3141 union { /* LINFLEX LIN Error Status (Base+0x000C) */
\r
3151 vuint32_t IDPEF:1;
\r
3159 union { /* LINFLEX UART Mode Control (Base+0x0010) */
\r
3177 union { /* LINFLEX UART Mode Status (Base+0x0014) */
\r
3183 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
\r
3196 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
\r
3208 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
\r
3217 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
\r
3227 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
\r
3231 vuint32_t DIV_F:4;
\r
3235 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
\r
3239 vuint32_t DIV_M:13;
\r
3243 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
\r
3251 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
\r
3266 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
\r
3278 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
\r
3281 vuint32_t DATA3:8;
\r
3282 vuint32_t DATA2:8;
\r
3283 vuint32_t DATA1:8;
\r
3284 vuint32_t DATA0:8;
\r
3288 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
\r
3291 vuint32_t DATA7:8;
\r
3292 vuint32_t DATA6:8;
\r
3293 vuint32_t DATA5:8;
\r
3294 vuint32_t DATA4:8;
\r
3298 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
\r
3306 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
\r
3314 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
\r
3322 union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
\r
3334 union { /* LINFLEX Global Counter (+0x008C) */
\r
3338 vuint32_t TDFBM:1;
\r
3339 vuint32_t RDFBM:1;
\r
3340 vuint32_t TDLIS:1;
\r
3341 vuint32_t RDLIS:1;
\r
3347 union { /* LINFLEX UART preset timeout (+0x0090) */
\r
3355 union { /* LINFLEX UART current timeout (+0x0094) */
\r
3363 union { /* LINFLEX DMA Tx Enable (+0x0098) */
\r
3367 vuint32_t DTE15:1;
\r
3368 vuint32_t DTE14:1;
\r
3369 vuint32_t DTE13:1;
\r
3370 vuint32_t DTE12:1;
\r
3371 vuint32_t DTE11:1;
\r
3372 vuint32_t DTE10:1;
\r
3386 union { /* LINFLEX DMA RX Enable (+0x009C) */
\r
3390 vuint32_t DRE15:1;
\r
3391 vuint32_t DRE14:1;
\r
3392 vuint32_t DRE13:1;
\r
3393 vuint32_t DRE12:1;
\r
3394 vuint32_t DRE11:1;
\r
3395 vuint32_t DRE10:1;
\r
3408 }; /* end of LINFLEXD0_tag */
\r
3409 /****************************************************************************/
\r
3410 /* MODULE : LINFLEXD1 */
\r
3411 /****************************************************************************/
\r
3412 struct LINFLEXD1_tag {
\r
3414 union { /* LINFLEX LIN Control 1 (Base+0x0000) */
\r
3429 vuint32_t SLEEP:1;
\r
3434 union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
\r
3448 vuint32_t DBFIE:1;
\r
3449 vuint32_t DBEIE:1;
\r
3456 union { /* LINFLEX LIN Status (Base+0x0008) */
\r
3475 union { /* LINFLEX LIN Error Status (Base+0x000C) */
\r
3485 vuint32_t IDPEF:1;
\r
3493 union { /* LINFLEX UART Mode Control (Base+0x0010) */
\r
3511 union { /* LINFLEX UART Mode Status (Base+0x0014) */
\r
3517 vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
\r
3530 union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
\r
3542 union { /* LINFLEX LIN Output Compare (Base+0x001C) */
\r
3551 union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
\r
3561 union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
\r
3565 vuint32_t DIV_F:4;
\r
3569 union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
\r
3573 vuint32_t DIV_M:13;
\r
3577 union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
\r
3585 union { /* LINFLEX LIN Control 2 (Base+0x0030) */
\r
3600 union { /* LINFLEX Buffer Identifier (Base+0x0034) */
\r
3612 union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
\r
3615 vuint32_t DATA3:8;
\r
3616 vuint32_t DATA2:8;
\r
3617 vuint32_t DATA1:8;
\r
3618 vuint32_t DATA0:8;
\r
3622 union { /* LINFLEX Buffer Data MSB (Base+0x003C */
\r
3625 vuint32_t DATA7:8;
\r
3626 vuint32_t DATA6:8;
\r
3627 vuint32_t DATA5:8;
\r
3628 vuint32_t DATA4:8;
\r
3632 union { /* LINFLEX Identifier Filter Enable (+0x0040) */
\r
3640 union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
\r
3648 union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
\r
3656 /* No IFCR registers on LinFlexD_1 */
\r
3658 union { /* LINFLEX Global Counter (+0x004C) */
\r
3662 vuint32_t TDFBM:1;
\r
3663 vuint32_t RDFBM:1;
\r
3664 vuint32_t TDLIS:1;
\r
3665 vuint32_t RDLIS:1;
\r
3671 union { /* LINFLEX UART preset timeout (+0x0050) */
\r
3679 union { /* LINFLEX UART current timeout (+0x0054) */
\r
3687 union { /* LINFLEX DMA Tx Enable (+0x0058) */
\r
3691 vuint32_t DTE15:1;
\r
3692 vuint32_t DTE14:1;
\r
3693 vuint32_t DTE13:1;
\r
3694 vuint32_t DTE12:1;
\r
3695 vuint32_t DTE11:1;
\r
3696 vuint32_t DTE10:1;
\r
3710 union { /* LINFLEX DMA RX Enable (+0x005C) */
\r
3714 vuint32_t DRE15:1;
\r
3715 vuint32_t DRE14:1;
\r
3716 vuint32_t DRE13:1;
\r
3717 vuint32_t DRE12:1;
\r
3718 vuint32_t DRE11:1;
\r
3719 vuint32_t DRE10:1;
\r
3732 }; /* end of LINFLEXD1_tag */
\r
3734 /****************************************************************************/
\r
3736 /****************************************************************************/
\r
3739 union { /* Global Status (Base+0x0000) */
\r
3742 vuint32_t S_CURRENTMODE:4;
\r
3743 vuint32_t S_MTRANS:1;
\r
3746 vuint32_t S_PDO:1;
\r
3748 vuint32_t S_MVR:1;
\r
3749 vuint32_t S_DFLA:2;
\r
3750 vuint32_t S_CFLA:2;
\r
3752 vuint32_t S_FMPLL:1;
\r
3753 vuint32_t S_FXOSC:1;
\r
3754 vuint32_t S_FIRC:1;
\r
3755 vuint32_t S_SYSCLK:4;
\r
3759 union { /* Mode Control (Base+0x004) */
\r
3762 vuint32_t TARGET_MODE:4;
\r
3768 union { /* Mode Enable (Base+0x0008) */
\r
3773 vuint32_t STANDBY0:1;
\r
3775 vuint32_t STOP0:1;
\r
3777 vuint32_t HALT0:1;
\r
3785 vuint32_t RESET:1;
\r
3789 union { /* Interrupt Status (Base+0x000C) */
\r
3793 vuint32_t I_ICONF:1;
\r
3794 vuint32_t I_IMODE:1;
\r
3795 vuint32_t I_SAFE:1;
\r
3796 vuint32_t I_MTC:1;
\r
3800 union { /* Interrupt Mask (Base+0x0010) */
\r
3804 vuint32_t M_ICONF:1;
\r
3805 vuint32_t M_IMODE:1;
\r
3806 vuint32_t M_SAFE:1;
\r
3807 vuint32_t M_MTC:1;
\r
3811 union { /* Invalid Mode Transition Status (Base+0x0014) */
\r
3815 vuint32_t S_MTI:1;
\r
3816 vuint32_t S_MRI:1;
\r
3817 vuint32_t S_DMA:1;
\r
3818 vuint32_t S_NMA:1;
\r
3819 vuint32_t S_SEA:1;
\r
3823 union { /* Debug Mode Transition Status (Base+0x0018) */
\r
3827 vuint32_t MPH_BUSY:1;
\r
3829 vuint32_t PMC_PROG:1;
\r
3830 vuint32_t CORE_DBG:1;
\r
3834 vuint32_t FMPLL_SC:1;
\r
3835 vuint32_t FXOSC_SC:1;
\r
3836 vuint32_t FIRC_SC:1;
\r
3838 vuint32_t SYSCLK_SW:1;
\r
3839 vuint32_t DFLASH_SC:1;
\r
3840 vuint32_t CFLASH_SC:1;
\r
3841 vuint32_t CDP_PRPH_0_143:1;
\r
3843 vuint32_t CDP_PRPH_96_127:1;
\r
3844 vuint32_t CDP_PRPH_64_95:1;
\r
3845 vuint32_t CDP_PRPH_32_63:1;
\r
3846 vuint32_t CDP_PRPH_0_31:1;
\r
3850 vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
\r
3852 union { /* Reset Mode Configuration (Base+0x0020) */
\r
3858 vuint32_t MVRON:1;
\r
3859 vuint32_t DFLAON:2;
\r
3860 vuint32_t CFLAON:2;
\r
3862 vuint32_t FMPLLON:1;
\r
3863 vuint32_t FXOSC0ON:1;
\r
3864 vuint32_t FIRCON:1;
\r
3865 vuint32_t SYSCLK:4;
\r
3869 union { /* Test Mode Configuration (Base+0x0024) */
\r
3875 vuint32_t MVRON:1;
\r
3876 vuint32_t DFLAON:2;
\r
3877 vuint32_t CFLAON:2;
\r
3879 vuint32_t FMPLLON:1;
\r
3880 vuint32_t FXOSC0ON:1;
\r
3881 vuint32_t FIRCON:1;
\r
3882 vuint32_t SYSCLK:4;
\r
3886 union { /* Safe Mode Configuration (Base+0x0028) */
\r
3892 vuint32_t MVRON:1;
\r
3893 vuint32_t DFLAON:2;
\r
3894 vuint32_t CFLAON:2;
\r
3896 vuint32_t FMPLLON:1;
\r
3897 vuint32_t FXOSC0ON:1;
\r
3898 vuint32_t FIRCON:1;
\r
3899 vuint32_t SYSCLK:4;
\r
3903 union { /* DRUN Mode Configuration (Base+0x002C) */
\r
3909 vuint32_t MVRON:1;
\r
3910 vuint32_t DFLAON:2;
\r
3911 vuint32_t CFLAON:2;
\r
3913 vuint32_t FMPLLON:1;
\r
3914 vuint32_t FXOSCON:1;
\r
3915 vuint32_t FIRCON:1;
\r
3916 vuint32_t SYSCLK:4;
\r
3920 union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
\r
3926 vuint32_t MVRON:1;
\r
3927 vuint32_t DFLAON:2;
\r
3928 vuint32_t CFLAON:2;
\r
3930 vuint32_t FMPLLON:1;
\r
3931 vuint32_t FXOSC0ON:1;
\r
3932 vuint32_t FIRCON:1;
\r
3933 vuint32_t SYSCLK:4;
\r
3937 union { /* HALT0 Mode Configuration (Base+0x0040) */
\r
3943 vuint32_t MVRON:1;
\r
3944 vuint32_t DFLAON:2;
\r
3945 vuint32_t CFLAON:2;
\r
3947 vuint32_t FMPLLON:1;
\r
3948 vuint32_t FXOSC0ON:1;
\r
3949 vuint32_t FIRCON:1;
\r
3950 vuint32_t SYSCLK:4;
\r
3954 vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
\r
3956 union { /* STOP0 Mode Configuration (Base+0x0048) */
\r
3962 vuint32_t MVRON:1;
\r
3963 vuint32_t DFLAON:2;
\r
3964 vuint32_t CFLAON:2;
\r
3966 vuint32_t FMPLLON:1;
\r
3967 vuint32_t FXOSC0ON:1;
\r
3968 vuint32_t FIRCON:1;
\r
3969 vuint32_t SYSCLK:4;
\r
3973 vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
\r
3975 union { /* STANDBY0 Mode Configuration (Base+0x0054) */
\r
3981 vuint32_t MVRON:1;
\r
3982 vuint32_t DFLAON:2;
\r
3983 vuint32_t CFLAON:2;
\r
3985 vuint32_t FMPLLON:1;
\r
3986 vuint32_t FXOSC0ON:1;
\r
3987 vuint32_t FIRCON:1;
\r
3988 vuint32_t SYSCLK:4;
\r
3992 vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
\r
3996 struct { /* Peripheral Status 0 (Base+0x0060) */
\r
3998 vuint32_t S_DMA_CH_MUX:1;
\r
4000 vuint32_t S_FLEXCAN5:1;
\r
4001 vuint32_t S_FLEXCAN4:1;
\r
4002 vuint32_t S_FLEXCAN3:1;
\r
4003 vuint32_t S_FLEXCAN2:1;
\r
4004 vuint32_t S_FLEXCAN1:1;
\r
4005 vuint32_t S_FLEXCAN0:1;
\r
4007 vuint32_t :1; /* S_LINFLEX9:1; // not present on B1M */
\r
4008 vuint32_t :1; /* S_LINFLEX8:1; // not present on B1M */
\r
4010 vuint32_t S_DSPI5:1;
\r
4011 vuint32_t S_DSPI4:1;
\r
4012 vuint32_t S_DSPI3:1;
\r
4013 vuint32_t S_DSPI2:1;
\r
4014 vuint32_t S_DSPI1:1;
\r
4015 vuint32_t S_DSPI0:1;
\r
4020 union { /* Peripheral Status 1 (Base+0x0064)*/
\r
4024 vuint32_t S_CANSAMPLER:1;
\r
4026 vuint32_t S_CTUL:1;
\r
4028 vuint32_t S_LINFLEX7:1;
\r
4029 vuint32_t S_LINFLEX6:1;
\r
4030 vuint32_t S_LINFLEX5:1;
\r
4031 vuint32_t S_LINFLEX4:1;
\r
4032 vuint32_t S_LINFLEX3:1;
\r
4033 vuint32_t S_LINFLEX2:1;
\r
4034 vuint32_t S_LINFLEX1:1;
\r
4035 vuint32_t S_LINFLEX0:1;
\r
4037 vuint32_t S_I2C0:1;
\r
4039 vuint32_t S_ADC1:1;
\r
4040 vuint32_t S_ADC0:1;
\r
4044 union { /* Peripheral Status 2 (Base+0x0068) */
\r
4048 vuint32_t S_PIT_RTI:1;
\r
4049 vuint32_t S_RTC_API:1;
\r
4051 vuint32_t S_EMIOS1:1;
\r
4052 vuint32_t S_EMIOS0:1;
\r
4054 vuint32_t S_WKPU:1;
\r
4055 vuint32_t S_SIUL:1;
\r
4060 union { /* Peripheral Status 3 (Base+0x006C) */
\r
4064 vuint32_t S_CMU:1;
\r
4069 vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
\r
4071 union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
\r
4082 vuint32_t RESET:1;
\r
4086 union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
\r
4090 vuint32_t STANDBY0:1;
\r
4092 vuint32_t STOP0:1;
\r
4094 vuint32_t HALT0:1;
\r
4100 /* Note on PCTL registers: There are only some PCTL implemented in */
\r
4101 /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */
\r
4102 /* are defined as an array (ie ME.PCTL[x].R). This means you have */
\r
4103 /* to be careful when addressing these registers in order not to */
\r
4104 /* access a PCTL that is not implemented. Following are available: */
\r
4105 /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 51, 50, 49,48, */
\r
4106 /* 44, 33, 32, 23, 21-16, 13, 12, 9-4 */
\r
4108 union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */
\r
4113 vuint8_t LP_CFG:3;
\r
4114 vuint8_t RUN_CFG:3;
\r
4118 }; /* end of ME_tag */
\r
4120 /****************************************************************************/
\r
4121 /* MODULE : CGM */
\r
4122 /****************************************************************************/
\r
4125 The "CGM" has fairly wide coverage and essentially includes everything in
\r
4127 chapter 9 of the Bolero Reference Manual:
\r
4129 Base Address | Clock Sources
\r
4131 -----------------------------
\r
4133 0xC3FE0000 | FXOSC_CTL
\r
4135 0xC3FE0040 | SXOSC_CTL
\r
4137 0xC3FE0060 | FIRC_CTL
\r
4139 0xC3FE0080 | SIRC_CTL
\r
4141 0xC3FE00A0 | FMPLL
\r
4143 0xC3FE00C0 | CGM Block 1
\r
4147 0xC3FE0120 | CGM Block 2
\r
4151 In this header file, "Base" referrs to the 1st address, 0xC3FE_0000
\r
4154 /* FXOSC - 0xC3FE_0000*/
\r
4155 union { /* Fast OSC Control (Base+0x0000) */
\r
4158 vuint32_t OSCBYP:1;
\r
4161 vuint32_t M_OSC:1;
\r
4163 vuint32_t OSCDIV:5;
\r
4164 vuint32_t I_OSC:1;
\r
4170 /* Reserved Space between end of FXOSC and start SXOSC */
\r
4171 vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
\r
4174 /* SXOSC - 0xC3FE_0040*/
\r
4175 union { /* Slow Osc Control (Base+0x0040) */
\r
4178 vuint32_t OSCBYP:1;
\r
4181 vuint32_t M_OSC:1;
\r
4183 vuint32_t OSCDIV:5;
\r
4184 vuint32_t I_OSC:1;
\r
4186 vuint32_t S_OSC:1;
\r
4187 vuint32_t OSCON:1;
\r
4192 /* Reserved space between end of SXOSC and start of FIRC */
\r
4193 vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
\r
4196 /* FIRC - 0xC3FE_0060 */
\r
4197 union { /* Fast IRC Control (Base+0x0060) */
\r
4201 vuint32_t RCTRIM:6;
\r
4203 vuint32_t RCDIV:5;
\r
4205 vuint32_t FIRCON_STDBY:1;
\r
4211 /* Reserved space between end of FIRC and start of SIRC */
\r
4212 vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
\r
4215 /* SIRC - 0xC3FE_0080 */
\r
4216 union { /* Slow IRC Control (Base+0x0080) */
\r
4220 vuint32_t SIRCTRIM:5;
\r
4222 vuint32_t SIRCDIV:5;
\r
4224 vuint32_t S_SIRC:1;
\r
4226 vuint32_t SIRCON_STDBY:1;
\r
4231 /* Reserved space between end of SIRC and start of FMPLL */
\r
4232 vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
\r
4235 /* FMPLL - 0xC3FE_00A0 */
\r
4236 union { /* FMPLL Control (Base+0x00A0) */
\r
4245 vuint32_t EN_PLL_SW:1;
\r
4247 vuint32_t UNLOCK_ONCE:1;
\r
4249 vuint32_t I_LOCK:1;
\r
4250 vuint32_t S_LOCK:1;
\r
4251 vuint32_t PLL_FAIL_MASK:1;
\r
4252 vuint32_t PLL_FAIL_FLAG:1;
\r
4257 union { /* FMPLL Modulation (Base+0x00A4) */
\r
4260 vuint32_t STRB_BYPASS:1;
\r
4262 vuint32_t SPRD_SEL:1;
\r
4263 vuint32_t MOD_PERIOD:13;
\r
4264 vuint32_t FM_EN:1;
\r
4265 vuint32_t INC_STEP:15;
\r
4270 /* Reserved space between end of FMPLL and start of CGM Block 1 */
\r
4271 vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */
\r
4273 /* CMU - 0xC3FE_0100 */
\r
4274 union { /* CMU Control Status (Base+0x0100) */
\r
4280 vuint32_t CLKSEL1:2;
\r
4282 vuint32_t RCDIV:2;
\r
4283 vuint32_t CME_A:1;
\r
4287 union { /* CMU Frequency Display (Base+0x0104) */
\r
4295 union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
\r
4299 vuint32_t HFREF:12;
\r
4303 union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
\r
4307 vuint32_t LFREF:12;
\r
4311 union { /* CMU Interrupt Status (Base+0x0110) */
\r
4315 vuint32_t FHHI:1; // *_A not present in RM
\r
4316 vuint32_t FLLI:1; // *_A not present in RM
\r
4321 /* Reserved space where IMR was previously positioned */
\r
4322 vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
\r
4324 union { /* CMU Measurement Duration (Base+0x0118) */
\r
4333 /* Reserved space between end of CMU and start of CGM Block 2 */
\r
4334 vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */
\r
4336 union { /* GCM Output Clock Enable (Base+0x0370) */
\r
4344 union { /* CGM Output Clock Division Sel (Base+0x0374) */
\r
4348 vuint32_t SELDIV:2;
\r
4349 vuint32_t SELCTL:4;
\r
4354 union { /* CGM System Clock Select Status (Base+0x0378) */
\r
4358 vuint32_t SELSTAT:4;
\r
4363 union { /* CGM Sys Clk Div Config 0.2 (0x037C-0x037E) */
\r
4372 // vuint8_t CGM_reserved7[15489]; /*Reserved 1 byte (Base+0x037F - 0x3FFF) */
\r
4374 }; /* end of CGM_tag */
\r
4376 /****************************************************************************/
\r
4377 /* MODULE : RGM base address - 0xC3FE_4000 */
\r
4378 /****************************************************************************/
\r
4381 union { /* Functional Event Status (Base+0x0000) */
\r
4384 vuint16_t F_EXR:1;
\r
4386 vuint16_t F_FLASH:1;
\r
4387 vuint16_t F_LVD45:1;
\r
4388 vuint16_t F_CMU_FHL:1;
\r
4389 vuint16_t F_CMU_OLR:1;
\r
4390 vuint16_t F_FMPLL:1;
\r
4391 vuint16_t F_CHKSTOP:1;
\r
4392 vuint16_t F_SOFT:1;
\r
4393 vuint16_t F_CORE:1;
\r
4394 vuint16_t F_JTAG:1;
\r
4398 union { /* Destructive Event Status (Base+0x0002) */
\r
4401 vuint16_t F_POR:1;
\r
4403 vuint16_t F_LVD27_VREG:1;
\r
4404 vuint16_t F_LVD27:1;
\r
4405 vuint16_t F_SWT:1;
\r
4406 vuint16_t F_LVD12_PD1:1;
\r
4407 vuint16_t F_LVD12_PD0:1;
\r
4411 union { /* Functional Event Reset Disable (+0x0004) */
\r
4414 vuint16_t D_EXR:1;
\r
4416 vuint16_t D_FLASH:1;
\r
4417 vuint16_t D_LVD45:1;
\r
4418 vuint16_t D_CMU_FHL:1;
\r
4419 vuint16_t D_CMU_OLR:1;
\r
4420 vuint16_t D_FMPLL:1;
\r
4421 vuint16_t D_CHKSTOP:1;
\r
4422 vuint16_t D_SOFT:1;
\r
4423 vuint16_t D_CORE:1;
\r
4424 vuint16_t D_JTAG:1;
\r
4428 union { /* Destructive Event Reset Disable (Base+0x0006)*/
\r
4432 vuint16_t D_LVD27_VREG:1;
\r
4433 vuint16_t D_LVD27:1;
\r
4434 vuint16_t D_SWT:1;
\r
4435 vuint16_t D_LVD12_PD1:1;
\r
4436 vuint16_t D_LVD12_PD0:1;
\r
4440 vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
\r
4442 union { /* Functional Event Alt Request (Base+0x0010) */
\r
4445 vuint16_t AR_EXR:1;
\r
4447 vuint16_t AR_FLASH:1;
\r
4448 vuint16_t AR_LVD45:1;
\r
4449 vuint16_t AR_CMU_FHL:1;
\r
4450 vuint16_t AR_CMU_OLR:1;
\r
4451 vuint16_t AR_FMPLL:1;
\r
4452 vuint16_t AR_CHKSTOP:1;
\r
4453 vuint16_t AR_SOFT:1;
\r
4454 vuint16_t AR_CORE:1;
\r
4455 vuint16_t AR_JTAG:1;
\r
4459 union { /* Destructive Event Alt Request (Base+0x0012) */
\r
4463 vuint16_t AR_LVD27_VREG:1;
\r
4464 vuint16_t AR_LVD27:1;
\r
4465 vuint16_t AR_SWT:1;
\r
4466 vuint16_t AR_LVD12_PD1:1;
\r
4467 vuint16_t AR_LVD12_PD0:1;
\r
4469 } DEAR; /* Destructive Event Alternate Request */
\r
4471 vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */
\r
4473 union { /* Functional Event Short Sequence (+0x0018) */
\r
4476 vuint16_t SS_EXR:1;
\r
4478 vuint16_t SS_FLASH:1;
\r
4479 vuint16_t SS_LVD45:1;
\r
4480 vuint16_t SS_CMU_FHL:1;
\r
4481 vuint16_t SS_CMU_OLR:1;
\r
4482 vuint16_t SS_FMPLL:1;
\r
4483 vuint16_t SS_CHKSTOP:1;
\r
4484 vuint16_t SS_SOFT:1;
\r
4485 vuint16_t SS_CORE:1;
\r
4486 vuint16_t SS_JTAG:1;
\r
4490 union { /* STANDBY reset sequence (Base+0x001A) */
\r
4494 vuint16_t BOOT_FROM_BKP_RAM:1;
\r
4499 union { /* Functional Bidirectional Reset En (+0x001C) */
\r
4502 vuint16_t BE_EXR:1;
\r
4504 vuint16_t BE_FLASH:1;
\r
4505 vuint16_t BE_LVD45:1;
\r
4506 vuint16_t BE_CMU_FHL:1;
\r
4507 vuint16_t BE_CMU_OLR:1;
\r
4508 vuint16_t BE_FMPLL:1;
\r
4509 vuint16_t BE_CHKSTOP:1;
\r
4510 vuint16_t BE_SOFT:1;
\r
4511 vuint16_t BE_CORE:1;
\r
4512 vuint16_t BE_JTAG:1;
\r
4516 }; /* end of RGM_tag */
\r
4517 /****************************************************************************/
\r
4518 /* MODULE : PCU (base address 0xC3FE_8000) */
\r
4519 /****************************************************************************/
\r
4522 union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
\r
4526 vuint32_t STBY0:1;
\r
4528 vuint32_t STOP0:1;
\r
4530 vuint32_t HALT0:1;
\r
4542 vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
\r
4544 union { /* PCU Power Domain Status (Base+0x0040) */
\r
4555 vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
\r
4558 /* Following register is from Voltage Regulators chapter of RM */
\r
4560 union { /* PCU Voltage Regulator Control (Base+0x0080) */
\r
4564 vuint32_t MASK_LVDHV5:1;
\r
4566 } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
\r
4568 }; /* end of PCU_tag */
\r
4570 /****************************************************************************/
\r
4571 /* MODULE : CTU Lite(base address - 0xFFE6_4000) */
\r
4572 /****************************************************************************/
\r
4575 // union { /* CTU Control Status Register (Base+0x0000)NOT PRESENT WITHIN RM*/
\r
4579 // vuint32_t TRGIEN:1;
\r
4580 // vuint32_t TRGI:1;
\r
4585 vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
\r
4587 union { /* Event Config 0..63 (Base+0x0030-0x012C) */
\r
4592 vuint32_t CLR_FLAG:1;
\r
4594 vuint32_t ADC_SEL:1;
\r
4596 vuint32_t CHANNEL_VALUE:7;
\r
4601 }; /* end of CTUL_tag */
\r
4603 /****************************************************************************/
\r
4604 /* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */
\r
4605 /****************************************************************************/
\r
4607 struct EMIOS_CHANNEL_tag{
\r
4609 union { /* Channel A Data (UCn Base+0x0000) */
\r
4617 union { /* Channel B Data (UCn Base+0x0004) */
\r
4625 union { /* Channel Counter (UCn Base+0x0008) */
\r
4633 union { /* Channel Control (UCn Base+0x000C) */
\r
4638 vuint32_t UCPRE:2;
\r
4639 vuint32_t UCPEN:1;
\r
4646 vuint32_t FORCMA:1;
\r
4647 vuint32_t FORCMB:1;
\r
4650 vuint32_t EDSEL:1;
\r
4651 vuint32_t EDPOL:1;
\r
4656 union { /* Channel Status (UCn Base+0x0010) */
\r
4664 vuint32_t UCOUT:1;
\r
4669 union { /* Alternate Channel A Data (UCn Base+0x0014) */
\r
4673 vuint32_t ALTA:16;
\r
4677 vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
\r
4679 }; /* end of EMIOS_CHANNEL_tag */
\r
4684 union { /* Module Configuration (Base+0x0000) */
\r
4692 vuint32_t GPREN:1;
\r
4699 union { /* Global Flag (Base+0x0004) */
\r
4737 union { /* Output Update Disable (Base+0x0008) */
\r
4775 union { /* Disable Channel (Base+0x000F) */
\r
4778 vuint32_t CHDIS31:1;
\r
4779 vuint32_t CHDIS30:1;
\r
4780 vuint32_t CHDIS29:1;
\r
4781 vuint32_t CHDIS28:1;
\r
4782 vuint32_t CHDIS27:1;
\r
4783 vuint32_t CHDIS26:1;
\r
4784 vuint32_t CHDIS25:1;
\r
4785 vuint32_t CHDIS24:1;
\r
4786 vuint32_t CHDIS23:1;
\r
4787 vuint32_t CHDIS22:1;
\r
4788 vuint32_t CHDIS21:1;
\r
4789 vuint32_t CHDIS20:1;
\r
4790 vuint32_t CHDIS19:1;
\r
4791 vuint32_t CHDIS18:1;
\r
4792 vuint32_t CHDIS17:1;
\r
4793 vuint32_t CHDIS16:1;
\r
4794 vuint32_t CHDIS15:1;
\r
4795 vuint32_t CHDIS14:1;
\r
4796 vuint32_t CHDIS13:1;
\r
4797 vuint32_t CHDIS12:1;
\r
4798 vuint32_t CHDIS11:1;
\r
4799 vuint32_t CHDIS10:1;
\r
4800 vuint32_t CHDIS9:1;
\r
4801 vuint32_t CHDIS8:1;
\r
4802 vuint32_t CHDIS7:1;
\r
4803 vuint32_t CHDIS6:1;
\r
4804 vuint32_t CHDIS5:1;
\r
4805 vuint32_t CHDIS4:1;
\r
4806 vuint32_t CHDIS3:1;
\r
4807 vuint32_t CHDIS2:1;
\r
4808 vuint32_t CHDIS1:1;
\r
4809 vuint32_t CHDIS0:1;
\r
4813 vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
\r
4815 struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
\r
4817 vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
\r
4819 }; /* end of EMIOS_tag */
\r
4821 /****************************************************************************/
\r
4822 /* MODULE : PIT (base address - 0xC3FF_FFFF) */
\r
4823 /****************************************************************************/
\r
4826 union { /* PIT Module Control (Base+0x0000) */
\r
4835 vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */
\r
4837 /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
\r
4840 union { /* PIT Timer Load Value (Offset+0x0000) */
\r
4847 union { /* PIT Current Timer Value (Offset+0x0004) */
\r
4854 union { /* PIT Timer Control (Offset+0x0008) */
\r
4863 union { /* PIT Timer Control (Offset+0x0008) */
\r
4871 }CH[8]; /* End of PIT Timer Channels */
\r
4873 }; /* end of PIT_tag */
\r
4874 /****************************************************************************/
\r
4875 /* MODULE : I2C (base address - 0xFFE3_0000) */
\r
4876 /****************************************************************************/
\r
4879 union { /* I2C Bus Address (Base+0x0000) */
\r
4887 union { /* I2C Bus Frequency Divider (Base+0x0001) */
\r
4894 union { /* I2C Bus Control (Base+0x0002) */
\r
4899 vuint8_t MS:1; /*different from RM for backward compatiblity MSSL in RM*/
\r
4908 union { /* I2C Bus Status (Base+0x0003) */
\r
4922 union { /* I2C Bus Data I/O (Base+0x0004) */
\r
4929 union { /* I2C Interrupt Configuration (Base+0x0005) */
\r
4937 vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */
\r
4939 }; /* end of i2c_tag */
\r
4940 /****************************************************************************/
\r
4941 /* MODULE : MPU (base address - 0xFFF1_0000) */
\r
4942 /****************************************************************************/
\r
4945 union { /* Control/Error Status (Base+0x0000) */
\r
4949 vuint32_t SPERR:3;
\r
4959 vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
\r
4962 union { /* Error Address Slave Port0 (Base+0x0010) */
\r
4965 vuint32_t EADDR:32;
\r
4969 union { /* Error Detail Slave Port0 (Base+0x0014) */
\r
4976 vuint32_t EATTR:3;
\r
4982 union { /* Error Address Slave Port1 (Base+0x0018) */
\r
4985 vuint32_t EADDR:32;
\r
4989 union { /* Error Detail Slave Port1 (Base+0x001C) */
\r
4996 vuint32_t EATTR:3;
\r
5002 union { /* Error Address Slave Port2 (Base+0x0020) */
\r
5005 vuint32_t EADDR:32;
\r
5009 union { /* Error Detail Slave Port2 (Base+0x0024) */
\r
5016 vuint32_t EATTR:3;
\r
5021 vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */
\r
5023 struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */
\r
5025 union { /* - Word 0 */
\r
5028 vuint32_t SRTADDR:27;
\r
5033 union { /* - Word 1 */
\r
5036 vuint32_t ENDADDR:27;
\r
5041 union { /* - Word 2 */
\r
5065 union { /* - Word 3 */
\r
5069 vuint32_t PIDMASK:8;
\r
5075 }RGD[8]; /* End of Region Descriptor Structure) */
\r
5077 vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */
\r
5079 union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */
\r
5103 vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */
\r
5105 }; /* end of MPU_tag */
\r
5106 /****************************************************************************/
\r
5107 /* MODULE : eDMA (base address - 0xFFF4_4000) */
\r
5108 /****************************************************************************/
\r
5110 /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */
\r
5111 struct EDMA_TCD_STD_tag {
\r
5113 vuint32_t SADDR; /* source address */
\r
5115 vuint16_t SMOD:5; /* source address modulo */
\r
5116 vuint16_t SSIZE:3; /* source transfer size */
\r
5117 vuint16_t DMOD:5; /* destination address modulo */
\r
5118 vuint16_t DSIZE:3; /* destination transfer size */
\r
5119 vint16_t SOFF; /* signed source address offset */
\r
5121 vuint32_t NBYTES; /* inner (?minor?) byte count */
\r
5123 vint32_t SLAST; /* last destination address adjustment, or scatter/gather address (if e_sg = 1) */
\r
5124 vuint32_t DADDR; /* destination address */
\r
5126 vuint16_t CITERE_LINK:1;
\r
5127 vuint16_t CITER:15;
\r
5129 vint16_t DOFF; /* signed destination address offset */
\r
5131 vint32_t DLAST_SGA;
\r
5133 vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
\r
5134 vuint16_t BITER:15;
\r
5136 vuint16_t BWC:2; /* bandwidth control */
\r
5137 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
\r
5138 vuint16_t DONE:1; /* channel done */
\r
5139 vuint16_t ACTIVE:1; /* channel active */
\r
5140 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
\r
5141 vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
5142 vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
5143 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
5144 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
5145 vuint16_t START:1; /* explicit channel start */
\r
5147 }; /* end of EDMA_TCD_STD_tag */
\r
5149 /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/
\r
5150 struct EDMA_TCD_CHLINK_tag {
\r
5152 vuint32_t SADDR; /* source address */
\r
5154 vuint16_t SMOD:5; /* source address modulo */
\r
5155 vuint16_t SSIZE:3; /* source transfer size */
\r
5156 vuint16_t DMOD:5; /* destination address modulo */
\r
5157 vuint16_t DSIZE:3; /* destination transfer size */
\r
5158 vint16_t SOFF; /* signed source address offset */
\r
5160 vuint32_t NBYTES; /* inner (?minor?) byte count */
\r
5162 vint32_t SLAST; /* last destination address adjustment, or
\r
5164 scatter/gather address (if e_sg = 1) */
\r
5165 vuint32_t DADDR; /* destination address */
\r
5167 vuint16_t CITERE_LINK:1;
\r
5168 vuint16_t CITERLINKCH:6;
\r
5169 vuint16_t CITER:9;
\r
5171 vint16_t DOFF; /* signed destination address offset */
\r
5173 vint32_t DLAST_SGA;
\r
5175 vuint16_t BITERE_LINK:1; /* beginning (?major?) iteration count */
\r
5176 vuint16_t BITERLINKCH:6;
\r
5177 vuint16_t BITER:9;
\r
5179 vuint16_t BWC:2; /* bandwidth control */
\r
5180 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
\r
5181 vuint16_t DONE:1; /* channel done */
\r
5182 vuint16_t ACTIVE:1; /* channel active */
\r
5183 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
\r
5184 vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
5185 vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
5186 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
5187 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
5188 vuint16_t START:1; /* explicit channel start */
\r
5190 }; /* end of EDMA_TCD_CHLINK_tag */
\r
5196 union { /* Control (Base+0x0000) */
\r
5203 vuint32_t GRP0PRI:2;
\r
5215 union { /* Error Status (Base+0x0004) */
\r
5221 vuint32_t ERRCHN:6;
\r
5233 vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/
\r
5235 union { /* Enable Request Low Ch15..0 (Base+0x000C) */
\r
5239 vuint32_t ERQ15:1;
\r
5240 vuint32_t ERQ14:1;
\r
5241 vuint32_t ERQ13:1;
\r
5242 vuint32_t ERQ12:1;
\r
5243 vuint32_t ERQ11:1;
\r
5244 vuint32_t ERQ10:1;
\r
5245 vuint32_t ERQ09:1;
\r
5246 vuint32_t ERQ08:1;
\r
5247 vuint32_t ERQ07:1;
\r
5248 vuint32_t ERQ06:1;
\r
5249 vuint32_t ERQ05:1;
\r
5250 vuint32_t ERQ04:1;
\r
5251 vuint32_t ERQ03:1;
\r
5252 vuint32_t ERQ02:1;
\r
5253 vuint32_t ERQ01:1;
\r
5254 vuint32_t ERQ00:1;
\r
5258 vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/
\r
5260 union { /* Enable Error Interrupt Low (Base+0x0014) */
\r
5264 vuint32_t EEI15:1;
\r
5265 vuint32_t EEI14:1;
\r
5266 vuint32_t EEI13:1;
\r
5267 vuint32_t EEI12:1;
\r
5268 vuint32_t EEI11:1;
\r
5269 vuint32_t EEI10:1;
\r
5270 vuint32_t EEI09:1;
\r
5271 vuint32_t EEI08:1;
\r
5272 vuint32_t EEI07:1;
\r
5273 vuint32_t EEI06:1;
\r
5274 vuint32_t EEI05:1;
\r
5275 vuint32_t EEI04:1;
\r
5276 vuint32_t EEI03:1;
\r
5277 vuint32_t EEI02:1;
\r
5278 vuint32_t EEI01:1;
\r
5279 vuint32_t EEI00:1;
\r
5283 union { /* DMA Set Enable Request (Base+0x0018) */
\r
5291 union { /* DMA Clear Enable Request (Base+0x0019) */
\r
5299 union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
\r
5307 union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
\r
5315 union { /* DMA Clear Interrupt Request (Base+0x001C) */
\r
5323 union { /* DMA Clear error (Base+0x001D) */
\r
5331 union { /* DMA Set Start Bit (Base+0x001E) */
\r
5339 union { /* DMA Clear Done Status Bit (Base+0x001F) */
\r
5347 vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/
\r
5349 union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */
\r
5353 vuint32_t INT15:1;
\r
5354 vuint32_t INT14:1;
\r
5355 vuint32_t INT13:1;
\r
5356 vuint32_t INT12:1;
\r
5357 vuint32_t INT11:1;
\r
5358 vuint32_t INT10:1;
\r
5359 vuint32_t INT09:1;
\r
5360 vuint32_t INT08:1;
\r
5361 vuint32_t INT07:1;
\r
5362 vuint32_t INT06:1;
\r
5363 vuint32_t INT05:1;
\r
5364 vuint32_t INT04:1;
\r
5365 vuint32_t INT03:1;
\r
5366 vuint32_t INT02:1;
\r
5367 vuint32_t INT01:1;
\r
5368 vuint32_t INT00:1;
\r
5372 vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/
\r
5374 union { /* DMA Error Low Ch15..0 (Base+0x002C)*/
\r
5378 vuint32_t ERR15:1;
\r
5379 vuint32_t ERR14:1;
\r
5380 vuint32_t ERR13:1;
\r
5381 vuint32_t ERR12:1;
\r
5382 vuint32_t ERR11:1;
\r
5383 vuint32_t ERR10:1;
\r
5384 vuint32_t ERR09:1;
\r
5385 vuint32_t ERR08:1;
\r
5386 vuint32_t ERR07:1;
\r
5387 vuint32_t ERR06:1;
\r
5388 vuint32_t ERR05:1;
\r
5389 vuint32_t ERR04:1;
\r
5390 vuint32_t ERR03:1;
\r
5391 vuint32_t ERR02:1;
\r
5392 vuint32_t ERR01:1;
\r
5393 vuint32_t ERR00:1;
\r
5397 vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/
\r
5399 union { /* DMA Hardware Request Stat Low (Base+0x0034) */
\r
5403 vuint32_t HRS15:1;
\r
5404 vuint32_t HRS14:1;
\r
5405 vuint32_t HRS13:1;
\r
5406 vuint32_t HRS12:1;
\r
5407 vuint32_t HRS11:1;
\r
5408 vuint32_t HRS10:1;
\r
5409 vuint32_t HRS09:1;
\r
5410 vuint32_t HRS08:1;
\r
5411 vuint32_t HRS07:1;
\r
5412 vuint32_t HRS06:1;
\r
5413 vuint32_t HRS05:1;
\r
5414 vuint32_t HRS04:1;
\r
5415 vuint32_t HRS03:1;
\r
5416 vuint32_t HRS02:1;
\r
5417 vuint32_t HRS01:1;
\r
5418 vuint32_t HRS00:1;
\r
5422 vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
\r
5424 union { /* Channel n Priority (Base+0x0100-0x010F)*/
\r
5429 vuint8_t GRPPRI:2;
\r
5434 vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */
\r
5436 /* Transfer Control Descriptors 0..16 (Base+0x1000-0x11E0) */
\r
5437 struct EDMA_TCD_STD_tag TCD[16];
\r
5439 /* or change to following if using channel linking */
\r
5440 /* Struct EDMA_TCD_CHLINK_tag TCD[16]; */
\r
5442 vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */
\r
5444 }; /* end of EDMA_tag */
\r
5445 /*************************************************************************/
\r
5446 /* MODULE : INTC (base address - 0xFFF4_8000) */
\r
5447 /*************************************************************************/
\r
5450 union { /* INTC Module Configuration (Base+0x0000) */
\r
5460 vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
\r
5462 union { /* INTC Current Priority (Base+0x0008) */
\r
5470 vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
\r
5472 union { /* INTC Interrupt Acknowledge (Base+0x0010) */
\r
5475 vuint32_t VTBA_PRC0:21;
\r
5476 vuint32_t INTVEC_PRC0:9;
\r
5481 vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
\r
5483 union { /* INTC End Of Interrupt (Base+0x0018) */
\r
5490 vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */
\r
5492 union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
\r
5501 vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
\r
5503 union { /* INTC Priority Select (Base+0x0040-0x0128) */
\r
5511 }; /* end of INTC_tag */
\r
5512 /****************************************************************************/
\r
5513 /* MODULE : DSPI */
\r
5514 /* Base Addresses: */
\r
5515 /* DSPI_0 - 0xFFF9_0000 */
\r
5516 /* DSPI_1 - 0xFFF9_4000 */
\r
5517 /* DSPI_2 - 0xFFF9_8000 */
\r
5518 /* DSPI_3 - 0xFFF9_C000 */
\r
5519 /* DSPI_4 - 0xFFFA_0000 */
\r
5520 /* DSPI_5 - 0xFFFA_4000 */
\r
5521 /****************************************************************************/
\r
5524 union { /* DSPI Module Configuraiton (Base+0x0000) */
\r
5528 vuint32_t CONT_SCKE:1;
\r
5529 vuint32_t DCONF:2;
\r
5532 vuint32_t PCSSE:1;
\r
5535 vuint32_t PCSIS5:1;
\r
5536 vuint32_t PCSIS4:1;
\r
5537 vuint32_t PCSIS3:1;
\r
5538 vuint32_t PCSIS2:1;
\r
5539 vuint32_t PCSIS1:1;
\r
5540 vuint32_t PCSIS0:1;
\r
5541 vuint32_t DOZE:1;
\r
5543 vuint32_t DIS_TXF:1;
\r
5544 vuint32_t DIS_RXF:1;
\r
5545 vuint32_t CLR_TXF:1;
\r
5546 vuint32_t CLR_RXF:1;
\r
5547 vuint32_t SMPL_PT:2;
\r
5553 vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
\r
5555 union { /* DSPI Transfer Count (Base+0x0008) */
\r
5558 vuint32_t TCNT:16;
\r
5563 union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
\r
5570 vuint32_t LSBFE:1;
\r
5571 vuint32_t PCSSCK:2;
\r
5575 vuint32_t CSSCK:4;
\r
5582 vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */
\r
5584 union { /* DSPI Status (Base+0x002C) */
\r
5588 vuint32_t TXRXS:1;
\r
5599 vuint32_t TXCTR:4;
\r
5600 vuint32_t TXNXTPTR:4;
\r
5601 vuint32_t RXCTR:4;
\r
5602 vuint32_t POPNXTPTR:4;
\r
5606 union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
\r
5609 vuint32_t TCFRE:1;
\r
5611 vuint32_t EOQFRE:1;
\r
5612 vuint32_t TFUFRE:1;
\r
5614 vuint32_t TFFFRE:1;
\r
5615 vuint32_t TFFFDIRS:1;
\r
5617 vuint32_t RFOFRE:1;
\r
5619 vuint32_t RFDFRE:1;
\r
5620 vuint32_t RFDFDIRS:1;
\r
5625 union { /* DSPI Push TX FIFO (Base+0x0034) */
\r
5631 vuint32_t CTCNT:1;
\r
5639 vuint32_t TXDATA:16;
\r
5643 union { /* DSPI Pop RX FIFO (Base+0x0038) */
\r
5647 vuint32_t RXDATA:16;
\r
5651 union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
\r
5654 vuint32_t TXCMD:16;
\r
5655 vuint32_t TXDATA:16;
\r
5659 vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
\r
5661 union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
\r
5665 vuint32_t RXDATA:16;
\r
5668 }; /* end of DSPI_tag */
\r
5669 /****************************************************************************/
\r
5670 /* MODULE : FlexCAN */
\r
5671 /* Base Addresses: */
\r
5672 /* FlexCAN_0 - 0xFFFC_0000 */
\r
5673 /* FlexCAN_1 - 0xFFFC_4000 */
\r
5674 /* FlexCAN_2 - 0xFFFC_8000 */
\r
5675 /* FlexCAN_3 - 0xFFFC_C000 */
\r
5676 /* FlexCAN_4 - 0xFFFD_0000 */
\r
5677 /* FlexCAN_5 - 0xFFFD_4000 */
\r
5678 /****************************************************************************/
\r
5679 struct FLEXCAN_BUF_t{
\r
5681 union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
\r
5690 vuint32_t LENGTH:4;
\r
5691 vuint32_t TIMESTAMP:16;
\r
5695 union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
\r
5699 vuint32_t STD_ID:11;
\r
5700 vuint32_t EXT_ID:18;
\r
5704 union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
\r
5705 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
\r
5706 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
\r
5707 vuint32_t W[2]; /* Data buffer in words (32 bits) */
\r
5708 vuint32_t R[2]; /* Data buffer in words (32 bits) */
\r
5711 }; /* end of FLEXCAN_BUF_t */
\r
5714 struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
\r
5716 union { /* RxFIFO Control & Status (Offset+0x0080) */
\r
5723 vuint32_t LENGTH:4;
\r
5724 vuint32_t TIMESTAMP:16;
\r
5728 union { /* RxFIFO Identifier (Offset+0x0084) */
\r
5732 vuint32_t STD_ID:11;
\r
5733 vuint32_t EXT_ID:18;
\r
5737 union { /* RxFIFO Data 0..7 (Offset+0x0088) */
\r
5738 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
\r
5739 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
\r
5740 vuint32_t W[2]; /* Data buffer in words (32 bits) */
\r
5741 vuint32_t R[2]; /* Data buffer in words (32 bits) */
\r
5744 vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
\r
5746 union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
\r
5750 }; /* end of FLEXCAN_RXFIFO_t */
\r
5753 struct FLEXCAN_tag{
\r
5755 union { /* FLEXCAN Module Configuration (Base+0x0000) */
\r
5762 vuint32_t NOTRDY:1;
\r
5763 vuint32_t WAKMSK:1;
\r
5764 vuint32_t SOFTRST:1;
\r
5765 vuint32_t FRZACK:1;
\r
5767 vuint32_t SLFWAK:1; /*not present in RM*/
\r
5768 vuint32_t WRNEN:1;
\r
5769 vuint32_t LPMACK:1;
\r
5770 vuint32_t WAKSRC:1;
\r
5771 vuint32_t DOZE:1; /*not present in RM*/
\r
5772 vuint32_t SRXDIS:1;
\r
5775 vuint32_t LPRIO_EN:1;
\r
5780 vuint32_t MAXMB:6;
\r
5784 union { /* FLEXCAN Control (Base+0x0004) */
\r
5787 vuint32_t PRESDIV:8;
\r
5789 vuint32_t PSEG1:3;
\r
5790 vuint32_t PSEG2:3;
\r
5791 vuint32_t BOFFMSK:1;
\r
5792 vuint32_t ERRMSK:1;
\r
5793 vuint32_t CLKSRC:1;
\r
5795 vuint32_t TWRNMSK:1;
\r
5796 vuint32_t RWRNMSK:1;
\r
5799 vuint32_t BOFFREC:1;
\r
5803 vuint32_t PROPSEG:3;
\r
5807 union { /* FLEXCAN Free Running Timer (Base+0x0008) */
\r
5811 vuint32_t TIMER:16;
\r
5815 vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
\r
5817 union { /* FLEXCAN RX Global Mask (Base+0x0010) */
\r
5824 /* --- Following 2 registers are included for legacy purposes only --- */
\r
5826 union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
\r
5833 union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
\r
5842 union { /* FLEXCAN Error Counter (Base+0x001C) */
\r
5846 vuint32_t RXECNT:8;
\r
5847 vuint32_t TXECNT:8;
\r
5851 union { /* FLEXCAN Error & Status (Base+0x0020) */
\r
5855 vuint32_t TWRNINT:1;
\r
5856 vuint32_t RWRNINT:1;
\r
5857 vuint32_t BIT1ERR:1;
\r
5858 vuint32_t BIT0ERR:1;
\r
5859 vuint32_t ACKERR:1;
\r
5860 vuint32_t CRCERR:1;
\r
5861 vuint32_t FRMERR:1;
\r
5862 vuint32_t STFERR:1;
\r
5863 vuint32_t TXWRN:1;
\r
5864 vuint32_t RXWRN:1;
\r
5867 vuint32_t FLTCONF:2;
\r
5869 vuint32_t BOFFINT:1;
\r
5870 vuint32_t ERRINT:1;
\r
5875 union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
\r
5878 vuint32_t BUF63M:1;
\r
5879 vuint32_t BUF62M:1;
\r
5880 vuint32_t BUF61M:1;
\r
5881 vuint32_t BUF60M:1;
\r
5882 vuint32_t BUF59M:1;
\r
5883 vuint32_t BUF58M:1;
\r
5884 vuint32_t BUF57M:1;
\r
5885 vuint32_t BUF56M:1;
\r
5886 vuint32_t BUF55M:1;
\r
5887 vuint32_t BUF54M:1;
\r
5888 vuint32_t BUF53M:1;
\r
5889 vuint32_t BUF52M:1;
\r
5890 vuint32_t BUF51M:1;
\r
5891 vuint32_t BUF50M:1;
\r
5892 vuint32_t BUF49M:1;
\r
5893 vuint32_t BUF48M:1;
\r
5894 vuint32_t BUF47M:1;
\r
5895 vuint32_t BUF46M:1;
\r
5896 vuint32_t BUF45M:1;
\r
5897 vuint32_t BUF44M:1;
\r
5898 vuint32_t BUF43M:1;
\r
5899 vuint32_t BUF42M:1;
\r
5900 vuint32_t BUF41M:1;
\r
5901 vuint32_t BUF40M:1;
\r
5902 vuint32_t BUF39M:1;
\r
5903 vuint32_t BUF38M:1;
\r
5904 vuint32_t BUF37M:1;
\r
5905 vuint32_t BUF36M:1;
\r
5906 vuint32_t BUF35M:1;
\r
5907 vuint32_t BUF34M:1;
\r
5908 vuint32_t BUF33M:1;
\r
5909 vuint32_t BUF32M:1;
\r
5913 union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
\r
5916 vuint32_t BUF31M:1;
\r
5917 vuint32_t BUF30M:1;
\r
5918 vuint32_t BUF29M:1;
\r
5919 vuint32_t BUF28M:1;
\r
5920 vuint32_t BUF27M:1;
\r
5921 vuint32_t BUF26M:1;
\r
5922 vuint32_t BUF25M:1;
\r
5923 vuint32_t BUF24M:1;
\r
5924 vuint32_t BUF23M:1;
\r
5925 vuint32_t BUF22M:1;
\r
5926 vuint32_t BUF21M:1;
\r
5927 vuint32_t BUF20M:1;
\r
5928 vuint32_t BUF19M:1;
\r
5929 vuint32_t BUF18M:1;
\r
5930 vuint32_t BUF17M:1;
\r
5931 vuint32_t BUF16M:1;
\r
5932 vuint32_t BUF15M:1;
\r
5933 vuint32_t BUF14M:1;
\r
5934 vuint32_t BUF13M:1;
\r
5935 vuint32_t BUF12M:1;
\r
5936 vuint32_t BUF11M:1;
\r
5937 vuint32_t BUF10M:1;
\r
5938 vuint32_t BUF09M:1;
\r
5939 vuint32_t BUF08M:1;
\r
5940 vuint32_t BUF07M:1;
\r
5941 vuint32_t BUF06M:1;
\r
5942 vuint32_t BUF05M:1;
\r
5943 vuint32_t BUF04M:1;
\r
5944 vuint32_t BUF03M:1;
\r
5945 vuint32_t BUF02M:1;
\r
5946 vuint32_t BUF01M:1;
\r
5947 vuint32_t BUF00M:1;
\r
5951 union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
\r
5954 vuint32_t BUF63I:1;
\r
5955 vuint32_t BUF62I:1;
\r
5956 vuint32_t BUF61I:1;
\r
5957 vuint32_t BUF60I:1;
\r
5958 vuint32_t BUF59I:1;
\r
5959 vuint32_t BUF58I:1;
\r
5960 vuint32_t BUF57I:1;
\r
5961 vuint32_t BUF56I:1;
\r
5962 vuint32_t BUF55I:1;
\r
5963 vuint32_t BUF54I:1;
\r
5964 vuint32_t BUF53I:1;
\r
5965 vuint32_t BUF52I:1;
\r
5966 vuint32_t BUF51I:1;
\r
5967 vuint32_t BUF50I:1;
\r
5968 vuint32_t BUF49I:1;
\r
5969 vuint32_t BUF48I:1;
\r
5970 vuint32_t BUF47I:1;
\r
5971 vuint32_t BUF46I:1;
\r
5972 vuint32_t BUF45I:1;
\r
5973 vuint32_t BUF44I:1;
\r
5974 vuint32_t BUF43I:1;
\r
5975 vuint32_t BUF42I:1;
\r
5976 vuint32_t BUF41I:1;
\r
5977 vuint32_t BUF40I:1;
\r
5978 vuint32_t BUF39I:1;
\r
5979 vuint32_t BUF38I:1;
\r
5980 vuint32_t BUF37I:1;
\r
5981 vuint32_t BUF36I:1;
\r
5982 vuint32_t BUF35I:1;
\r
5983 vuint32_t BUF34I:1;
\r
5984 vuint32_t BUF33I:1;
\r
5985 vuint32_t BUF32I:1;
\r
5989 union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
\r
5992 vuint32_t BUF31I:1;
\r
5993 vuint32_t BUF30I:1;
\r
5994 vuint32_t BUF29I:1;
\r
5995 vuint32_t BUF28I:1;
\r
5996 vuint32_t BUF27I:1;
\r
5997 vuint32_t BUF26I:1;
\r
5998 vuint32_t BUF25I:1;
\r
5999 vuint32_t BUF24I:1;
\r
6000 vuint32_t BUF23I:1;
\r
6001 vuint32_t BUF22I:1;
\r
6002 vuint32_t BUF21I:1;
\r
6003 vuint32_t BUF20I:1;
\r
6004 vuint32_t BUF19I:1;
\r
6005 vuint32_t BUF18I:1;
\r
6006 vuint32_t BUF17I:1;
\r
6007 vuint32_t BUF16I:1;
\r
6008 vuint32_t BUF15I:1;
\r
6009 vuint32_t BUF14I:1;
\r
6010 vuint32_t BUF13I:1;
\r
6011 vuint32_t BUF12I:1;
\r
6012 vuint32_t BUF11I:1;
\r
6013 vuint32_t BUF10I:1;
\r
6014 vuint32_t BUF09I:1;
\r
6015 vuint32_t BUF08I:1;
\r
6016 vuint32_t BUF07I:1;
\r
6017 vuint32_t BUF06I:1;
\r
6018 vuint32_t BUF05I:1;
\r
6019 vuint32_t BUF04I:1;
\r
6020 vuint32_t BUF03I:1;
\r
6021 vuint32_t BUF02I:1;
\r
6022 vuint32_t BUF01I:1;
\r
6023 vuint32_t BUF00I:1;
\r
6025 } IFRL; /* Interruput Flag Register */
\r
6027 vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
\r
6029 /****************************************************************************/
\r
6030 /* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
\r
6031 /****************************************************************************/
\r
6032 /* Standard Buffer Structure */
\r
6033 struct FLEXCAN_BUF_t BUF[64];
\r
6035 /* RX FIFO and Buffer Structure */
\r
6036 /*struct FLEXCAN_RXFIFO_t RXFIFO; */
\r
6037 /*struct FLEXCAN_BUF_t BUF[56]; */
\r
6038 /****************************************************************************/
\r
6040 vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
\r
6042 union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
\r
6049 }; /* end of FLEXCAN_tag */
\r
6050 /****************************************************************************/
\r
6051 /* MODULE : DMAMUX (base address - 0xFFFD_C000) */
\r
6052 /****************************************************************************/
\r
6053 struct DMAMUX_tag {
\r
6054 union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
\r
6059 vuint8_t SOURCE:6;
\r
6063 }; /* end of DMAMUX_tag */
\r
6064 /****************************************************************************/
\r
6065 /* MODULE : DFLASH (base address - 0x0080_0000) */
\r
6066 /****************************************************************************/
\r
6067 struct DFLASH_tag {
\r
6068 union { /* Module Configuration (Base+0x0000) */
\r
6093 union { /* Low/Mid address block locking (Base+0x0004) */
\r
6105 union { /* High address block locking (Base+0x0008) */
\r
6110 vuint32_t HBLOCK:6;
\r
6114 union { /* Secondary Low/mid block locking (Base+0x000C)*/
\r
6119 vuint32_t STSLK:1;
\r
6126 union { /* Low/Mid address space block sel (Base+0x0010)*/
\r
6135 union { /* High address space block sel (Base+0x0014)*/
\r
6143 union { /* Address Register (Base+0x0018) */
\r
6152 vuint8_t DFLASH_reserved0[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
\r
6154 union { /* User Test 0 (Base+0x003C) */
\r
6170 union { /* User Test 1 (Base+0x0040) */
\r
6177 union { /* User Test 2 (Base+0x0044) */
\r
6184 union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
\r
6191 }; /* end of Dflash_tag */
\r
6192 /****************************************************************************/
\r
6193 /* MODULE : CFLASH (base address - 0xC3F8_8000) */
\r
6194 /****************************************************************************/
\r
6195 struct CFLASH_tag {
\r
6196 union { /* Module Configuration (Base+0x0000) */
\r
6222 union { /* Low/Mid address block locking (Base+0x0004) */
\r
6234 union { /* High address space block locking (Base+0x0008)*/
\r
6239 vuint32_t HBLOCK:12;
\r
6243 union { /* Secondary Low/Mid block lock (Base+0x000C)*/
\r
6248 vuint32_t STSLK:1;
\r
6255 union { /* Low/Mid address space block sel (Base+0x0010)*/
\r
6264 union { /* High address Space block select (Base+0x0014)*/
\r
6272 union { /* Address Register (Base+0x0018) */
\r
6281 /* Note the following 3 registers, BIU[0..2] are mirrored to */
\r
6282 /* the code flash configuraiton PFCR[0..2] registers */
\r
6283 /* To make it easier to code, the BIU registers have been */
\r
6284 /* replaced with the PFCR registers in this header file! */
\r
6285 /* A commented out BIU register is shown for reference! */
\r
6288 union { /* CFLASH Configuration 0 (Base+0x001C) */
\r
6291 vuint32_t BK0_APC:5;
\r
6292 vuint32_t BK0_WWSC:5;
\r
6293 vuint32_t BK0_RWSC:5;
\r
6294 vuint32_t BK0_RWWC2:1;
\r
6295 vuint32_t BK0_RWWC1:1;
\r
6296 /* vuint32_t B0_P1_BCFG:2; // only has one port to the cross bar i.e. port 0
\r
6297 vuint32_t B0_P1_DPFE:1;
\r
6298 vuint32_t B0_P1_IPFE:1;
\r
6299 vuint32_t B0_P1_PFLM:2;
\r
6300 vuint32_t B0_P1_BFE:1; */
\r
6302 vuint32_t BK0_RWWC0:1;
\r
6303 vuint32_t B0_P0_BCFG:2;
\r
6304 vuint32_t B0_P0_DPFE:1;
\r
6305 vuint32_t B0_P0_IPFE:1;
\r
6306 vuint32_t B0_P0_PFLM:2;
\r
6307 vuint32_t B0_P0_BFE:1;
\r
6311 /* Commented out Bus Interface Unit 0 (Base+0x001C) */
\r
6319 union { /* CFLASH Configuration Register 1 (Base+0x0020)*/
\r
6322 vuint32_t BK1_APC:5;
\r
6323 vuint32_t BK1_WWSC:5;
\r
6324 vuint32_t BK1_RWSC:5;
\r
6325 vuint32_t BK1_RWWC2:1;
\r
6326 vuint32_t BK1_RWWC1:1;
\r
6327 vuint32_t:7; /* changed to 7 to suit comment below */
\r
6328 //vuint32_t B1_P1_BFE:1; /* should have no effect, there is only one XBAR port (no P1) to P-flash controller */
\r
6329 vuint32_t BK1_RWWC0:1;
\r
6331 vuint32_t B1_P0_BFE:1;
\r
6335 /* Commented out Bus Interface Unit 1 (Base+0x0020) */
\r
6343 union { /* CFLASH Access Protection (Base+0x0024) */
\r
6346 vuint32_t:6; /*incorrect - B1M/B1.5M does not have this many masters TBD*/
\r
6348 vuint32_t M7PFD:1;
\r
6349 vuint32_t M6PFD:1;
\r
6350 vuint32_t M5PFD:1;
\r
6351 vuint32_t M4PFD:1;
\r
6352 vuint32_t M3PFD:1;
\r
6353 vuint32_t M2PFD:1;
\r
6354 vuint32_t M1PFD:1;
\r
6355 vuint32_t M0PFD:1;
\r
6367 /* Commented out Bus Interface Unit 2 (Base+0x0024) */
\r
6375 vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
\r
6377 union { /* User Test 0 (Base+0x003C) */
\r
6393 union { /* User Test 1 (Base+0x0040) */
\r
6400 union { /* User Test 2 (Base+0x0044) */
\r
6407 union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
\r
6414 vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
\r
6416 }; /* end of CFLASH_tag */
\r
6417 /******************************************************************
\r
6418 | defines and macros (scope: module-local)
\r
6419 |-----------------------------------------------------------------*/
\r
6420 /* Define instances of modules */
\r
6422 #define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)
\r
6423 #define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
\r
6424 #define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
\r
6425 #define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
\r
6426 #define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
\r
6427 #define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
\r
6428 #define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
\r
6429 #define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
\r
6430 #define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
\r
6431 #define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
\r
6432 #define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
\r
6433 #define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)
\r
6434 #define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
\r
6435 #define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
\r
6436 #define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
\r
6437 #define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
\r
6438 #define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
\r
6439 #define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
\r
6440 #define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)
\r
6441 #define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)
\r
6442 #define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
\r
6443 #define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
\r
6444 #define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
\r
6445 #define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)
\r
6446 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
\r
6447 #define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)
\r
6448 #define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)
\r
6449 #define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
\r
6450 #define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
\r
6451 #define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)
\r
6452 #define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)
\r
6453 #define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)
\r
6454 #define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)
\r
6455 #define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)
\r
6456 #define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)
\r
6457 #define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
\r
6458 #define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
\r
6459 #define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
\r
6460 #define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
\r
6461 #define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
\r
6462 #define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
\r
6463 #define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
\r
6464 #define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
\r
6465 #define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
\r
6466 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
\r
6467 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
\r
6468 #define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
\r
6474 #ifdef __cplusplus
\r
projects / arc.git / blob