1 /*****************************************************************
\r
3 * FILE : MPC5604B_0M27V_0100.h
\r
5 * DESCRIPTION : This is the header file describing the register
\r
7 * MPC5604B, mask set = 0M27V
\r
8 * SPC560B4, mask set = FB50X20B
\r
10 * COPYRIGHT :(c) 2009, Freescale & STMicroelectronics
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13 * DATE : 08 MAY 2009
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15 * HISTORY : Original source taken from jdp_0100.h.
\r
16 * Updated to be compatable with
\r
17 * - MPC5604B Mask ID 0M27V
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18 * - MPC5604B Reference Manual Rev 3 Draft A
\r
19 * - SPC560B4 Mask ID FB50X20B
\r
20 * - SPC560B4 Reference Manual Rev 3 Draft A
\r
22 ******************************************************************/
\r
24 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
26 /*****************************************************************
\r
27 * Example instantiation and use:
\r
29 * <MODULE>.<REGISTER>.B.<BIT> = 1;
\r
30 * <MODULE>.<REGISTER>.R = 0x10000000;
\r
32 ******************************************************************/
\r
34 #ifndef _MPC5604B_H_
\r
35 #define _MPC5604B_H_
\r
37 #include "Compiler.h"
\r
38 #include "typedefs.h"
\r
48 #pragma ANSI_strict off
\r
52 #include "ip_adc_mpc56xx.h"
\r
55 /****************************************************************************/
\r
57 /****************************************************************************/
\r
75 vuint32_t ADCLKSEL:1;
\r
76 vuint32_t ABORTCHAIN:1;
\r
82 } MCR; /* MAIN CONFIGURATION REGISTER */
\r
93 vuint32_t CTUSTART:1;
\r
98 vuint32_t ADCSTATUS:3;
\r
100 } MSR; /* MAIN STATUS REGISTER */
\r
102 int32_t ADC_reserved1[2]; /* (0x010 - 0x008)/4 = 0x02 */
\r
114 } ISR; /* INTERRUPT STATUS REGISTER */
\r
119 vuint32_t EOC_CH31:1;
\r
120 vuint32_t EOC_CH30:1;
\r
121 vuint32_t EOC_CH29:1;
\r
122 vuint32_t EOC_CH28:1;
\r
123 vuint32_t EOC_CH27:1;
\r
124 vuint32_t EOC_CH26:1;
\r
125 vuint32_t EOC_CH25:1;
\r
126 vuint32_t EOC_CH24:1;
\r
127 vuint32_t EOC_CH23:1;
\r
128 vuint32_t EOC_CH22:1;
\r
129 vuint32_t EOC_CH21:1;
\r
130 vuint32_t EOC_CH20:1;
\r
131 vuint32_t EOC_CH19:1;
\r
132 vuint32_t EOC_CH18:1;
\r
133 vuint32_t EOC_CH17:1;
\r
134 vuint32_t EOC_CH16:1;
\r
135 vuint32_t EOC_CH15:1;
\r
136 vuint32_t EOC_CH14:1;
\r
137 vuint32_t EOC_CH13:1;
\r
138 vuint32_t EOC_CH12:1;
\r
139 vuint32_t EOC_CH11:1;
\r
140 vuint32_t EOC_CH10:1;
\r
141 vuint32_t EOC_CH9:1;
\r
142 vuint32_t EOC_CH8:1;
\r
143 vuint32_t EOC_CH7:1;
\r
144 vuint32_t EOC_CH6:1;
\r
145 vuint32_t EOC_CH5:1;
\r
146 vuint32_t EOC_CH4:1;
\r
147 vuint32_t EOC_CH3:1;
\r
148 vuint32_t EOC_CH2:1;
\r
149 vuint32_t EOC_CH1:1;
\r
150 vuint32_t EOC_CH0:1;
\r
152 } CEOCFR[3]; /* Channel Pending Register 0 */
\r
158 vuint32_t MSKEOCTU:1;
\r
159 vuint32_t MSKJEOC:1;
\r
160 vuint32_t MSKJECH:1;
\r
161 vuint32_t MSKEOC:1;
\r
162 vuint32_t MSKECH:1;
\r
164 } IMR; /* INTERRUPT MASK REGISTER */
\r
202 } CIMR[3]; /* Channel Interrupt Mask Register 0 */
\r
217 } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
\r
223 vuint32_t MSKWDG3H:1;
\r
224 vuint32_t MSKWDG2H:1;
\r
225 vuint32_t MSKWDG1H:1;
\r
226 vuint32_t MSKWDG0H:1;
\r
227 vuint32_t MSKWDG3L:1;
\r
228 vuint32_t MSKWDG2L:1;
\r
229 vuint32_t MSKWDG1L:1;
\r
230 vuint32_t MSKWDG0L:1;
\r
232 } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER */
\r
234 int32_t ADC_reserved2[6]; /* (0x050 - 0x038)/4 = 0x06 */
\r
241 vuint32_t THRINV:1;
\r
245 } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */
\r
255 } THRHLR[4]; /* THRESHOLD REGISTER */
\r
257 int32_t ADC_reserved3[4]; /* (0x080 - 0x070)/4 = 0x04 */
\r
263 vuint32_t PREVAL2:2;
\r
264 vuint32_t PREVAL1:2;
\r
265 vuint32_t PREVAL0:2;
\r
266 vuint32_t PRECONV:1;
\r
268 } PSCR; /* PRESAMPLING CONTROL REGISTER */
\r
273 vuint32_t PRES31:1;
\r
274 vuint32_t PRES30:1;
\r
275 vuint32_t PRES29:1;
\r
276 vuint32_t PRES28:1;
\r
277 vuint32_t PRES27:1;
\r
278 vuint32_t PRES26:1;
\r
279 vuint32_t PRES25:1;
\r
280 vuint32_t PRES24:1;
\r
281 vuint32_t PRES23:1;
\r
282 vuint32_t PRES22:1;
\r
283 vuint32_t PRES21:1;
\r
284 vuint32_t PRES20:1;
\r
285 vuint32_t PRES19:1;
\r
286 vuint32_t PRES18:1;
\r
287 vuint32_t PRES17:1;
\r
288 vuint32_t PRES16:1;
\r
289 vuint32_t PRES15:1;
\r
290 vuint32_t PRES14:1;
\r
291 vuint32_t PRES13:1;
\r
292 vuint32_t PRES12:1;
\r
293 vuint32_t PRES11:1;
\r
294 vuint32_t PRES10:1;
\r
306 } PSR[3]; /* PRESAMPLING REGISTER */
\r
308 int32_t ADC_reserved4[1]; /* (0x094 - 0x090)/4 = 0x01 */
\r
314 vuint32_t INPLATCH:1;
\r
316 vuint32_t INPCMP:2;
\r
318 vuint32_t INPSAMP:8;
\r
320 } CTR[3]; /* CONVERSION TIMING REGISTER */
\r
322 int32_t ADC_reserved5[1]; /* (0x0A4 - 0x0A0)/4 = 0x01 */
\r
360 } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER */
\r
362 int32_t ADC_reserved6[1]; /* (0x0B4 - 0x0B0)/4 = 0x01 */
\r
400 } JCMR[3]; /* Injected CONVERSION MASK REGISTER */
\r
402 int32_t ADC_reserved7[1]; /* (0x0C4 - 0x0C0)/4 = 0x01 */
\r
410 } DSDR; /* DECODE SIGNALS DELAY REGISTER */
\r
418 } PDEDR; /* POWER DOWN DELAY REGISTER */
\r
420 int32_t ADC_reserved8[13]; /* (0x100 - 0x0CC)/4 = 0x0D */
\r
428 vuint32_t RESULT:2;
\r
430 vuint32_t CDATA:10;
\r
432 } CDR[96]; /* Channel 0-95 Data REGISTER */
\r
434 }; /* end of ADC_tag */
\r
437 /****************************************************************************/
\r
438 /* MODULE : CANSP */
\r
439 /****************************************************************************/
\r
445 vuint32_t RX_COMPLETE:1;
\r
447 vuint32_t ACTIVE_CK:1;
\r
450 vuint32_t CAN_RX_SEL:3;
\r
452 vuint32_t CAN_SMPLR_EN:1;
\r
454 } CR; /* CANSP Control Register */
\r
458 } SR[12]; /* CANSP Sample Register 0 to 11 */
\r
460 }; /* end of CANSP_tag */
\r
461 /****************************************************************************/
\r
462 /* MODULE : CFLASH */
\r
463 /****************************************************************************/
\r
464 struct CFLASH_tag {
\r
465 union { /* Module Configuration Register */
\r
491 union { /* LML Register */
\r
503 union { /* HBL Register */
\r
508 vuint32_t HBLOCK:8;
\r
512 union { /* SLML Register */
\r
524 union { /* LMS Register */
\r
533 union { /* High Address Space Block Select Register */
\r
541 union { /* Address Register */
\r
550 union { /* CFLASH Configuration Register 0 */
\r
553 vuint32_t BK0_APC:5;
\r
554 vuint32_t BK0_WWSC:5;
\r
555 vuint32_t BK0_RWSC:5;
\r
556 vuint32_t BK0_RWWC2:1;
\r
557 vuint32_t BK0_RWWC1:1;
\r
558 vuint32_t B0_P1_BCFG:2;
\r
559 vuint32_t B0_P1_DPFE:1;
\r
560 vuint32_t B0_P1_IPFE:1;
\r
561 vuint32_t B0_P1_PFLM:2;
\r
562 vuint32_t B0_P1_BFE:1;
\r
563 vuint32_t BK0_RWWC0:1;
\r
564 vuint32_t B0_P0_BCFG:2;
\r
565 vuint32_t B0_P0_DPFE:1;
\r
566 vuint32_t B0_P0_IPFE:1;
\r
567 vuint32_t B0_P0_PFLM:2;
\r
568 vuint32_t B0_P0_BFE:1;
\r
572 union { /* CFLASH Configuration Register 1 */
\r
575 vuint32_t BK1_APC:5;
\r
576 vuint32_t BK1_WWSC:5;
\r
577 vuint32_t BK1_RWSC:5;
\r
578 vuint32_t BK1_RWWC2:1;
\r
579 vuint32_t BK1_RWWC1:1;
\r
581 vuint32_t B0_P1_BFE:1;
\r
582 vuint32_t BK1_RWWC0:1;
\r
584 vuint32_t B1_P0_BFE:1;
\r
588 union { /* cflash Access Protection Register */
\r
612 int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
\r
614 union { /* User Test Register 0 */
\r
630 union { /* User Test Register 1 */
\r
637 union { /* User Test Register 2 */
\r
644 union { /* User Multiple Input Signature Register 0-4 */
\r
651 }; /* end of CFLASH_tag */
\r
652 /****************************************************************************/
\r
654 /****************************************************************************/
\r
657 /* The CGM provides a unified register interface, enabling access to
\r
661 Base Address | Clock Sources
\r
663 -----------------------------
\r
665 0xC3FE0000 | FXOSC_CTL
\r
667 ---------- | Reserved
\r
669 0xC3FE0040 | SXOSC_CTL
\r
671 0xC3FE0060 | FIRC_CTL
\r
673 0xC3FE0080 | SIRC_CTL
\r
675 0xC3FE00A0 | FMPLL_0
\r
677 ---------- | Reserved
\r
682 /************************************/
\r
683 /* FXOSC_CTL @ CGM base address + 0x0000 */
\r
684 /************************************/
\r
688 vuint32_t OSCBYP:1;
\r
693 vuint32_t OSCDIV:5;
\r
697 } FXOSC_CTL; /* Fast OSC Control Register */
\r
699 /************************************/
\r
700 /* SXOSC_CTL @ CGM base address + 0x0040 */
\r
701 /************************************/
\r
702 int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
\r
707 vuint32_t OSCBYP:1;
\r
712 vuint32_t OSCDIV:5;
\r
718 } SXOSC_CTL; /* Slow OSC Control Register */
\r
720 /************************************/
\r
721 /* FIRC_CTL @ CGM base address + 0x0060 */
\r
722 /************************************/
\r
723 int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
\r
729 vuint32_t RCTRIM:6;
\r
734 } FIRC_CTL; /* Fast IRC Control Register */
\r
736 /****************************************/
\r
737 /* SIRC_CTL @ CGM base address + 0x0080 */
\r
738 /****************************************/
\r
739 int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
\r
745 vuint32_t RCTRIM:5;
\r
749 vuint32_t S_SIRC:1;
\r
751 vuint32_t SIRCON_STDBY:1;
\r
753 } SIRC_CTL; /* Slow IRC Control Register */
\r
755 /*************************************/
\r
756 /* FMPLL @ CGM base address + 0x00A0 */
\r
757 /*************************************/
\r
758 int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
\r
769 vuint32_t EN_PLL_SW:1;
\r
771 vuint32_t UNLOCK_ONCE:1;
\r
773 vuint32_t I_LOCK:1;
\r
774 vuint32_t S_LOCK:1;
\r
775 vuint32_t PLL_FAIL_MASK:1;
\r
776 vuint32_t PLL_FAIL_FLAG:1;
\r
779 } FMPLL_CR; /* FMPLL Control Register */
\r
784 vuint32_t STRB_BYPASS:1;
\r
786 vuint32_t SPRD_SEL:1;
\r
787 vuint32_t MOD_PERIOD:13;
\r
789 vuint32_t INC_STEP:15;
\r
791 } FMPLL_MR; /* FMPLL Modulation Register */
\r
793 /************************************/
\r
794 /* CMU @ CGM base address + 0x0100 */
\r
795 /************************************/
\r
796 int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */
\r
804 vuint32_t CLKSEL1:2;
\r
809 } CMU_CSR; /* Control Status Register */
\r
817 } CMU_FDR; /* Frequency Display Register */
\r
823 vuint32_t HFREF_A:12;
\r
825 } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
\r
831 vuint32_t LFREF_A:12;
\r
833 } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
\r
839 vuint32_t FLCI_A:1;
\r
840 vuint32_t FHHI_A:1;
\r
841 vuint32_t FLLI_A:1;
\r
844 } CMU_ISR; /* Interrupt Status Register */
\r
851 } CMU_IMR; /* Interrupt Mask Register */
\r
859 } CMU_MDR; /* Measurement Duration Register */
\r
861 /************************************/
\r
862 /* CGM General Registers @ CGM base address + 0x0370 */
\r
863 /************************************/
\r
864 int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */
\r
872 } OC_EN; /* Output Clock Enable Register */
\r
878 vuint32_t SELDIV:2;
\r
879 vuint32_t SELCTL:4;
\r
882 } OCDS_SC; /* Output Clock Division Select Register */
\r
888 vuint32_t SELSTAT:4;
\r
891 } SC_SS; /* System Clock Select Status */
\r
900 } SC_DC[3]; /* System Clock Divider Configuration 0->2 */
\r
902 }; /* end of CGM_tag */
\r
903 /****************************************************************************/
\r
905 /****************************************************************************/
\r
911 vuint32_t TRGIEN:1;
\r
915 } CSR; /* Control Status Register */
\r
917 int32_t CTU_reserved0[11]; /* (0x030 - 0x004)/4 = 0x0B */
\r
925 vuint32_t CLR_FLAG:1;
\r
927 vuint32_t CHANNELVALUE:6;
\r
929 } EVTCFGR[64]; /* Event Configuration Register */
\r
931 }; /* end of CTU_tag */
\r
932 /****************************************************************************/
\r
933 /* MODULE : DFLASH */
\r
934 /****************************************************************************/
\r
935 struct DFLASH_tag {
\r
936 union { /* Module Configuration Register */
\r
962 union { /* LML Register */
\r
974 union { /* HBL Register */
\r
979 vuint32_t HBLOCK:8;
\r
983 union { /* SLML Register */
\r
995 union { /* LMS Register */
\r
1004 union { /* High Address Space Block Select Register */
\r
1012 union { /* Address Register */
\r
1021 int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
\r
1023 union { /* User Test Register 0 */
\r
1039 union { /* User Test Register 1 */
\r
1046 union { /* User Test Register 2 */
\r
1053 union { /* User Multiple Input Signature Register 0-4 */
\r
1060 }; /* end of Dflash_tag */
\r
1061 /****************************************************************************/
\r
1062 /* MODULE : DSPI */
\r
1063 /****************************************************************************/
\r
1064 #include "ip_dspi.h"
\r
1066 /****************************************************************************/
\r
1067 /* MODULE : ECSM */
\r
1068 /****************************************************************************/
\r
1073 } PCT; /* ECSM Processor Core Type Register */
\r
1077 } REV; /* ECSM Revision Register */
\r
1079 int32_t ECSM_reserved1;
\r
1083 } IMC; /* ECSM IPS Module Configuration Register */
\r
1085 int8_t ECSM_reserved2[7];
\r
1090 vuint8_t ENBWCR:1;
\r
1092 vuint8_t PRILVL:4;
\r
1094 } MWCR; /* ECSM Miscellaneous Wakeup Control Register */
\r
1096 int32_t ECSM_reserved3[2];
\r
1097 int8_t ECSM_reserved4[3];
\r
1108 } MIR; /* ECSM Miscellaneous Interrupt Register */
\r
1110 int32_t ECSM_reserved5;
\r
1114 } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
\r
1116 int32_t ECSM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
\r
1117 int8_t ECSM_reserved7[3];
\r
1129 } ECR; /* ECSM ECC Configuration Register */
\r
1131 int8_t ECSM_reserved8[3];
\r
1143 } ESR; /* ECSM ECC Status Register */
\r
1145 int16_t ECSM_reserved9;
\r
1151 vuint16_t FRC1BI:1;
\r
1152 vuint16_t FR11BI:1;
\r
1154 vuint16_t FRCNCI:1;
\r
1155 vuint16_t FR1NCI:1;
\r
1157 vuint16_t ERRBIT:7;
\r
1159 } EEGR; /* ECSM ECC Error Generation Register */
\r
1161 int32_t ECSM_reserved10;
\r
1165 } FEAR; /* ECSM Flash ECC Address Register */
\r
1167 int16_t ECSM_reserved11;
\r
1175 } FEMR; /* ECSM Flash ECC Master Number Register */
\r
1182 vuint8_t PROTECTION:4;
\r
1184 } FEAT; /* ECSM Flash ECC Attributes Register */
\r
1186 int32_t ECSM_reserved12;
\r
1190 } FEDR; /* ECSM Flash ECC Data Register */
\r
1194 } REAR; /* ECSM RAM ECC Address Register */
\r
1196 int8_t ECSM_reserved13;
\r
1200 } RESR; /* ECSM RAM ECC Address Register */
\r
1208 } REMR; /* ECSM RAM ECC Master Number Register */
\r
1215 vuint8_t PROTECTION:4;
\r
1217 } REAT; /* ECSM RAM ECC Attributes Register */
\r
1219 int32_t ECSM_reserved14;
\r
1223 } REDR; /* ECSM RAM ECC Data Register */
\r
1225 }; /* end of ECSM_tag */
\r
1226 /****************************************************************************/
\r
1227 /* MODULE : EMIOS */
\r
1228 /****************************************************************************/
\r
1229 struct EMIOS_CHANNEL_tag {
\r
1234 vuint32_t CADR:16;
\r
1236 } CADR; /* Channel A Data Register */
\r
1242 vuint32_t CBDR:16;
\r
1244 } CBDR; /* Channel B Data Register */
\r
1250 vuint32_t CCNTR:16;
\r
1252 } CCNTR; /* Channel Counter Register */
\r
1259 vuint32_t ODISSL:2;
\r
1260 vuint32_t UCPRE:2;
\r
1261 vuint32_t UCPEN:1;
\r
1268 vuint32_t FORCMA:1;
\r
1269 vuint32_t FORCMB:1;
\r
1272 vuint32_t EDSEL:1;
\r
1273 vuint32_t EDPOL:1;
\r
1276 } CCR; /* Channel Control Register */
\r
1286 vuint32_t UCOUT:1;
\r
1289 } CSR; /* Channel Status Register */
\r
1292 vuint32_t R; /* Alternate Channel A Data Register */
\r
1295 uint32_t emios_channel_reserved[2];
\r
1297 }; /* end of EMIOS_CHANNEL_tag */
\r
1299 struct EMIOS_tag {
\r
1308 vuint32_t GPREN:1;
\r
1314 } MCR; /* Module Configuration Register */
\r
1345 } GFR; /* Global FLAG Register */
\r
1376 } OUDR; /* Output Update Disable Register */
\r
1382 vuint32_t CHDIS23:1;
\r
1383 vuint32_t CHDIS22:1;
\r
1384 vuint32_t CHDIS21:1;
\r
1385 vuint32_t CHDIS20:1;
\r
1386 vuint32_t CHDIS19:1;
\r
1387 vuint32_t CHDIS18:1;
\r
1388 vuint32_t CHDIS17:1;
\r
1389 vuint32_t CHDIS16:1;
\r
1390 vuint32_t CHDIS15:1;
\r
1391 vuint32_t CHDIS14:1;
\r
1392 vuint32_t CHDIS13:1;
\r
1393 vuint32_t CHDIS12:1;
\r
1394 vuint32_t CHDIS11:1;
\r
1395 vuint32_t CHDIS10:1;
\r
1396 vuint32_t CHDIS9:1;
\r
1397 vuint32_t CHDIS8:1;
\r
1398 vuint32_t CHDIS7:1;
\r
1399 vuint32_t CHDIS6:1;
\r
1400 vuint32_t CHDIS5:1;
\r
1401 vuint32_t CHDIS4:1;
\r
1402 vuint32_t CHDIS3:1;
\r
1403 vuint32_t CHDIS2:1;
\r
1404 vuint32_t CHDIS1:1;
\r
1405 vuint32_t CHDIS0:1;
\r
1407 } UCDIS; /* Disable Channel Register */
\r
1409 uint32_t emios_reserved1[4];
\r
1411 struct EMIOS_CHANNEL_tag CH[28];
\r
1413 }; /* end of EMIOS_tag */
\r
1414 /****************************************************************************/
\r
1415 /* MODULE : FlexCAN */
\r
1416 /****************************************************************************/
\r
1417 #include "ip_flexcan.h"
\r
1419 /****************************************************************************/
\r
1420 /* MODULE : i2c */
\r
1421 /****************************************************************************/
\r
1429 } IBAD; /* Module Bus Address Register */
\r
1436 } IBFD; /* Module Bus Frequency Register */
\r
1448 vuint8_t IBDOZE:1;
\r
1450 } IBCR; /* Module Bus Control Register */
\r
1464 } IBSR; /* Module Status Register */
\r
1471 } IBDR; /* Module Data Register */
\r
1479 } IBIC; /* Module Interrupt Configuration Register */
\r
1481 }; /* end of I2C_tag */
\r
1482 /****************************************************************************/
\r
1483 /* MODULE : INTC */
\r
1484 /****************************************************************************/
\r
1494 } MCR; /* Module Configuration Register */
\r
1496 int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
\r
1504 } CPR; /* Current Priority Register */
\r
1506 int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
\r
1511 vuint32_t VTBA:21;
\r
1512 vuint32_t INTVEC:9;
\r
1515 } IACKR; /* Interrupt Acknowledge Register */
\r
1517 int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
\r
1524 } EOIR; /* End of Interrupt Register */
\r
1526 int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
\r
1535 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
1537 uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
\r
1545 } PSR[512]; /* Software Set/Clear Interrupt Register */
\r
1547 }; /* end of INTC_tag */
\r
1548 /****************************************************************************/
\r
1549 /* MODULE : LINFLEX */
\r
1550 /****************************************************************************/
\r
1552 struct LINFLEX_tag {
\r
1569 vuint32_t SLEEP:1;
\r
1572 } LINCR1; /* LINFLEX LIN Control Register 1 */
\r
1588 vuint32_t DBFIE:1;
\r
1589 vuint32_t DBEIE:1;
\r
1594 } LINIER; /* LINFLEX LIN Interrupt Enable Register */
\r
1613 } LINSR; /* LINFLEX LIN Status Register */
\r
1625 vuint32_t IDPEF:1;
\r
1631 } LINESR; /* LINFLEX LIN Error Status Register */
\r
1649 } UARTCR; /* LINFLEX UART Mode Control Register */
\r
1668 } UARTSR; /* LINFLEX UART Mode Status Register */
\r
1680 } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
\r
1689 } LINOCR; /* LINFLEX LIN Output Compare Register */
\r
1700 } LINTOCR; /* LINFLEX LIN Output Compare Register */
\r
1707 vuint32_t DIV_F:4;
\r
1709 } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
\r
1716 vuint32_t DIV_M:13;
\r
1718 } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
\r
1727 } LINCFR; /* LINFLEX LIN Checksum Field Register */
\r
1743 } LINCR2; /* LINFLEX LIN Control Register 2 */
\r
1755 } BIDR; /* LINFLEX Buffer Identifier Register */
\r
1760 vuint32_t DATA3:8;
\r
1761 vuint32_t DATA2:8;
\r
1762 vuint32_t DATA1:8;
\r
1763 vuint32_t DATA0:8;
\r
1765 } BDRL; /* LINFLEX Buffer Data Register Least Significant */
\r
1770 vuint32_t DATA7:8;
\r
1771 vuint32_t DATA6:8;
\r
1772 vuint32_t DATA5:8;
\r
1773 vuint32_t DATA4:8;
\r
1775 } BDRM; /* LINFLEX Buffer Data Register Most Significant */
\r
1784 } IFER; /* LINFLEX Identifier Filter Enable Register */
\r
1793 } IFMI; /* LINFLEX Identifier Filter Match Index Register */
\r
1802 } IFMR; /* LINFLEX Identifier Filter Mode Register */
\r
1815 } IFCR[16]; /* LINFLEX Identifier Filter Control Register 0-15 */
\r
1817 }; /* end of LINFLEX_tag */
\r
1818 /****************************************************************************/
\r
1820 /****************************************************************************/
\r
1826 vuint32_t S_CURRENTMODE:4;
\r
1827 vuint32_t S_MTRANS:1;
\r
1830 vuint32_t S_PDO:1;
\r
1832 vuint32_t S_MVR:1;
\r
1833 vuint32_t S_DFLA:2;
\r
1834 vuint32_t S_CFLA:2;
\r
1836 vuint32_t S_FMPLL:1;
\r
1837 vuint32_t S_FXOSC:1;
\r
1838 vuint32_t S_FIRC:1;
\r
1839 vuint32_t S_SYSCLK:4;
\r
1841 } GS; /* Global Status Register */
\r
1846 vuint32_t TARGET_MODE:4;
\r
1850 } MCTL; /* Mode Control Register */
\r
1856 vuint32_t STANDBY0:1;
\r
1858 vuint32_t STOP0:1;
\r
1860 vuint32_t HALT0:1;
\r
1868 vuint32_t RESET:1;
\r
1870 } MER; /* Mode Enable Register */
\r
1876 vuint32_t I_CONF:1;
\r
1877 vuint32_t I_MODE:1;
\r
1878 vuint32_t I_SAFE:1;
\r
1879 vuint32_t I_MTC:1;
\r
1881 } IS; /* Interrupt Status Register */
\r
1887 vuint32_t M_CONF:1;
\r
1888 vuint32_t M_MODE:1;
\r
1889 vuint32_t M_SAFE:1;
\r
1890 vuint32_t M_MTC:1;
\r
1892 } IM; /* Interrupt Mask Register */
\r
1898 vuint32_t S_MTI:1;
\r
1899 vuint32_t S_MRI:1;
\r
1900 vuint32_t S_DMA:1;
\r
1901 vuint32_t S_NMA:1;
\r
1902 vuint32_t S_SEA:1;
\r
1904 } IMTS; /* Invalid Mode Transition Status Register */
\r
1910 vuint32_t MPH_BUSY:1;
\r
1912 vuint32_t PMC_PROG:1;
\r
1913 vuint32_t CORE_DBG:1;
\r
1917 vuint32_t FMPLL_SC:1;
\r
1918 vuint32_t FXOSC_SC:1;
\r
1919 vuint32_t FIRC_SC:1;
\r
1921 vuint32_t SYSCLK_SW:1;
\r
1922 vuint32_t DFLASH_SC:1;
\r
1923 vuint32_t CFLASH_SC:1;
\r
1924 vuint32_t CDP_PRPH_0_143:1;
\r
1926 vuint32_t CDP_PRPH_96_127:1;
\r
1927 vuint32_t CDP_PRPH_64_95:1;
\r
1928 vuint32_t CDP_PRPH_32_63:1;
\r
1929 vuint32_t CDP_PRPH_0_31:1;
\r
1931 } DMTS; /* Invalid Mode Transition Status Register */
\r
1933 int32_t ME_reserved0;
\r
1941 vuint32_t MVRON:1;
\r
1942 vuint32_t DFLAON:2;
\r
1943 vuint32_t CFLAON:2;
\r
1945 vuint32_t FMPLLON:1;
\r
1946 vuint32_t FXOSC0ON:1;
\r
1947 vuint32_t FIRCON:1;
\r
1948 vuint32_t SYSCLK:4;
\r
1950 } RESET; /* Reset Mode Configuration Register */
\r
1958 vuint32_t MVRON:1;
\r
1959 vuint32_t DFLAON:2;
\r
1960 vuint32_t CFLAON:2;
\r
1962 vuint32_t FMPLLON:1;
\r
1963 vuint32_t FXOSC0ON:1;
\r
1964 vuint32_t FIRCON:1;
\r
1965 vuint32_t SYSCLK:4;
\r
1967 } TEST; /* Test Mode Configuration Register */
\r
1975 vuint32_t MVRON:1;
\r
1976 vuint32_t DFLAON:2;
\r
1977 vuint32_t CFLAON:2;
\r
1979 vuint32_t FMPLLON:1;
\r
1980 vuint32_t FXOSC0ON:1;
\r
1981 vuint32_t FIRCON:1;
\r
1982 vuint32_t SYSCLK:4;
\r
1984 } SAFE; /* Safe Mode Configuration Register */
\r
1992 vuint32_t MVRON:1;
\r
1993 vuint32_t DFLAON:2;
\r
1994 vuint32_t CFLAON:2;
\r
1996 vuint32_t FMPLLON:1;
\r
1997 vuint32_t FXOSC0ON:1;
\r
1998 vuint32_t FIRCON:1;
\r
1999 vuint32_t SYSCLK:4;
\r
2001 } DRUN; /* DRUN Mode Configuration Register */
\r
2009 vuint32_t MVRON:1;
\r
2010 vuint32_t DFLAON:2;
\r
2011 vuint32_t CFLAON:2;
\r
2013 vuint32_t FMPLLON:1;
\r
2014 vuint32_t FXOSC0ON:1;
\r
2015 vuint32_t FIRCON:1;
\r
2016 vuint32_t SYSCLK:4;
\r
2018 } RUN[4]; /* RUN 0->4 Mode Configuration Register */
\r
2026 vuint32_t MVRON:1;
\r
2027 vuint32_t DFLAON:2;
\r
2028 vuint32_t CFLAON:2;
\r
2030 vuint32_t FMPLLON:1;
\r
2031 vuint32_t FXOSC0ON:1;
\r
2032 vuint32_t FIRCON:1;
\r
2033 vuint32_t SYSCLK:4;
\r
2035 } HALT0; /* HALT0 Mode Configuration Register */
\r
2037 int32_t ME_reserved1;
\r
2045 vuint32_t MVRON:1;
\r
2046 vuint32_t DFLAON:2;
\r
2047 vuint32_t CFLAON:2;
\r
2049 vuint32_t FMPLLON:1;
\r
2050 vuint32_t FXOSC0ON:1;
\r
2051 vuint32_t FIRCON:1;
\r
2052 vuint32_t SYSCLK:4;
\r
2054 } STOP0; /* STOP0 Mode Configuration Register */
\r
2056 int32_t ME_reserved2[2];
\r
2064 vuint32_t MVRON:1;
\r
2065 vuint32_t DFLAON:2;
\r
2066 vuint32_t CFLAON:2;
\r
2068 vuint32_t FMPLLON:1;
\r
2069 vuint32_t FXOSC0ON:1;
\r
2070 vuint32_t FIRCON:1;
\r
2071 vuint32_t SYSCLK:4;
\r
2073 } STANDBY0; /* STANDBY0 Mode Configuration Register */
\r
2075 int32_t ME_reserved3[2];
\r
2081 vuint32_t S_FLEXCAN5:1;
\r
2082 vuint32_t S_FLEXCAN4:1;
\r
2083 vuint32_t S_FLEXCAN3:1;
\r
2084 vuint32_t S_FLEXCAN2:1;
\r
2085 vuint32_t S_FLEXCAN1:1;
\r
2086 vuint32_t S_FLEXCAN0:1;
\r
2088 vuint32_t S_DSPI2:1;
\r
2089 vuint32_t S_DSPI1:1;
\r
2090 vuint32_t S_DSPI0:1;
\r
2093 } PS0; /* Peripheral Status Register 0 */
\r
2099 vuint32_t S_CANSAMPLER:1;
\r
2101 vuint32_t S_CTU:1;
\r
2103 vuint32_t S_LINFLEX3:1;
\r
2104 vuint32_t S_LINFLEX2:1;
\r
2105 vuint32_t S_LINFLEX1:1;
\r
2106 vuint32_t S_LINFLEX0:1;
\r
2108 vuint32_t S_I2C:1;
\r
2110 vuint32_t S_ADC:1;
\r
2112 } PS1; /* Peripheral Status Register 1 */
\r
2118 vuint32_t S_PIT_RTI:1;
\r
2119 vuint32_t S_RTC_API:1;
\r
2121 vuint32_t S_EMIOS:1;
\r
2123 vuint32_t S_WKUP:1;
\r
2124 vuint32_t S_SIU:1;
\r
2127 } PS2; /* Peripheral Status Register 2 */
\r
2133 vuint32_t S_CMU:1;
\r
2136 } PS3; /* Peripheral Status Register 3 */
\r
2138 int32_t ME_reserved4[4];
\r
2151 vuint32_t RESET:1;
\r
2153 } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
\r
2159 vuint32_t STANDBY0:1;
\r
2161 vuint32_t STOP0:1;
\r
2163 vuint32_t HALT0:1;
\r
2166 } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
\r
2173 vuint8_t LP_CFG:3;
\r
2174 vuint8_t RUN_CFG:3;
\r
2176 } PCTL[144]; /* Peripheral Control 0->143 Register */
\r
2178 }; /* end of ME_tag */
\r
2179 /****************************************************************************/
\r
2180 /* MODULE : MPU */
\r
2181 /****************************************************************************/
\r
2186 vuint32_t SPERR:8;
\r
2194 } CESR; /* Module Control/Error Status Register */
\r
2196 uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
\r
2201 vuint32_t EADDR:32;
\r
2208 vuint32_t EACD:16;
\r
2211 vuint32_t EATTR:3;
\r
2219 vuint32_t EADDR:32;
\r
2226 vuint32_t EACD:16;
\r
2229 vuint32_t EATTR:3;
\r
2237 vuint32_t EADDR:32;
\r
2244 vuint32_t EACD:16;
\r
2247 vuint32_t EATTR:3;
\r
2255 vuint32_t EADDR:32;
\r
2262 vuint32_t EACD:16;
\r
2265 vuint32_t EATTR:3;
\r
2270 uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
\r
2276 vuint32_t SRTADDR:27;
\r
2279 } WORD0; /* Region Descriptor n Word 0 */
\r
2284 vuint32_t ENDADDR:27;
\r
2287 } WORD1; /* Region Descriptor n Word 1 */
\r
2313 } WORD2; /* Region Descriptor n Word 2 */
\r
2319 vuint32_t PIDMASK:8;
\r
2323 } WORD3; /* Region Descriptor n Word 3 */
\r
2327 uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
\r
2353 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
\r
2355 }; /* end of MPU_tag */
\r
2356 /****************************************************************************/
\r
2357 /* MODULE : PCU */
\r
2358 /****************************************************************************/
\r
2365 vuint32_t STBY0:1;
\r
2367 vuint32_t STOP0:1;
\r
2369 vuint32_t HALT0:1;
\r
2379 } PCONF[3]; /* Power domain 0-2 configuration register */
\r
2381 int32_t PCU_reserved0[13]; /* (0x040 - 0x00C)/4 = 0x0D */
\r
2391 } PSTAT; /* Power Domain Status Register */
\r
2393 int32_t PCU_reserved1[15]; /* {0x0080-0x0044}/0x4 = 0xF */
\r
2399 vuint32_t MASK_LVDHV5:1;
\r
2401 } VCTL; /* Voltage Regulator Control Register */
\r
2403 }; /* end of PCU_tag */
\r
2404 /****************************************************************************/
\r
2405 /* MODULE : pit */
\r
2406 /****************************************************************************/
\r
2417 uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
\r
2452 }; /* end of PIT_tag */
\r
2453 /****************************************************************************/
\r
2454 /* MODULE : RGM */
\r
2455 /****************************************************************************/
\r
2461 vuint16_t F_EXR:1;
\r
2463 vuint16_t F_FLASH:1;
\r
2464 vuint16_t F_LVD45:1;
\r
2465 vuint16_t F_CMU_FHL:1;
\r
2466 vuint16_t F_CMU_OLR:1;
\r
2467 vuint16_t F_FMPLL:1;
\r
2468 vuint16_t F_CHKSTOP:1;
\r
2469 vuint16_t F_SOFT:1;
\r
2470 vuint16_t F_CORE:1;
\r
2471 vuint16_t F_JTAG:1;
\r
2473 } FES; /* Functional Event Status */
\r
2478 vuint16_t F_POR:1;
\r
2480 vuint16_t F_LVD27:1;
\r
2481 vuint16_t F_SWT:1;
\r
2482 vuint16_t F_LVD12_PD1:1;
\r
2483 vuint16_t F_LVD12_PD0:1;
\r
2485 } DES; /* Destructive Event Status */
\r
2490 vuint16_t D_EXR:1;
\r
2492 vuint16_t D_FLASH:1;
\r
2493 vuint16_t D_LVD45:1;
\r
2494 vuint16_t D_CMU_FHL:1;
\r
2495 vuint16_t D_CMU_OLR:1;
\r
2496 vuint16_t D_FMPLL:1;
\r
2497 vuint16_t D_CHKSTOP:1;
\r
2498 vuint16_t D_SOFT:1;
\r
2499 vuint16_t D_CORE:1;
\r
2500 vuint16_t D_JTAG:1;
\r
2502 } FERD; /* Functional Event Reset Disable */
\r
2507 vuint16_t D_POR:1;
\r
2509 vuint16_t D_LVD27:1;
\r
2510 vuint16_t D_SWT:1;
\r
2511 vuint16_t D_LVD12_PD1:1;
\r
2512 vuint16_t D_LVD12_PD0:1;
\r
2514 } DERD; /* Destructive Event Reset Disable */
\r
2516 int16_t RGM_reserved0[4];
\r
2521 vuint16_t AR_EXR:1;
\r
2523 vuint16_t AR_FLASH:1;
\r
2524 vuint16_t AR_LVD45:1;
\r
2525 vuint16_t AR_CMU_FHL:1;
\r
2526 vuint16_t AR_CMU_OLR:1;
\r
2527 vuint16_t AR_FMPLL:1;
\r
2528 vuint16_t AR_CHKSTOP:1;
\r
2529 vuint16_t AR_SOFT:1;
\r
2530 vuint16_t AR_CORE:1;
\r
2531 vuint16_t AR_JTAG:1;
\r
2533 } FEAR; /* Functional Event Alternate Request */
\r
2539 vuint16_t AR_LVD27:1;
\r
2540 vuint16_t AR_SWT:1;
\r
2541 vuint16_t AR_LVD12_PD1:1;
\r
2542 vuint16_t AR_LVD12_PD0:1;
\r
2544 } DEAR; /* Destructive Event Alternate Request */
\r
2546 int16_t RGM_reserved1[2];
\r
2552 vuint16_t SS_LVD45:1;
\r
2553 vuint16_t SS_CMU_FHL:1;
\r
2554 vuint16_t SS_CMU_OLR:1;
\r
2555 vuint16_t SS_PLL:1;
\r
2556 vuint16_t SS_CHKSTOP:1;
\r
2557 vuint16_t SS_SOFT:1;
\r
2558 vuint16_t SS_CORE:1;
\r
2559 vuint16_t SS_JTAG:1;
\r
2561 } FESS; /* Functional Event Short Sequence */
\r
2567 vuint16_t BOOT_FROM_BKP_RAM:1;
\r
2570 } STDBY; /* STANDBY reset sequence */
\r
2575 vuint16_t BE_EXR:1;
\r
2577 vuint16_t BE_FLASH:1;
\r
2578 vuint16_t BE_LVD45:1;
\r
2579 vuint16_t BE_CMU_FHL:1;
\r
2580 vuint16_t BE_CMU_OLR:1;
\r
2581 vuint16_t BE_FMPLL:1;
\r
2582 vuint16_t BE_CHKSTOP:1;
\r
2583 vuint16_t BE_SOFT:1;
\r
2584 vuint16_t BE_CORE:1;
\r
2585 vuint16_t BE_JTAG:1;
\r
2587 } FBRE; /* Functional Bidirectional Reset Enable */
\r
2589 }; /* end of RGM_tag */
\r
2590 /****************************************************************************/
\r
2591 /* MODULE : RTC */
\r
2592 /****************************************************************************/
\r
2600 } RTCSUPV; /* RTC Supervisor Control Register */
\r
2605 vuint32_t CNTEN:1;
\r
2606 vuint32_t RTCIE:1;
\r
2607 vuint32_t FRZEN:1;
\r
2608 vuint32_t ROVREN:1;
\r
2609 vuint32_t RTCVAL:12;
\r
2610 vuint32_t APIEN:1;
\r
2611 vuint32_t APIIE:1;
\r
2612 vuint32_t CLKSEL:2;
\r
2613 vuint32_t DIV512EN:1;
\r
2614 vuint32_t DIV32EN:1;
\r
2615 vuint32_t APIVAL:10;
\r
2617 } RTCC; /* RTC Control Register */
\r
2627 vuint32_t ROVRF:1;
\r
2630 } RTCS; /* RTC Status Register */
\r
2635 vuint32_t RTCCNT:32;
\r
2637 } RTCCNT; /* RTC Counter Register */
\r
2639 }; /* end of RTC_tag */
\r
2640 /****************************************************************************/
\r
2641 /* MODULE : SIU */
\r
2642 /****************************************************************************/
\r
2645 int32_t SIU_reserved0; /* {0x004-0x000}/4 = 0x01 */
\r
2647 union { /* MCU ID Register 1 */
\r
2650 vuint32_t PARTNUM:16;
\r
2654 vuint32_t MAJOR_MASK:4;
\r
2655 vuint32_t MINOR_MASK:4;
\r
2659 union { /* MCU ID Register 2 */
\r
2663 vuint32_t FLASH_SIZE_1:4;
\r
2664 vuint32_t FLASH_SIZE_2:4;
\r
2666 vuint32_t PARTNUM:8;
\r
2673 int32_t SIU_reserved1[2]; /* {0x014-0x00C}/4 = 0x02 */
\r
2675 union { /* Interrupt Status Flag Register */
\r
2679 vuint32_t EIF15:1;
\r
2680 vuint32_t EIF14:1;
\r
2681 vuint32_t EIF13:1;
\r
2682 vuint32_t EIF12:1;
\r
2683 vuint32_t EIF11:1;
\r
2684 vuint32_t EIF10:1;
\r
2698 union { /* Interrupt Request Enable Register */
\r
2702 vuint32_t EIRE15:1;
\r
2703 vuint32_t EIRE14:1;
\r
2704 vuint32_t EIRE13:1;
\r
2705 vuint32_t EIRE12:1;
\r
2706 vuint32_t EIRE11:1;
\r
2707 vuint32_t EIRE10:1;
\r
2708 vuint32_t EIRE9:1;
\r
2709 vuint32_t EIRE8:1;
\r
2710 vuint32_t EIRE7:1;
\r
2711 vuint32_t EIRE6:1;
\r
2712 vuint32_t EIRE5:1;
\r
2713 vuint32_t EIRE4:1;
\r
2714 vuint32_t EIRE3:1;
\r
2715 vuint32_t EIRE2:1;
\r
2716 vuint32_t EIRE1:1;
\r
2717 vuint32_t EIRE0:1;
\r
2721 int32_t SIU_reserved2[3]; /* {0x028-0x01C}/4 = 0x03 */
\r
2723 union { /* Interrupt Rising-Edge Event Enable Register */
\r
2727 vuint32_t IREE15:1;
\r
2728 vuint32_t IREE14:1;
\r
2729 vuint32_t IREE13:1;
\r
2730 vuint32_t IREE12:1;
\r
2731 vuint32_t IREE11:1;
\r
2732 vuint32_t IREE10:1;
\r
2733 vuint32_t IREE9:1;
\r
2734 vuint32_t IREE8:1;
\r
2735 vuint32_t IREE7:1;
\r
2736 vuint32_t IREE6:1;
\r
2737 vuint32_t IREE5:1;
\r
2738 vuint32_t IREE4:1;
\r
2739 vuint32_t IREE3:1;
\r
2740 vuint32_t IREE2:1;
\r
2741 vuint32_t IREE1:1;
\r
2742 vuint32_t IREE0:1;
\r
2746 union { /* Interrupt Falling-Edge Event Enable Register */
\r
2750 vuint32_t IFEE15:1;
\r
2751 vuint32_t IFEE14:1;
\r
2752 vuint32_t IFEE13:1;
\r
2753 vuint32_t IFEE12:1;
\r
2754 vuint32_t IFEE11:1;
\r
2755 vuint32_t IFEE10:1;
\r
2756 vuint32_t IFEE9:1;
\r
2757 vuint32_t IFEE8:1;
\r
2758 vuint32_t IFEE7:1;
\r
2759 vuint32_t IFEE6:1;
\r
2760 vuint32_t IFEE5:1;
\r
2761 vuint32_t IFEE4:1;
\r
2762 vuint32_t IFEE3:1;
\r
2763 vuint32_t IFEE2:1;
\r
2764 vuint32_t IFEE1:1;
\r
2765 vuint32_t IFEE0:1;
\r
2769 union { /* Interrupt Filter Enable Register */
\r
2773 vuint32_t IFE15:1;
\r
2774 vuint32_t IFE14:1;
\r
2775 vuint32_t IFE13:1;
\r
2776 vuint32_t IFE12:1;
\r
2777 vuint32_t IFE11:1;
\r
2778 vuint32_t IFE10:1;
\r
2792 int32_t SIU_reserved3[3]; /* {0x040-0x034}/4 = 0x03 */
\r
2794 union { /* Pad Configuration Registers */
\r
2813 int32_t SIU_reserved4[242]; /* {0x500-0x136}/0xF2 */
\r
2815 union { /* Pad Selection for Multiplexed Input Register */
\r
2819 vuint8_t PADSEL:4;
\r
2823 int32_t SIU_reserved5[56]; /* {0x600-0x520}/4 = 0x38 */
\r
2825 union { /* GPIO Pin Data Output Registers */
\r
2833 int32_t SIU_reserved6[97]; /* {0x800-0x67C}/4 = 0x61 */
\r
2835 union { /* GPIO Pin Data Input Registers */
\r
2843 int32_t SIU_reserved7[225]; /* {0xC00-0x87C}/0x4 = 0xE1 */
\r
2845 union { /* Parallel GPIO Pin Data Output Register */
\r
2848 vuint32_t PPD0:32;
\r
2852 int32_t SIU_reserved8[12]; /* {0xC40-0xC10}/0x4 = 0x0C */
\r
2854 union { /* Parallel GPIO Pin Data Input Register */
\r
2857 vuint32_t PPDI:32;
\r
2861 int32_t SIU_reserved9[12]; /* {0xC80-0xC50}/0x4 = 0x0C */
\r
2863 union { /* Masked Parallel GPIO Pin Data Out Register */
\r
2866 vuint32_t MASK:16;
\r
2867 vuint32_t MPPDO:16;
\r
2871 int32_t SIU_reserved10[216]; /* {0x1000-0x0CA0}/4 = 0xD8 */
\r
2873 union { /* Interrupt Filter Maximum Counter Register */
\r
2877 vuint32_t MAXCNT:4;
\r
2881 int32_t SIU_reserved11[16]; /* {0x1080-0x1040}/4 = 0x10 */
\r
2883 union { /* Interrupt Filter Clock Prescaler Register */
\r
2891 }; /* end of SIU_tag */
\r
2892 /****************************************************************************/
\r
2893 /* MODULE : SSCM */
\r
2894 /****************************************************************************/
\r
2902 vuint16_t BMODE:3;
\r
2907 } STATUS; /* Status Register */
\r
2912 vuint16_t SRAM_SIZE:5;
\r
2918 } MEMCONFIG; /* System Memory Configuration Register */
\r
2920 int16_t SSCM_reserved;
\r
2929 } ERROR; /* Error Configuration Register */
\r
2931 int16_t SSCM_reserved1[2];
\r
2936 vuint32_t PWD_HI:32;
\r
2938 } PWCMPH; /* Password Comparison Register High Word */
\r
2943 vuint32_t PWD_LO:32;
\r
2945 } PWCMPL; /* Password Comparison Register Low Word */
\r
2947 }; /* end of SSCM_tag */
\r
2948 /****************************************************************************/
\r
2949 /* MODULE : STM */
\r
2950 /****************************************************************************/
\r
2951 struct STM_CHANNEL_tag {
\r
2959 } CCR; /* STM Channel Control Register */
\r
2967 } CIR; /* STM Channel Interrupt Register */
\r
2971 } CMP; /* STM Channel Compare Register 0 */
\r
2973 int32_t STM_CHANNEL_reserved;
\r
2975 }; /* end of STM_CHANNEL_tag */
\r
2988 } CR; /* STM Control Register */
\r
2992 } CNT; /* STM Count Register */
\r
2994 int32_t STM_reserved[2];
\r
2996 struct STM_CHANNEL_tag CH[4];
\r
2998 }; /* end of STM_tag */
\r
2999 /****************************************************************************/
\r
3000 /* MODULE : SWT */
\r
3001 /****************************************************************************/
\r
3025 } CR; /* SWT Control Register */
\r
3033 } IR; /* SWT Interrupt Register */
\r
3040 } TO; /* SWT Time-Out Register */
\r
3047 } WN; /* SWT Window Register */
\r
3055 } SR; /* SWT Service Register */
\r
3062 } CO; /* SWT Counter Output Register */
\r
3064 }; /* end of SWT_tag */
\r
3065 /****************************************************************************/
\r
3066 /* MODULE : WKUP */
\r
3067 /****************************************************************************/
\r
3073 vuint32_t NOVF0:1;
\r
3076 } NSR; /* NMI Status Register */
\r
3078 int32_t WKUP_reserved;
\r
3083 vuint32_t NLOCK:1;
\r
3092 } NCR; /* NMI Configuration Register */
\r
3094 int32_t WKUP_reserved1[2];
\r
3102 } WISR; /* Wakeup/Interrupt Status Flag Register */
\r
3108 vuint32_t EIRE:20;
\r
3110 } IRER; /* Interrupt Request Enable Register */
\r
3118 } WRER; /* Wakeup Request Enable Register */
\r
3120 int32_t WKUP_reserved2[2];
\r
3126 vuint32_t IREE:20;
\r
3128 } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
\r
3134 vuint32_t IFEE:20;
\r
3136 } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
\r
3144 } WIFER; /* Wakeup/Interrupt Filter Enable Register */
\r
3150 vuint32_t IPUE:20;
\r
3152 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
\r
3154 }; /* end of WKUP_tag */
\r
3155 /******************************************************************
\r
3156 | defines and macros (scope: module-local)
\r
3157 |-----------------------------------------------------------------*/
\r
3158 /* Define instances of modules */
\r
3159 #define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL)
\r
3160 #define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
\r
3161 #define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
\r
3162 #define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
\r
3163 #define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
\r
3164 #define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
\r
3165 #define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
\r
3166 #define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
\r
3167 #define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
\r
3168 #define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
\r
3169 #define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
\r
3170 #define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
\r
3171 #define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
\r
3172 #define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
\r
3173 #define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
\r
3174 #define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
\r
3175 #define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
\r
3176 #define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
\r
3177 #define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
\r
3178 #define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL)
\r
3179 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
\r
3180 #define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
\r
3181 #define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
\r
3182 #define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
\r
3183 #define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
\r
3184 #define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
\r
3185 #define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
\r
3186 #define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
\r
3187 #define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
\r
3188 #define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
\r
3189 #define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
\r
3190 #define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
\r
3191 #define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
\r
3192 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
\r
3193 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
\r
3194 #define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
\r
3201 #ifdef __cplusplus
\r
3206 #endif /* ifdef _MPC5604B_H */
\r
3208 /* End of file */
\r
projects / arc.git / blob