net: zynq: gem: Use hardware assisted system time stamping
Since the hardware frequency adjustment is complex,using software
method to do that.
In this mode, PTP packets are still time stamped by the NIC, but the clock
which is controlled by PTPd is the system time. For this to work, the time
stamps generated inside the NIC are transformed into system time before
feeding them into the normal PTPd machinery: each time a NIC time stamp is
extracted from the NIC, the NIC system time offset is measured and added to
the NIC time stamp to obtain the corresponding system time stamp.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Fri, 16 May 2014 11:11:37 +0000 (16:41 +0530)]
i2c: cadence: Handle > 252 byte transfers
The I2C controller sends a NACK to the slave when transfer size register
reaches zero, irrespective of the hold bit. So, in order to handle transfers
greater than 252 bytes, the transfer size register has to be maintained at a
value >= 1. This patch implements the same.
The interrupt status is cleared at the beginning of the isr instead of
the end, to avoid missing any interrupts - this is in sync with the new
transfer handling.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "media: xilinx: dma: Workaround for bytesperline"
This reverts commit b4859c939e1febb638e23accc1c3a66b72e10ccc.
Zynq Base TRD LogiCVC DRM integration requires programming
bytesperline field i.e stride is not same as width.
So we need to get rid of this workaround and send mplayer
fix to its mailing list.
Soren Brinkmann [Wed, 14 May 2014 21:43:04 +0000 (14:43 -0700)]
ARM: zynq: DT: Migrate UART to Cadence binding
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit 271b35d5c200d69d5fb317a976c8f24383c929a7)
Soren Brinkmann [Wed, 14 May 2014 21:43:03 +0000 (14:43 -0700)]
tty: cadence: Document DT binding
Add binding documentation for the Cadence UART.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit 09b6771798f262bedba51bbb66027564b0ff226e)
Soren Brinkmann [Wed, 14 May 2014 21:43:02 +0000 (14:43 -0700)]
tty: xuartps: Rebrand driver as Cadence UART
Zynq's UART is Cadence IP. Make this visible in the prompt in kconfig
and additional comments in the driver.
This also renames functions and symbols, as far as possible without
breaking user space API, to reflect the Cadence origin. This is achieved
through simple search and replace:
- s/XUARTPS/CDNS_UART/g
- s/xuartps/cdns_uart/g
The only exceptions are PORT_XUARTPS and the driver name, which stay as is,
due to their exposure to user space. As well as the - no legacy -
compatibility string 'xlnx,xuartps'
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit d9bb3fb12685209765fd838bec69d701d7b479e5) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Wed, 14 May 2014 21:43:01 +0000 (14:43 -0700)]
tty: xuartps: Don't write IRQ disable register to enable interrupts
A comment states, that, according to the data sheet, to enable
interrupts the disable register should be written, but the enable
register could be left untouched. And it suspsects a HW bug requiring
to write both.
Reviewing the data sheet, these statements seem wrong. Just as one would
expect. Writing to the enable/disable register enables/disables
interrupts.
Hence the misleading comment and needless write to the disable register
are removed from the enable sequence.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit b494a5fae452fc43519872565892fa873f6ea4fb) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Wed, 14 May 2014 21:43:00 +0000 (14:43 -0700)]
tty: xuartps: Refactor read-modify-writes
A lot of read-modify-write sequences used a one-line statement which
nests a readl() within a writel(). Convert this into code sequences that
make the three steps more obvious.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 35dc5a538fb54bc30bdedf4c825da5c970b5ff90) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Wed, 14 May 2014 21:42:59 +0000 (14:42 -0700)]
tty: xuartps: Print warning in clock notifier
Print a warning if the clock notifier rejects a clock frequency change
to facilitate debugging (see:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/304329/focus=304379)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 5ce15d2d1efb9cacab9a331c730cc805124ee612) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 14 May 2014 21:42:57 +0000 (14:42 -0700)]
tty: xuartps: Initialize ports according to aliases
Register port numbers according to order in DT aliases.
If aliases are not defined, order in DT is used.
If aliases are defined, register port id based
on that.
This patch ensures proper ttyPS0/1 assignment.
[soren]: Combined integer declarations in probe(), removed warning message
if no alias is found.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 928e9263492069eeebb4c867b841508837895e0e)
Soren Brinkmann [Sun, 4 May 2014 22:43:02 +0000 (15:43 -0700)]
net: macb: Fix race between HW and driver
Under "heavy" RX load, the driver cannot handle the descriptors fast
enough. In detail, when a descriptor is consumed, its used flag is
cleared and once the RX budget is consumed all descriptors with a
cleared used flag are prepared to receive more data. Under load though,
the HW may constantly receive more data and use those descriptors with a
cleared used flag before they are actually prepared for next usage.
The head and tail pointers into the RX-ring should always be valid and
we can omit clearing and checking of the used flag.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Soren Brinkmann [Sun, 4 May 2014 22:43:01 +0000 (15:43 -0700)]
net: macb: Remove 'unlikely' optimization
Coverage data suggests that the unlikely case of receiving data while
the receive handler is running may not be that unlikely.
Coverage data after running iperf for a while:
91320: 891: work_done = bp->macbgem_ops.mog_rx(bp, budget);
91320: 892: if (work_done < budget) {
2362: 893: napi_complete(napi);
-: 894:
-: 895: /* Packets received while interrupts were disabled */
4724: 896: status = macb_readl(bp, RSR);
2362: 897: if (unlikely(status)) {
762: 898: if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
762: 899: macb_writel(bp, ISR, MACB_BIT(RCOMP));
-: 900: napi_reschedule(napi);
-: 901: } else {
1600: 902: macb_writel(bp, IER, MACB_RX_INT_FLAGS);
-: 903: }
-: 904: }
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Soren Brinkmann [Sun, 4 May 2014 22:42:59 +0000 (15:42 -0700)]
net: macb: Clear interrupt flags
A few interrupt flags were not cleared in the ISR, resulting in a sytem
trapped in the ISR in cases one of those interrupts occurred. Clear all
flags to avoid such situations.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Soren Brinkmann [Sun, 4 May 2014 22:42:58 +0000 (15:42 -0700)]
net: macb: Pass same size to DMA_UNMAP as used for DMA_MAP
Just as commit "net: macb: DMA-unmap full rx-buffer"
(48330e08fa168395b9fd9f369f06cca1df204361), pass the size that
was used for mapping the memory also to the unmap routine to
avoid warnings from the DMA_API.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Value of "maxpacket_limit" should be set in UDC driver probe function, using
usb_ep_set_maxpacket_limit() function, defined in gadget.h. This function
set choosen value to both "maxpacket_limit" and "maxpacket" fields.
Michal Simek [Fri, 11 Apr 2014 13:05:56 +0000 (15:05 +0200)]
ARM: zynq: Enable big-endian
Enable ARCH_SUPPORTS_BIG_ENDIAN in Kconfig.
zynq_secondary_trampoline is the first function
that is called on secondary CPU.
Reference:
"ARM: mcpm: fix big endian issue in mcpm startup code"
(sha1: 519ceb9fd10cd7e836d0aa97b2068cc9e97f463b)
Michal Simek [Fri, 11 Apr 2014 13:36:06 +0000 (15:36 +0200)]
net: zynq: gem: Use readl/writel_relaxed instead of __raw
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.
Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3473115ac7df3fe19bd2502149d8c51)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 11 Apr 2014 13:39:29 +0000 (15:39 +0200)]
clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.
Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3473115ac7df3fe19bd2502149d8c51)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:40 +0000 (19:52 -0700)]
Documentation: devicetree: bindings: drm: xilinx: Add the connector type
Add the connector type property in the node. User can specify the type of
connector to use, and the value is used to initialize the drm connector in
the connector driver.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:39 +0000 (19:52 -0700)]
drm: xilinx: connector: Configure the type from DT property
The connector can be either HDMI or DisplayPort depending on which encoder
slave is used. Add the struct xilinx_drm_connector_type to have supported
connector types, and decide the type based on DT.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:36 +0000 (19:52 -0700)]
drm: xilinx: encoder: Initialize the drm encoder before the encoder slave
drm_encoder_init() and drm_encoder_helper_add() need to be called before
initializing the encoder slave. The encoder slave can generate interrupts
right after initalization, which may result in error from not initialized
drm device.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:35 +0000 (19:52 -0700)]
drm: xilinx: encoder: Support encoder slaves on a platform bus
The Xilinx display pipeline can have encoder slaves on a platform bus,
so encoder slaves on a platform bus support is added in addition to
i2c encoder slaves.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:33 +0000 (19:52 -0700)]
drm: platform encoder driver support
Add struct drm_platform_encoder_driver. This structure can be used for
the encoder slave drivers on a platform bus. The i2c specific assumption
better be removed, and other drm encoder slave interfaces would be updated
to be more generic.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:30 +0000 (19:52 -0700)]
drm: adv7511: Add adv7511_encoder_mode_valid() function
Add adv7511_encoder_mode_valid() function. This valid check code was
implemented in the drm connector driver, but this check should be done in
the adv7511 driver.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:29 +0000 (19:52 -0700)]
drm: xilinx: encoder: Remove dependency on adv7511
The previous adv7511 patch moves the dependency code to inside the adv7511
driver. This makes the xilinx encoder more generic to have other encoders.
Do not call encoder_sfuncs->set_config() when a mode is set, as the adv7511
driver handles it internally.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:28 +0000 (19:52 -0700)]
drm: adv7511: Configure adv7511 with default values
This patch adds adv7511_set_default_config() which configures adv7511 device
with default values. This configuration can be overwritten with custom values
when client driver calls adv7511_set_config() explicitly.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 6 May 2014 02:52:27 +0000 (19:52 -0700)]
drm: adv7511: Add the rgb format flag to adv7511_link_config
Add the rgb format boolean flag to struct adv7511_link_config. This was in
the drm encoder driver, but having it in the adv7511 driver would remove
direct dependency. The flag is copied to the struct adv7511 to be used for
the transmitter configuration.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Only insert a delayed disconnected event when we transition from connected to
connect. If we transition from disconnected to connected there is no need for
this since the system will already assume that the monitor was disconnected.
DRM: adv7511: Properly initialize dpms_mode and status
Set dpms_mode to DRM_MODE_DPMS_OFF and status to connector_status_disconnected
to make sure that they match the state of the chip. This fixes an issue where
the monitor was incorrectly reported as disconnected during cold boot.
Harini Katakam [Mon, 5 May 2014 09:33:14 +0000 (15:03 +0530)]
spi: zynq-qspi: Dont write more than requested bytes to rxbuf
In case of dual parallel odd byte transfer, write even bytes and
read bytes accordingly but write only the requested number of bytes to rxbuf.
Otherwise any user data adjacent to rxbuf might be corrupted.
Improve related comments.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 1 May 2014 16:36:39 +0000 (09:36 -0700)]
ARM: zynq: Synchronise zynq_cpu_die/kill
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1: 2f3edfd7e27ad4206acbc2ae99c9df5f46353024)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 1 May 2014 16:36:36 +0000 (09:36 -0700)]
ARM: zynq: Remove redundant code from hotplug
When secondary cores are hotplugged, their reset gets asserted and cache
operations are handled in the core. Due to most of the Zynq's
arch-specific hotplug code can be removed.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add xilinx compatible string along with cadence.
Compatible string should be first in the node.
Make num-cs optional property.
Add is-decoded-cs property.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:07 +0000 (14:59 +0530)]
spi: cadence: Chip select related changes
Change chip select property name to "num-cs". Use a default value
instead of giving error when num-cs is not found.
Add "is-decoded-cs" property for using extended slave select; make
necessary changes in cdns_spi_chipselect function.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:06 +0000 (14:59 +0530)]
spi: cadence: Suspend/Resume cleanup
Remove use of driver state in probe, suspend, resume and prep_transfer_hw.
Just call master suspend/resume and disable_unprepare or prepare_enable clocks
as required in suspend/resume.
Remove debug prints in suspend/resume.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:05 +0000 (14:59 +0530)]
spi: cadence: setup cleanup
Make CPOL/CPHA configuration a separate function. Since these dont vary
between transfers and need to be set when preparing hw before enabling spi,
call from prep_transfer_hw.
Remove spi_setup as this is no longer required.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:04 +0000 (14:59 +0530)]
spi: cadence: Use transfer_one hook
Implement transfer_one and set_cs functions. Change initialization, completion
and irq handling accordingly. Remove timeout check as core does this.
Remove reset function as it is no longer used.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:03 +0000 (14:59 +0530)]
spi: cadence: Make register read and write operations static inline functions
Make cdns_spi_read and cdns_spi_write static inline functions which
take driver instance pointer, offset, data as inputs and perform necessary
read/write operation.
Modify init_hw function to pass instance pointer instead of register base address.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:02 +0000 (14:59 +0530)]
spi: cadence: irq related cleanup
Request irq after init_hw in probe.
Check for irq<=0 as 0 is also considered error condition.
Return IRQ_HANDLED only when interrupt is handled, otherwise return IRQ_NONE.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:00 +0000 (14:59 +0530)]
spi: cadence: Use max speed checks in the core
Set master->max_speed_hz to let core perform necessary checks.
Remove checks in the driver.
If transfer speed is requested as zero after checks in the core,
dont set max speed, default to min speed.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 May 2014 14:03:55 +0000 (16:03 +0200)]
tty: serial: uartlite: Specify time for sending chars
Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.
Make this time delay not to be cpu speed dependent.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
media: xilinx: dma: Stop entity chain walk at the entity with no sink pad
When starting or stopping the pipeline, the pipeline driver walks
the entities chain, and starts or stops all of them. When the walk reaches
the entity with no sink pad, walk needs to stop. xvip_get_entity_sink()
returns either the valid sink pad, or NULL when the entity doesn't have any
sink pad. When NULL is returned, stop the walk.
drm: i2c: adv7511: Initialize the DPMS value in adv7511_probe()
Initialize the DPMS value to DRM_MODE_DPMS_OFF in adv7511_probe() function.
Otherwise, the value is set to DRM_MODE_DPMS_ON(=0) which doesn't reflect
the actual device's DPMS state. This also results in not turning on
the device properly.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: drv: Set bpp and color depth to drm_framebuffer
The drm crtc helper doesn't set bpp and color depth for non RGB format
drm_framebuffer, and that results in not supporting YUV format planes
properly. This patch fixes and the YUV format drm_framebuffer can be allocated
and used for planes.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: drv: Add color depth info to the format descriptor
Add color depth info to the the format descriptor. xilinx_drm_format_depth()
can be used to retrieve the color depth value corresponding to the given drm
format code.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 18 Mar 2014 16:18:13 +0000 (09:18 -0700)]
media: xilinx: dma: Change vdma configuration to cyclic-mode
VDMA in non-cyclic mode doesn't work with fsync enabled. Fsync is needed
to synchronize the pipeline with external input. So VDMA is configured to
cyclic mode in this patch, with fsync enabled at synthesis. This patch is
the only way to run the pipeline with external input, and it will be
revisited after IP level investigation.
net: xilinx_emacps: Release receive BDs when there is a resource error
Driver should clean/release the BDs when it detects a resource error to
ensure the proper cleanup and allow the controller to recover from rx
lockdown issue.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Changes to support dual parallel in new driver implementation
This patch implements support for dual parallel on top of the recent changes
to qspi driver which implements transfer->one.
In parallel configuration, all commands are sent to both flash devices but
the data is split into odd and even bits between lower and upper flash.
As a result of this data should be of even length for write/read operations.
For Ex.,
A program operation for 3 bytes will ideally be:
CMD + 3 ADDR BYTES + 3 DATA BYTES
In dual parallel case, this means 8 + 24 + (3*8/2) = 44 clock cycles will be sent.
From the flash perspective, it only received 1 and 1/2 bytes' cycles.
To avoid this error, when odd number of data bytes are asked to be transmitted,
an extra byte is sent to compensate for the nibble flash devices will be expecting.
Checks for bytes_to_receive/transmit < 0 were removed where not required.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In the changed m25p80.c from mainline, quad read opcode is set based on
flags in device table. This also takes care of dummy bytes. Make use of this.
Added this flag to all devices known to support quad read.
Updated m25p80.c from mainline calls spansion_quad_enable by default
when quad mode is supported. This command is only required (supported)
for spansion and winbond. Even in that case, it's a non-volatile setting.
This implementation is not guaranteed to work when flash devices are
connected in parallel/stacked configuration.
Hence remove it and revisit if required.
Updated m25p80.c from mainline uses "mode" in spi device structure to
select quad read. This, in turn, is set by spi core based on dts properties.
Hence, update tx and rx bus width in dts for above purpose.
The flags M25P80_QUAD_READ and SECT_32 both have the same value - correct this.
Remove unused variables in flash structure.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration of U_PAGE/L_PAGE before asserting chip select.
(This was removed earlier when subsystem workqueue, set_cs and transfer_one
hooks were used)
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The existing timeout value in wait_for_completion_timeout is
calculated from the transfer length and speed with tolerance of 10msec.
This is too low because this is used for error conditions such as
hardware hang etc.
The xfer->speed_hz considered may not be the actual speed set
because the best clock divisor is chosen from a limited set such that
the actual speed <= requested speed. This will lead to timeout being
less than actual transfer time.
Considering acceptable latencies, this timeout can be set to a
value double the expected transfer plus 100 msecs.
This patch adds the same in the core.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
clocksource/cadence_ttc: Adjust timer frequency on clock changes
Implement a clock notifier to handle changes of the timer's input clock
frequency.
This syncs up the driver with mainline squashing the following commits
into this one:
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clocksource/cadence_ttc: Call clockevents_update_freq() with IRQs enabled
The timer core takes care of serialization and IRQs. Hence the driver is
no longer required to disable interrupts when calling
clockevents_update_freq().
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit 5f0ba3b462b2d36b3c28748863747fb1050f40d0)
clocksource/cadence_ttc: Overhaul clocksource frequency adjustment
The currently used method adjusting the clocksource to a changing input
frequency does not work on kernels from 3.11 on.
The new approach is to keep the timer frequency as constant as possible.
I.e.
- due to the TTC's prescaler limitations, allow frequency changes
only if the frequency scales by a power of 2
- adjust the counter's divider on the fly when a frequency change
occurs
This limits cpufreq to scale by certain factors only.
But we may keep the time base somewhat constant, so that sleep() & co
keep working as expected, while supporting cpufreq.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit b3e90722f6f53fa457a88146a877e34ea71d25ea)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
clockevents: Adjust timer interval when frequency changes
clockevent devices in periodic mode are not updated when the frequency
of the device changes. Issue a dev->set_mode() callback which forces
the device to reevaluate the timer settings.
Thomas Gleixner [Fri, 11 Apr 2014 16:24:01 +0000 (09:24 -0700)]
clockevents: Serialize calls to clockevents_update_freq() in the core
We can identify the broadcast device in the core and serialize all
callers including interrupts on a different CPU against the update.
Also, disabling interrupts is moved into the core allowing callers to
leave interrutps enabled when calling clockevents_update_freq().
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Michal Simek <michal.simek@xilinx.com> Link: http://lkml.kernel.org/r/1391466877-28908-2-git-send-email-soren.brinkmann@xilinx.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 627ee7947e2e83ba565c31c5c9373d6e364b1ecd) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use the name pclk instead of aper_clk and change the variable name accordingly.
Change variable name from devclk to refclk just for clarity.
Changes made in driver and relevant dts.
projects / zynq / linux.git / log