Xilinx: ARM: PSS: Modified the linux usb host controller driver for USB
Modified the existing linux host controller driver for PSS USB controller changes
and updated the Kconfig files to include the driver in the linux kernel config.
Xilinx: ARM: PSS: Modified the linux usb gadget controller driver
Modified the existing linux gadget controller driver for PSS USB controller changes
and updated the Kconfig file to include the driver in the linux kernel config.
Sadanand M [Mon, 22 Nov 2010 06:58:30 +0000 (12:28 +0530)]
Xilinx: ARM: QSPI driver: Use 128 byte pages in MTD driver
There seems to be a problem in the QSPI because of which
writes larger than FIFO size are causing a problem (the
last word in some pages is corrupt). This patch hacks the
m25p80.c driver to use a smaller page size so that there
is no issue with page writes.
Sadanand M [Mon, 22 Nov 2010 06:49:18 +0000 (12:19 +0530)]
Xilinx: ARM: QSPI driver: Hack to transmit PP command & addr together
There seems to be some problem with QPSI, because of which
some page writes aren't happenning correctly when command
and data are transmitted seperately. This patch hacks the
driver such that data and command are transmitted together,
to fix the issue.
Sadanand M [Tue, 16 Nov 2010 09:54:51 +0000 (15:24 +0530)]
Xilinx: ARM: QSPI driver: Remove redundant code
Remove the lines of code which set the value of the Threshold
register to 127, in the xqspipss_fill_tx_fifo() function. This
code has crept in during testing and is not required
Sadanand M [Tue, 16 Nov 2010 09:33:42 +0000 (15:03 +0530)]
Xilinx: ARM: QSPI driver: Check for instructions only in 1st message
Use a flag to indicate the first message in a transfer request
list and check for the instuctions only in the first message of
a request. This is to avoid treating data as instructions and
accidentally writing them to the wrong Tx register
Sadanand M [Tue, 26 Oct 2010 15:09:43 +0000 (20:39 +0530)]
arm: XIlinx: QSPI driver: Update command sizes & allow data only transfers
These changes allow this driver to be used with the standard way of
transmitting SPI data in Linux. This enables the driver to be used
with the m25p80.c driver, among others.
Sadanand M [Tue, 26 Oct 2010 05:45:27 +0000 (11:15 +0530)]
arm: Xilinx: QSPI driver: bug fixes
Fix a bug while checking the array size in xqspipss_start_transfer
and update xqspipss_copy_read_data, xqspipss_copy_read_data to
set bytes_to_transfer and bytes_to_receive to 0, when they are < 0
Dan Carpenter [Thu, 12 Aug 2010 07:53:52 +0000 (09:53 +0200)]
mtd/m25p80: retlen is never NULL
This is just a cleanup, it doesn't fix any bugs.
These functions all check retlen inconsistently and it generates a
warning in Smatch (http://smatch.sf.net). If retlen were ever NULL it
would cause an oops and the code has been this way since 2006 so someone
would have complained. Also I looked at other places that implemented
the mtd read and write functions and they dereference retlen without
checking.
I removed the checks.
Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Anton Vorontsov [Tue, 22 Jun 2010 16:57:42 +0000 (20:57 +0400)]
mtd: m25p80: Make jedec_probe() return proper errno values
spi_write_then_read() may return its own return codes (e.g. -EIO),
so let's propagate the value down to the probe().
Also, remove jedec == 0 check, it isn't needed as nowadays we use
dedicated SPI device IDs for non-JEDEC flashes.
Suggested-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This was needed to support non-JEDEC flashes. Though, it appears
that some platforms (e.g. blackfin bf533 stamp[1]) used the old
behavior to detect if there's any flash connected, so the driver
have to fail on JEDEC probing errors.
This patch restores the old behavior for JEDEC flashes, and adds
"-nonjedec" SPI device IDs for M25Pxx flashes, so that the kernel
still supports non-JEDEC flashes.
Reported-by: Mingquan Pan Reported-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
John Linn [Thu, 14 Oct 2010 18:14:08 +0000 (12:14 -0600)]
Xilinx: ARM: QSPI: updating makefile and kconfig file for new driver
The previous commit forgot these details for the new driver. This
also renames the driver file (not everything in the file) so that
it matches other driver file names.
Sadanand M [Thu, 14 Oct 2010 11:25:23 +0000 (16:55 +0530)]
ARM: Xilinx: QSPI: New driver for the QSPI controller
This driver supports the QSPI flash on PEEP. It supports most
of the generic flash commands. New commands supported by a
specific flash can be easily added to the driver
Sadanand M [Thu, 14 Oct 2010 10:36:12 +0000 (16:06 +0530)]
ARM: Xilinx: sdhci.c: Temp hack for card ins status
Hack the Generic SDIO host controller driver, to not check
for the card insertion status, as the SDIO controller on
PEEP doesn't update this status. Without this hack the
driver assumes that there is no card and errors out
Sadanand M [Thu, 14 Oct 2010 10:31:10 +0000 (16:01 +0530)]
ARM: Xilinx: SDIO: Add platform device info
Add the platform device info for the SDIO controllers in Pele.
These SDIO controllers use the generic SDIO host controller
driver (sdhci.c). This patch also hacks the sdhci.c driver
to not check the card insertion status since this status is
not being reflected in the SDIO controllers on PEEP.
John Linn [Wed, 6 Oct 2010 17:59:12 +0000 (11:59 -0600)]
Xilinx: ARM: Updated non-SMP kernel defconfigs to not use high res timers
The timer code was updated to support one-shot which allows high res timers
to work. But high res timers require the HZ to be higher than the 10 that
we are currently using.
Values of 60 and up seem to work for non-SMP, but SMP seems to need higher than
that. The patch for the timer one-shot mode can cause the non-SMP kernel
to not boot due to this problem (or hang while booting).
We talked about it and think that non-high res is probably the right default
for now. The SMP kernel defaults to non-high res timers.
John Linn [Tue, 5 Oct 2010 15:56:47 +0000 (09:56 -0600)]
Xilinx: ARM: updated test def configs for NFS root operation
Now that we have both ethernet IPs up and running we need to specify
which ethernet to use for NFS root since the 2nd one is not hooked
up to a network.
It seems that NFS root doesn't work if eth0 is not specified on the
kernel command line.
Brian Hill [Tue, 21 Sep 2010 22:28:34 +0000 (16:28 -0600)]
Xilinx: ARM: Correct DT 576001 - zero descriptor tracking memory at initialization.
When the kernel attempts IP address assignment at bootup it closed the interface
without it having ever been opened. Some cleanup code which expected only NULL
or valid addresses didn't cope with this situation.
Zero descriptor tracking array at initialization to avoid this problem.
Brian Hill [Thu, 16 Sep 2010 16:06:48 +0000 (10:06 -0600)]
Xilinx: ARM: Correct various GEM hi-traffic issues
- Strictly adhere to NAPI budget.
- xemacpss_start_xmit must return NETDEV_TX_BUSY when TX ring full, not
-ENOSPC
- Correct xemacpss_tx_timeout so that it might actually succeed when needed.
Remove GEM TX bottom-half. TX processing is not so onerous that it require
a bottom half.
TX completion is now performed directly within the interrupt handler, which
can only execute on on processor at a time. No new packet processing locks
are required as NAPI poll routines are guaranteed to no be run on more than one
CPU at the same instant, and other pre-existing locks are sufficient.
John Linn [Fri, 3 Sep 2010 22:15:01 +0000 (16:15 -0600)]
Xilinx: ARM: Cleanup of BSP for I2C and SPI so RTC works.
The I2C eeprom was being configured wrong such that it consumed
multiple addresses which conflicted with the next address (0x51)
which is used by the real time clock.
The SPI eeproms were also cleaned up to be simpler.
Sadanand [Fri, 27 Aug 2010 04:27:27 +0000 (09:57 +0530)]
Xilinx: ARM: BSP: SMC initialization code for SRAM interface
This patch adds initialization code for the SRAM interface of
the PL353 SMC and ioremaps the SRAM memory space.
The SRAM has been tested using mmap from the user space.
projects / zynq / linux.git / log