Xilinx: SMC NAND Definitions

Added the SMC NAND controller definitions to the device list.

Signed-off-by: Naveen naveenm@xilinx.com

diff --git a/arch/arm/mach-xilinx/devices.c b/arch/arm/mach-xilinx/devices.c
index baa58261417f94eb0d5e557db72f10ce08a2d789..8bc54a40a67549843eb43ba85ccabee0d4069798 100644 (file)
--- a/arch/arm/mach-xilinx/devices.c
+++ b/arch/arm/mach-xilinx/devices.c
@@ -202,6 +202,32 @@ struct platform_device xilinx_norpss_device = {
        .num_resources = ARRAY_SIZE(xnorpss_0_resource),
 };
 
+/*************************PSS NAND ***********************/
+#include <linux/mtd/nand.h>
+static u32 options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
+static struct resource xnand_res[] = {
+       {
+               .start  = NAND_BASE,
+               .end    = NAND_BASE + 0xFFFFFF,
+               .flags  = IORESOURCE_MEM
+       },
+       {
+               .start  = SMC_BASE,
+               .end    = SMC_BASE + 0xFFF,
+               .flags  = IORESOURCE_MEM
+       },
+};
+
+struct platform_device xilinx_nandpss_device = {
+       .name = "Xilinx_PSS_NAND",
+       .id = 0,
+       .dev = {
+               .platform_data = &options,
+       },
+       .num_resources = ARRAY_SIZE(xnand_res),
+       .resource = xnand_res,
+};
+
 #define ETH0_PHY_MASK 0x17
 #define ETH1_PHY_MASK 24
 
@@ -374,6 +400,7 @@ struct platform_device *xilinx_pdevices[] __initdata = {
        &xilinx_spipss_0_device,
        &xilinx_wdtpss_0_device,
        &xilinx_a9wdt_device,
+       &xilinx_nandpss_device,
 };
 
 /**

diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
index a7848a93c24ee3d174959db72f63e07482ea5eca..7f456195c041a2ee71eb8836de8860a0ef89d3b7 100644 (file)
--- a/arch/arm/mach-xilinx/include/mach/hardware.h
+++ b/arch/arm/mach-xilinx/include/mach/hardware.h
@@ -59,6 +59,7 @@
 
 #define SMC_BASE               (IO_BASE + 0x0000E000)
 #define NOR_BASE               (IO_BASE + 0x04000000)
+#define NAND_BASE              (IO_BASE + 0x01000000)
 
 /* Cleaned up addresses start here, please keep addresses in order to make
  * them easier to read.
@@ -113,6 +114,7 @@
 #define IRQ_TIMERCOUNTER0      42
 #define IRQ_DMAC0_ABORT                45
 #define IRQ_DMAC0              46
+#define IRQ_SMC                        50
 #define IRQ_GPIO0              52
 #define IRQ_ETH0                54
 #define IRQ_I2C0               57