drm: xlnx: pl_disp: Added plane atomic check function
This patch adds the atomic check helper function to update mode
changed flag and returns error when framebuffer remove functionality
forces to commit without disable crtc.
Without this patch, new DRM framework commits without disable crtc
which leads image corruption and delay in consecutive runs.
Versal watchdog driver uses generic watchdog mode.
Generic watchdog contains closed and open window of equal timeout.
Generic watchdog will generate reset signal if it is not explicitly
refreshed in second window.
watchdog: of_xilinx_wdt: Introduce wdttype enum for identification
There is a need to identify watchdog type that's why new enum was
was introduced to cover it. Move functionality valid only for this
watchdog type if statement.
watchdog: of_xilinx_wdt: Initialize watchdog via data structure
This patch is preparation for adding new watchdog based on this driver.
of_id->data is storing link xwdt_devtype_data which stores watchdog
info and ops pointers to structures.
Based on checkpatch every spinlock should be documented.
The patch is fixing this issue:
./scripts/checkpatch.pl --strict -f drivers/watchdog/of_xilinx_wdt.c
CHECK: spinlock_t definition without comment
+ spinlock_t spinlock;
mtd: rawnand: pl353: Allow raw read/write only for on-die ecc flash parts
When using HW-ECC, do not assign pl353_read_page_raw() and
pl353_write_page_raw() to ecc->write_page_raw and ecc->read_page_raw
hooks. if we do that read and writes will fail. We came to know this,
when running mtd_nandbiterrs test. This test case uses raw read/writes
when assigned but with hw-ecc, causes failures in data read
and writes.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As per the new devicetree documentation, update the compatible and
clock-names properties.
i.e. add "arm,primecell" as another compatibility
and apb_pclk instead of aclk in clock-names.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
uio: xilinx_ai_engine: Simulate the irq if no hw irq is available
Only when there's no hw irq available and the debugfs is enabled,
simulate the irq. This allows users to trigger the interrupt through
debugfs and helps debug, as some emulation platforms don't even
have the NPI interrupt connected.
v4l: xilinx: scd: Don't mark channel as disabled in .s_stream(0)
Commit 2e77607047c6 ("xilinx: v4l2: dma: Add multiple output support")
incorrectly calls .s_stream(0) on all channels when one of them gets
disabled, causing all the other channels to hang. Work around this by
not disabling the channel in .s_stream(0). The channel will be disabled
in xscd_dma_terminate_all() which should be safe as long as
dmaengine_terminate_all() is called after xvip_pipeline_set_stream().
v4l: xilinx: scd: Cleanup the xscd_dma_chan structure
Cleanup the xscd_dma_chan structure by
- Reordering fields to group them by category
- Renaming the en field to enabled
- Removing the unused chan_node field
- Turning the id field from u8 to unsigned int
xilinx-scenechange.h contains various #include statements not needed by
the header itself but by the multiple .c files that include it. Move
them to the .c files and remove unneeded includes.
v4l: xilinx: scd: Initialize DMA channels in xilinx-scenechange-dma.c
Most of the DMA channel initialization is performed in
xilinx-scenechange-dma.c, but a small part is in
xilinx-scenechange-channel.c. Move all the initialization code to
xilinx-scenechange-dma.c, rename the xscd_dma_chan_probe() function to
xscd_dma_chan_init(), and simplify the code as the function can't fail.
v4l: xilinx: scd: Request IRQ after completing initialization
IRQs can be triggered as soon as they're requested. To ensure a valid
state in the IRQ handler, make sure to request the IRQ after
initializing all components.
v4l: xilinx: scd: Store channel registers address in iomem field
Store the channel registers address instead of the base offset in the
iomem field of the channel structures. This allows accessing the channel
registers without having to compute the offset each time.
Allocating the pads array dynamically doesn't save much memory, if at
all, due to the extra data needed to track the devm allocation, compared
to embedding an array of two pads in the xscd_device structure. Replace
the dynamic allocation.
v4l: xilinx: scd: Refactor the xscd_device structure
Reorder fields to group them by category (system resources,
configuration V4L2 channels, DMA channels), squash the xscd_shared_data
structure with xscd_device and remove duplicated fields.
v4l: xilinx: scd: Compile all SCD source files in a single module
The files xilinx-scenechange.c, xilinx-scenechange-dma.c and
xilinx-scenechange-channel.c are part of the same driver. Compile them
as a single module.
v4l: xilinx: scd: Merge the main and DMA IRQ handlers
Both the main SCD driver and the DMA support code register an IRQ
handler, for the same IRQ. This is unnecessary, we can just call the DMA
IRQ handling function from the main IRQ handler.
v4l: xilinx: scd: Cleanup the DMA engine at remove() time
The resources allocated by the xscd_dma_init() function are never
released. Add a new xscd_dma_cleanup() function to handle the cleanup
and call it at driver remove() time.
v4l: xilinx: scd: Merge the DMA support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the DMA support. Merge the xscd_dma_device structure into the
xscd_device. This allows removing duplicating fields, as well as
unneeded code.
v4l: xilinx: scd: Merge the main and V4L2 IRQ handlers
Both the main SCD driver and the V4L2 support code register an IRQ
handler, for the same IRQ. This is unnecessary, we can just call the
V4L2 IRQ handling function from the main IRQ handler.
v4l: xilinx: scd: Merge the V4L2 support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the V4L2 support. Call the xilinx-scenechange-channel initialization
function directly from the main driver. This allows removing duplicating
fields, as well as unneeded code.
Move all driver data structures to the xilinx-scenechange.h header. Turn
the cast macros into static inline function and rename them all to
to_<struct name> for consistency.
v4l: xilinx: vipp: Support entity matching on DT subnodes
When the video IP pipeline is parsed in DT, the composite device stores
all entities found in the graph, along with their corresponding DT node.
Later on the DT nodes pointers are used to locate the corresponding V4L2
subdevs by matching them against subdev->dev->of_node.
This mechanism works fine for devices that register a single subdev. For
devices that register multiple subdevs, subdev->dev->of_node points to
the DT node of the device, while the entities parsed from the pipeline
point to child nodes of the device DT node.
The v4l2_subdev structure has a fwnode field that is set to point to the
fwnode corresponding to the device DT node. Drivers that register
multiple subdevs must set the fwnode field manually to the associated
child node of the device DT node. We can thus fix this issue by locating
V4L2 subdevs for an entity based on the subdev fwnode instead of the
dev->of_node.
v4l: xilinx: sdirxss: Fix the media bus formats to 10bpc type
With commit id 563e888fca45a978e4c29b2f5ec5a8a95af60e68, xyavta now
fails to start stream as the media bus format requested is
MEDIA_BUS_FMT_UYVY10_1x20 but the SDI Rx subdev returned media bus
format is MEDIA_BUS_FMT_UYVY8_1x16.
Fix this by updating the driver for correct media bus formats for YUV
422 and 420 10bpc i.e. MEDIA_BUS_FMT_UYVY10_1X20 and
MEDIA_BUS_FMT_VYYUYY10_4X20.
Vishal Sagar [Fri, 29 Mar 2019 06:23:20 +0000 (23:23 -0700)]
v4l: xilinx: tpg: Dynamically modify TPG output format
The TPG output format was fixed based on the device tree. This patch now
allows the TPG output format to be configured at runtime. This is valid
only for the HLS version of TPG.
Wendy Liang [Fri, 29 Mar 2019 16:45:29 +0000 (09:45 -0700)]
dt-bindings: remoteproc: zynqmp-r5: correct dts example
* Correct ZynqMP r5 remoteproc device node example bindings to
remove the old sram, power domain nodes, and add new reserved memory
nodes.
* Fix the remoteproc device node compatible string to match the driver
* Use the mailbox to match the OpenAMP usecase
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes CONFIG_ZYNQMP_RESET_CONTROLLER entry from
xilinx_zynqmp_defconfig file since zynqmp reset driver will
build for ZYNQMP platform by default.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx: axiethernet: Fix crash in ifconfig down
In axidma(allow un-aligned transfers) designs, axienet_dma_q structure
tx_bufs pointer is not explicitly initialized to NULL so freeing it in
.ndo_stop may result in a kernel crash. To fix it allocate axienet_dma_q
structure memory using kzalloc. This fixes below crash in vcu118 design.
gpio: zynq: Disable the irq if it is not a wakeup source
If gpio is not set to wake disable the interrupt. ATF set all slaves with
enabled interrupts as wakeup sources and if gpio is used in r5 then it
wakes up linux.
net: can: xilinx_can: Fix FSR register handling in the rx path
After commit fc8c67368936 ("net: can: xilinx_can: Add support for
CANFD FD frames") driver is updating the FSR IRI index multiple
times(i.e in xcanfd_rx() and xcan_rx_fifo_get_next_frame()),
It should be updated once per rx packet this patch fixes this issue,
also this patch removes the unnecessary fsr register checks in
xcanfd_rx() API.
Hyun Kwon [Fri, 29 Mar 2019 05:22:00 +0000 (22:22 -0700)]
drm: xlnx: zynqmp_disp: Skip the modeset for same fb
Since the async update creates a separate atomic mode set, there can be
back to back atomic modeset with same fb. If the mode set is applied
twice, it ends up submitting 2 dma transactions, and it results in
jitter. This fixes it by adding the check in plane atomic update,
and using plane mode set in async update.
Rajan Vaja [Fri, 29 Mar 2019 05:46:49 +0000 (22:46 -0700)]
clk: zynqmp: Warn user if clock user are more than allowed
Warn user if clock is used by more than allowed devices.
This check is done by firmware and returns respective
error code. Upon receiving error code for excessive user,
warn user for the same.
This change is done to restrict VPLL use count. It is
assumed that VPLL is used by one user only.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: devices: m25p80: sync driver with mainline v4.19
This patch syncs the driver with mainline 4.19 m25p80.c.
Below is the commit from mainline 9882b53 mtd: m25p80: Use SPI_MEM_OP_NO_DUMMY instead of
SPI_MEM_OP_DUMMY(0, x)
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch move eemi_ops into priv struct zynqmp_reset_data.
Updated all the functions to get the priv struct and use the eemi_ops
structure present inside priv struct.
62f0d7d reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
reset: reset-zynqmp: Sync Reset Id macro with Mainline
Reset Start and End Macro values are updated as part of below
commit Id. bc3843d firmware: xilinx: Add reset API's
Hence updated the driver in using the start and end macro values.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
serial: uartlite: fix null dereference on probe error path
The `pdata->ulite_uart_driver` is assigned last in the probe function. So,
when un-registering the serial device on the error path this causes a
null dereference and a crash.
This fixes that by passing the initialized `ulite_uart_driver` pointer.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Thu, 28 Mar 2019 13:05:56 +0000 (06:05 -0700)]
clk: zynqmp: Fix divider calculation
Linux doesn't know maximum value of divisor that it can support.
zynqmp_clk_divider_round_rate() returns actual divider value
after calculating from parent rate and desired rate, even though
that rate is not supported by single divider of hardware. It is
also possible that such divisor value can be achieved through 2
different dividers. As, Linux tries to set such divisor value(out
of range) in single divider set divider is getting failed.
Fix the same by computing best possible combination of two
divisors which provides more accurate clock rate.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jolly Shah [Fri, 22 Mar 2019 14:21:35 +0000 (07:21 -0700)]
drivers: firmware: Add Pdi load API support
This patch adds load pdi api support to enable pdi/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kalyani Akula [Wed, 27 Mar 2019 07:38:11 +0000 (13:08 +0530)]
zynqmp-secure: Fix for crash seen with secure image loading
This patch resolves the crash/backtrace seen with secure load.
arch_setup_dma_ops is not setting coherent mask due to which
we see a warning (added recently in dma_mapping.h) and backtrace
along with it.
So, instead of using arch_setup_dma_ops we used of_dma_configure.
Kalyani Akula [Wed, 27 Mar 2019 07:38:09 +0000 (13:08 +0530)]
firmware: zynqmp: Modify zynqmp_pm_secure_load to return only dst.
This extra parameter added earlier to know proper error code
from the SMC, but earlier change broken backward compatibility.
So, handling the same in PMU by displaying proper error code
using PmErr.
Wolfram Sang [Thu, 28 Mar 2019 12:35:08 +0000 (18:05 +0530)]
mmc: core: use mrq->sbc when sending CMD23 for RPMB
When sending out CMD23 in the blk preparation, the comment there
rightfully says:
* However, it is not sufficient to just send CMD23,
* and avoid the final CMD12, as on an error condition
* CMD12 (stop) needs to be sent anyway. This, coupled
* with Auto-CMD23 enhancements provided by some
* hosts, means that the complexity of dealing
* with this is best left to the host. If CMD23 is
* supported by card and host, we'll fill sbc in and let
* the host deal with handling it correctly.
Let's do this behaviour for RPMB as well, and not send CMD23
independently. Otherwise IP cores (like Renesas SDHI) may timeout
because of automatic CMD23/CMD12 handling.
spi: spi-xilinx: Added workaround when startup block is enabled
In AXI SPI when the startup block is enabled in the hardware
STARTUP block don't provide clock as soon as SPI provides command,
first command fails. So to overcome this issue added a workaround
to perform a dummy Read Id if startup block is enabled in the
hardware.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Acked-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: phy: dp83867: Add support for 6-wire mode in SGMII configuration
SGMII interface is capable of working as a 4-wire or 6-wire SGMII
interface. Default is 4-wire mode. Read DT "ti,6-wire-mode" property
to program SGMIICTL1[SGMII_TYPE] 6-wire mode.
v4l: xilinx: scd: Enable 10 bit formats support for memory based IP
This patch enables 10bit format support in driver. This will configure
the 8bit or 10bit video format in IP based on media bus format set by
the application.
Harini Katakam [Sat, 23 Mar 2019 07:12:31 +0000 (12:42 +0530)]
arm64: zynqmp: Update Micrel PHY details on zc1275 and zc1285
The FMC card AES-FMC-NETW1-G is the necessary to support ethernet
on zc1275 and zc1285 boards. No previous PHYs/FMCs will be supported
on this HW. So update the phy address to 1 and necessary skew values.
Also remove PL IP related nodes and parameters that DTG generates.
projects / zynq / linux.git / log