From a45919785400a76876e2f3b49e4bdbb6d0aaf4f1 Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Fri, 27 Apr 2018 15:42:48 +0530 Subject: [PATCH] dmaengine: xilinx: dma: In axidma add support for 64MB data transfer In 2018.1 axidma IP support for 64 MB data transfer is added by increasing buffer length width to 26bit. Modify DT "xlnx,sg-length-width" validation accordingly. Since max length for previous IP version is 23 bit display a warning message if length is in 23-26 bit range. It would have an ideal solution to add a separate compatibility string and config structure for this changed IP but due to lack of proper DMA IP versioning it's dropped. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- drivers/dma/xilinx/xilinx_dma.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index b78d005fbfff..0a669c23a680 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -163,6 +163,7 @@ /* AXI DMA Specific Masks/Bit fields */ #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) #define XILINX_DMA_CR_COALESCE_SHIFT 16 @@ -2732,12 +2733,14 @@ static int xilinx_dma_probe(struct platform_device *pdev) if (!of_property_read_u32(node, "xlnx,sg-length-width", &len_width)) { if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || - len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) { + len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { dev_warn(xdev->dev, "invalid xlnx,sg-length-width property value using default width\n"); } else { - xdev->max_buffer_len = GENMASK(len_width - 1, - 0); + if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) + dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); + + xdev->max_buffer_len = GENMASK(len_width - 1, 0); } } } -- 2.39.2