dmaengine: xilinx: dma: In axidma add support for 64MB data transfer

[zynq/linux.git] / drivers / dma / xilinx / xilinx_dma.c

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index b78d005fbfff3be6031f52f34944796b0980f2e7..0a669c23a68074725b2d181441a51da2577e4889 100644 (file)
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -163,6 +163,7 @@
 /* AXI DMA Specific Masks/Bit fields */
 #define XILINX_DMA_MAX_TRANS_LEN_MIN   8
 #define XILINX_DMA_MAX_TRANS_LEN_MAX   23
+#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX        26
 #define XILINX_DMA_CR_COALESCE_MAX     GENMASK(23, 16)
 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK        BIT(4)
 #define XILINX_DMA_CR_COALESCE_SHIFT   16
@@ -2732,12 +2733,14 @@ static int xilinx_dma_probe(struct platform_device *pdev)
                if (!of_property_read_u32(node, "xlnx,sg-length-width",
                                          &len_width)) {
                        if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
-                           len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) {
+                           len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
                                dev_warn(xdev->dev,
                                         "invalid xlnx,sg-length-width property value using default width\n");
                        } else {
-                               xdev->max_buffer_len = GENMASK(len_width - 1,
-                                                              0);
+                               if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
+                                       dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
+
+                               xdev->max_buffer_len = GENMASK(len_width - 1, 0);
                        }
                }
        }