]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree - system/script/
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / script /
drwxr-xr-x   ..
-rw-r--r-- 931 build.tcl
-rw-r--r-- 676 dist.tcl
-rw-r--r-- 7085 recreate.tcl