]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header. microzed_apo
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 25 Jul 2017 13:14:07 +0000 (15:14 +0200)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 25 Jul 2017 13:14:07 +0000 (15:14 +0200)
commit0e341ea1a146c458dc7fb965ccedb6a47b51d16d
treefa9c9642b0c429dc44da7c4cf947e8a6f5b22798
parenta829d40319bb6e14c76c288852c8aba457019b20
microzed_apo: Correct  JX1_LVDS_21_N pin assignment on FPGA_IO header.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/src/constrs/microzed_apo-rev1.xdc