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[fpga/zynq/canbench-sw.git] / system / ip / spi_leds_and_enc_1.0 / hdl /

drwxr-xr-x		..
-rw-r--r--	1679	cnt_div.vhdl	blob \| history \| raw
-rw-r--r--	434	dff.vhdl	blob \| history \| raw
-rw-r--r--	1578	dff3cke.vhdl	blob \| history \| raw
-rw-r--r--	1858	pulse_gen.vhdl	blob \| history \| raw
-rw-r--r--	2930	qcounter_nbit.vhdl	blob \| history \| raw
-rw-r--r--	12953	spi_leds_and_enc_v1_0.vhd	blob \| history \| raw
-rw-r--r--	23393	spi_leds_and_enc_v1_0_S00_AXI.vhd	blob \| history \| raw
-rw-r--r--	2344	spi_leds_and_enc_v1_0_spi_fsm.vhd	blob \| history \| raw

CAN benchmark FPGA design and software for MicroZed board