]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree - petalinux/
xilinx_can: debugging, fixed timing problem, lowered can clk to 20MHz
[fpga/zynq/canbench-sw.git] / petalinux /
drwxr-xr-x   ..
-rw-r--r-- 342 .gitignore
drwxr-xr-x - .petalinux
-rw-r--r-- 1201 Makefile
-rw-r--r-- 1118 bootscript.txt
drwxr-xr-x - components
-rw-r--r-- 248 config.project
drwxr-xr-x - hw-description
-rwxr-xr-x 101 mkbootscript
drwxr-xr-x - subsystems
-rw-r--r-- 216 uEnv.txt
-rw-r--r-- 676 uboot-extra-env.h