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(parent: 61b3e9f) | patch
xilinx_can: debugging, fixed timing problem, lowered can clk to 20MHz
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 17 May 2016 21:48:25 +0000 (23:48 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 17 May 2016 21:57:45 +0000 (23:57 +0200)
commit36418f6d3aa3ad64857341b4930f77274e33cc16
tree538287f6678641a7fb9c4a741e005e68939be6d6tree | snapshot
parent61b3e9f31eabfba1a155e67c32812922be854716commit | diff
xilinx_can: debugging, fixed timing problem, lowered can clk to 20MHz

The Xilinx Zynq TRM description of CAN RX timestamp resolution
is misleading - it is clocked by undivided peripheral clock, not
by divided bit time clock.
petalinux/components/modules/xilinx_can/xilinx_can.c diff | blob | history
system/src/top/top.bd diff | blob | history
CAN benchmark FPGA design and software for MicroZed board