]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree
xilinx_can: debugging, fixed timing problem, lowered can clk to 20MHz
-rw-r--r-- 29 .gitignore
-rw-r--r-- 99 .gitmodules
-rw-r--r-- 694 Makefile
-rw-r--r-- 1831 README.txt
m--------- - can-benchmark
drwxr-xr-x - petalinux
drwxr-xr-x - system