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microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / ip / audio_single_pwm_1.0 / hdl / pulse_gen.vhdl
2017-02-14 Pavel Pisamicrozed_apo: Single channel PWM audio implemented... blob | commitdiff | raw
CAN benchmark FPGA design and software for MicroZed board