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component audio_single_pwm_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
- C_S_AXI_ADDR_WIDTH : integer := 6
+ C_S_AXI_ADDR_WIDTH : integer := 6;
+ audio_pwm_width : integer := 24
);
port (
+ audio_pwm_period: out std_logic_vector(audio_pwm_width-1 downto 0);
+ audio_pwm_duty: out std_logic_vector(audio_pwm_width-1 downto 0);
+
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
);
end component audio_single_pwm_v1_0_M00_AXI;
+ component cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
+ );
+ end component;
+
+ component pulse_gen is
+ generic (
+ duration_width_g : natural := 4
+ );
+ port (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ trigger_i : in std_logic; --start to generate pulse
+ duration_i : in std_logic_vector(duration_width_g-1 downto 0);--duration/interval of the pulse
+ q_out_o : out std_logic --generates pulse for given duration
+ );
+ end component;
+
+ constant audio_pwm_width : integer := 24;
+
+ signal audio_pwm_period: std_logic_vector(audio_pwm_width-1 downto 0);
+ signal audio_pwm_duty: std_logic_vector(audio_pwm_width-1 downto 0);
+
+ signal fsm_clk : std_logic;
+ signal fsm_rst : std_logic;
+
+ signal pwm_cycle_start : std_logic;
+
signal m00_axi_init_axi_txn : std_logic;
signal m00_axi_error : std_logic;
signal m00_axi_txn_done : std_logic;
audio_single_pwm_v1_0_S00_AXI_inst : audio_single_pwm_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
- C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
+ C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH,
+
+ audio_pwm_width => audio_pwm_width
)
port map (
+ audio_pwm_period => audio_pwm_period,
+ audio_pwm_duty => audio_pwm_duty,
+
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
-- Add user logic here
- speaker_pwm_out <= '0';
- irq_rq_out <= '0';
- m00_axi_init_axi_txn <= '0';
+cnt_div_inst: cnt_div
+ generic map (
+ cnt_width_g => audio_pwm_width
+ )
+ port map (
+ clk_i => fsm_clk,
+ en_i => '1',
+ reset_i => fsm_rst,
+ ratio_i => audio_pwm_period,
+ q_out_o => pwm_cycle_start
+ );
+
+audio_pwm_inst: pulse_gen
+ generic map (
+ duration_width_g => audio_pwm_width
+ )
+ port map (
+ clk_i => fsm_clk,
+ en_i => '1',
+ reset_i => fsm_rst,
+ trigger_i => pwm_cycle_start,
+ duration_i => audio_pwm_duty,
+ q_out_o => speaker_pwm_out
+ );
+
+ irq_rq_out <= '0';
+ m00_axi_init_axi_txn <= '0';
+
+ fsm_clk <= s00_axi_aclk;
+ fsm_rst <= not s00_axi_aresetn;
-- User logic ends
end arch_imp;
entity audio_single_pwm_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-
+ audio_pwm_width : integer := 24;
-- User parameters ends
-- Do not modify the parameters beyond this line
);
port (
-- Users to add ports here
-
+ audio_pwm_period: out std_logic_vector(audio_pwm_width-1 downto 0);
+ audio_pwm_duty: out std_logic_vector(audio_pwm_width-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Add user logic here
-
+ audio_pwm_period <= slv_reg2(audio_pwm_width-1 downto 0);
+ audio_pwm_duty <= slv_reg3(audio_pwm_width-1 downto 0);
-- User logic ends
end arch_imp;
--- /dev/null
+--
+-- * Counter - divider *
+--
+-- part of LXPWR motion control board (c) PiKRON Ltd
+-- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
+--
+-- license: BSD
+--
+-- This file is used in "RPI PMS motor control" as frequency divider - divides by 6
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
+ );
+end cnt_div;
+
+architecture behavioral of cnt_div is
+ signal cnt_val_s : natural range 0 to (2**cnt_width_g - 1); --counter value before DFF
+ signal cnt_val_r : natural range 0 to (2**cnt_width_g - 1); --counter value after DFF
+begin
+
+comb: process (reset_i, en_i, ratio_i, cnt_val_r)
+ begin
+ if reset_i = '1' then --reset detection
+ cnt_val_s <= to_integer(unsigned(ratio_i)); --set initial value
+ q_out_o <= '0'; --reset output
+ else
+ if en_i = '0' then --stop-state
+ cnt_val_s <= cnt_val_r; --hold the value
+ q_out_o <= '0'; --reset output
+ else
+ if cnt_val_r <= 1 then --counter underflows
+ cnt_val_s <= to_integer(unsigned(ratio_i)); --set initial value
+ q_out_o <= '1'; --set output
+ else
+ cnt_val_s <= cnt_val_r - 1; --decrement counter
+ q_out_o <= '0'; --reset output
+ end if;
+ end if;
+ end if;
+ end process;
+
+seq: process
+ begin
+ wait until clk_i'event and clk_i = '1';
+ cnt_val_r <= cnt_val_s;
+ end process;
+
+end behavioral;
+
--- /dev/null
+--
+-- * pulse generator *
+--
+-- based on code from LXPWR motion control board (c) PiKRON Ltd
+-- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
+--
+-- license: BSD
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pulse_gen is
+ generic (
+ duration_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ trigger_i : in std_logic; --start to generate pulse
+ duration_i : in std_logic_vector(duration_width_g-1 downto 0);--duration/interval of the pulse
+ q_out_o : out std_logic --generates pulse for given duration
+ );
+end pulse_gen;
+
+architecture behavioral of pulse_gen is
+ signal cnt_val_s : natural range 0 to (2**duration_width_g - 1); --counter value before DFF
+ signal cnt_val_r : natural range 0 to (2**duration_width_g - 1); --counter value after DFF
+begin
+
+comb: process (reset_i, en_i, duration_i, trigger_i, cnt_val_r)
+ begin
+ if reset_i = '1' then --reset detection
+ cnt_val_s <= 0; --set defined value
+ q_out_o <= '0'; --reset output
+ else
+ if en_i = '0' then --stop-state
+ cnt_val_s <= cnt_val_r; --hold the value
+ else
+ if trigger_i = '1' then --trigger pulse generator
+ if to_integer(unsigned(duration_i)) = 0 then
+ q_out_o <= '0';
+ else
+ q_out_o <= '1';
+ end if;
+ cnt_val_s <= to_integer(unsigned(duration_i)); --set initial value
+ elsif cnt_val_r = 0 then --pulse finished
+ cnt_val_s <= cnt_val_r;
+ q_out_o <= '0'; --set output
+ else
+ cnt_val_s <= cnt_val_r - 1; --decrement counter
+ q_out_o <= '1'; --reset output
+ end if;
+ end if;
+ end if;
+ end process;
+
+seq: process
+ begin
+ wait until clk_i'event and clk_i = '1';
+ cnt_val_r <= cnt_val_s;
+ end process;
+
+end behavioral;
+
projects / fpga / zynq / canbench-sw.git / commitdiff