]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
projects / fpga / zynq / canbench-sw.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 43fcb1b) | patch
scripts: include script for applying new FPGA design at runtime. master
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Mon, 16 Jan 2017 16:33:56 +0000 (17:33 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Mon, 16 Jan 2017 16:33:56 +0000 (17:33 +0100)
commit62330ef440463927eb496eae01091bd9b81007b4
tree4ed047ec647d4689da362300438b7d2426b0fcd3tree | snapshot
parent43fcb1b645ae691936bc2ed9b641eeb570877faccommit | diff
scripts: include script for applying new FPGA design at runtime.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
scripts/upbit [new file with mode: 0755] blob
CAN benchmark FPGA design and software for MicroZed board