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sja1000: fixes
[fpga/zynq/canbench-sw.git] / system / ip / sja1000_1.0 / hdl / can_bsp.v
2017-10-10 Martin Jerabeksja1000: fixes blob | commitdiff | raw
2017-10-10 Martin Jerabeksja1000: tx_data register access de-parallelized (TOTEST) blob | commitdiff | raw | diff to current
2017-10-10 Martin Jerabeksja1000: formatting, comments blob | commitdiff | raw | diff to current
2016-05-12 Martin Jerabeksja1000: synchronous with AXI, duplex register access... blob | commitdiff | raw | diff to current
2016-05-12 Martin Jerabekadded sja1000 IP blob | commitdiff | raw | diff to current
CAN benchmark FPGA design and software for MicroZed board