// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
-`include "can_defines.v"
+//`include "can_defines.v"
module can_bsp
(
- input clk,
- input rst,
- input sample_point,
- input sampled_bit,
- input sampled_bit_q,
- input tx_point,
- input hard_sync,
- input [7:0] addr, // FIFO read address
- input [7:0] data_in, // input data for FIFO and error count settings (looks magical :/)
- output [7:0] data_out, // from FIFO only
- input fifo_selected, // only forwarded
+ input wire clk,
+ input wire rst,
+ input wire sample_point,
+ input wire sampled_bit,
+ input wire sampled_bit_q,
+ input wire tx_point,
+ input wire hard_sync,
+ input wire [7:0] addr, // FIFO read address
+ input wire [7:0] data_in, // input data for FIFO and error count settings (looks magical :/)
+ output wire [7:0] data_out, // from FIFO only
+ input wire fifo_selected, // only forwarded
/* Mode register */
- input reset_mode,
- input listen_only_mode,
- input acceptance_filter_mode,
- input extended_mode,
- input self_test_mode,
+ input wire reset_mode,
+ input wire listen_only_mode,
+ input wire acceptance_filter_mode,
+ input wire extended_mode,
+ input wire self_test_mode,
/* Command register */
- input release_buffer,
- input tx_request,
- input abort_tx,
- input self_rx_request,
- input single_shot_transmission,
- output tx_state,
- output tx_state_q,
+ input wire release_buffer,
+ input wire tx_request,
+ input wire abort_tx,
+ input wire self_rx_request,
+ input wire single_shot_transmission,
+ output reg tx_state,
+ output reg tx_state_q,
// When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
// be send in a row. This is not implemented, yet, because host can not send an overload request.
- input overload_request,
- output overload_frame,
+ input wire overload_request,
+ output reg overload_frame,
/* Arbitration Lost Capture Register */
- input read_arbitration_lost_capture_reg;
+ input wire read_arbitration_lost_capture_reg,
/* Error Code Capture Register */
- input read_error_code_capture_reg;
- output [7:0] error_capture_code;
+ input wire read_error_code_capture_reg,
+ output reg [7:0] error_capture_code,
/* Error Warning Limit register */
- input [7:0] error_warning_limit;
+ input wire [7:0] error_warning_limit,
/* Rx Error Counter register */
- input we_rx_err_cnt;
+ input wire we_rx_err_cnt,
/* Tx Error Counter register */
- input we_tx_err_cnt;
-
- output rx_idle;
- output transmitting;
- output transmitter;
- output go_rx_inter;
- output not_first_bit_of_inter;
- output rx_inter;
- output set_reset_mode;
- output node_bus_off;
- output error_status;
- output [8:0] rx_err_cnt;
- output [8:0] tx_err_cnt;
- output transmit_status;
- output receive_status;
- output tx_successful;
- output need_to_tx;
- output overrun;
- output info_empty;
- output set_bus_error_irq;
- output set_arbitration_lost_irq;
- output [4:0] arbitration_lost_capture;
- output node_error_passive;
- output node_error_active;
- output [6:0] rx_message_counter;
+ input wire we_tx_err_cnt,
+
+ output reg rx_idle,
+ output reg transmitting,
+ output reg transmitter,
+ output wire go_rx_inter,
+ output wire not_first_bit_of_inter,
+ output reg rx_inter,
+ output wire set_reset_mode,
+ output reg node_bus_off,
+ output wire error_status,
+ output reg [8:0] rx_err_cnt,
+ output reg [8:0] tx_err_cnt,
+ output wire transmit_status,
+ output wire receive_status,
+ output wire tx_successful,
+ output reg need_to_tx, // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
+ output wire overrun,
+ output wire info_empty,
+ output wire set_bus_error_irq,
+ output wire set_arbitration_lost_irq,
+ output reg [4:0] arbitration_lost_capture,
+ output reg node_error_passive,
+ output wire node_error_active,
+ output wire [6:0] rx_message_counter,
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
- input [7:0] acceptance_code_0;
+ input wire [7:0] acceptance_code_0,
/* Acceptance mask register */
- input [7:0] acceptance_mask_0;
+ input wire [7:0] acceptance_mask_0,
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
- input [7:0] acceptance_code_1;
- input [7:0] acceptance_code_2;
- input [7:0] acceptance_code_3;
+ input wire [7:0] acceptance_code_1,
+ input wire [7:0] acceptance_code_2,
+ input wire [7:0] acceptance_code_3,
/* Acceptance mask register */
- input [7:0] acceptance_mask_1;
- input [7:0] acceptance_mask_2;
- input [7:0] acceptance_mask_3;
+ input wire [7:0] acceptance_mask_1,
+ input wire [7:0] acceptance_mask_2,
+ input wire [7:0] acceptance_mask_3,
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
- output [3:0] tx_data_addr_o;
- input [7:0] tx_data_i;
+ output reg [3:0] tx_data_addr_o,
+ input wire [7:0] tx_data_i,
/* End: Tx data registers */
/* Tx signal */
- output tx;
- output tx_next;
- output bus_off_on;
+ output reg tx,
+ output reg tx_next,
+ output wire bus_off_on,
- output go_overload_frame;
- output go_error_frame;
- output go_tx;
- output send_ack;
+ output wire go_overload_frame,
+ output wire go_error_frame,
+ output wire go_tx,
+ output wire send_ack
/* Bist */
`ifdef CAN_BIST
- input mbist_si_i;
- output mbist_so_o;
- input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
+ ,
+ input wire mbist_si_i,
+ output wire mbist_so_o,
+ input wire [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i // bist chain shift control
`endif
);
reg [2:0] bit_stuff_cnt_tx;
reg tx_point_q;
-reg rx_idle;
reg rx_id1;
reg rx_rtr1;
reg rx_ide;
reg rx_ack;
reg rx_ack_lim;
reg rx_eof;
-reg rx_inter;
reg go_early_tx_latched;
reg rtr1;
reg [2:0] eof_cnt;
reg [2:0] passive_cnt;
-reg transmitting;
-
reg error_frame;
reg enable_error_cnt2;
reg [2:0] error_cnt1;
reg [2:0] error_cnt2;
reg [2:0] delayed_dominant_cnt;
reg enable_overload_cnt2;
-reg overload_frame;
reg overload_frame_blocked;
reg [1:0] overload_request_cnt;
reg [2:0] overload_cnt1;
reg [2:0] overload_cnt2;
-reg tx;
reg crc_err;
reg arbitration_lost;
reg arbitration_lost_q;
reg arbitration_field_d;
-reg [4:0] arbitration_lost_capture;
reg [4:0] arbitration_cnt;
reg arbitration_blocked;
reg tx_q;
-reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
reg [2:0] header_cnt; // Counting header length
reg wr_fifo; // Write data and header to 64-byte fifo
reg [5:0] tx_pointer;
reg tx_bit;
-reg tx_state;
-reg tx_state_q;
-reg transmitter;
reg finish_msg;
-reg [8:0] rx_err_cnt;
-reg [8:0] tx_err_cnt;
reg [3:0] bus_free_cnt;
reg bus_free_cnt_en;
reg bus_free;
reg waiting_for_bus_free;
-reg node_error_passive;
-reg node_bus_off;
reg node_bus_off_q;
reg ack_err_latched;
reg bit_err_latched;
reg [2:0] susp_cnt;
reg error_flag_over_latched;
-reg [7:0] error_capture_code;
reg [7:6] error_capture_code_type;
reg error_capture_code_blocked;
-reg tx_next;
reg first_compare_bit;
wire go_rx_ack;
wire go_rx_ack_lim;
wire go_rx_eof;
-wire go_rx_inter;
wire last_bit_of_inter;
wire [7:0] r_tx_data;
-wire send_ack;
wire bit_err_exc1;
wire bit_err_exc2;
wire bit_err_exc3;
reg [5:0] limited_tx_cnt_ext;
reg [5:0] limited_tx_cnt_std;
+reg tx_is_extended_frame;
+
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt[3:0] == 4'd10);
/* Changing bit order from [7:0] to [0:7] */
-can_ibo i_ibo_tx_data (.di(tx_data), .do(r_tx_data));
+can_ibo i_ibo_tx_data (.di(tx_data_i), .do(r_tx_data));
/* Changing bit order from [14:0] to [0:14] */
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
-wire [3:0] basic_chain_byte [4:0];
-wire [3:0] basic_chain_duration [4:0];
+wire [5*4-1 : 0] basic_chain_byte;
+wire [5*4-1 : 0] basic_chain_duration;
-wire [3:0] extended_chain_std_byte [5:0];
-wire [3:0] extended_chain_std_duration [5:0];
+wire [6*4-1 : 0] extended_chain_std_byte;
+wire [6*4-1 : 0] extended_chain_std_duration;
-wire [3:0] extended_chain_ext_byte [9:0];
-wire [3:0] extended_chain_ext_duration [9:0];
+wire [10*4-1 : 0] extended_chain_ext_byte;
+wire [10*4-1 : 0] extended_chain_ext_duration;
// combinatorial
-reg [3:0] chain_byte [9:0];
-reg [3:0] chain_duration [9:0];
+reg [10*4-1 : 0] chain_byte;
+reg [10*4-1 : 0] chain_duration;
// registers
reg [3:0] item_idx;
reg [3:0] item_cnt;
-wire [3:0] basic_chain_data_byte [7:0];
-wire [3:0] extended_chain_data_std_byte [7:0];
-wire [3:0] extended_chain_data_ext_byte [7:0];
+wire [8*4-1 : 0] basic_chain_data_byte;
+wire [8*4-1 : 0] extended_chain_data_std_byte;
+wire [8*4-1 : 0] extended_chain_data_ext_byte;
assign basic_chain_byte = { 4'h1, 4'hx, 4'h1, 4'h0, 4'hx};
assign basic_chain_byte_duration = { 4'h4, 4'h2, 4'h4, 4'h8, 4'h1};
begin
if (tx_is_extended_frame) // Extended frame
begin
- chain_byte <= extended_chain_ext_byte;
- chain_duration <= extended_chain_ext_duration;
+ chain_byte = extended_chain_ext_byte;
+ chain_duration = extended_chain_ext_duration;
end else begin
- chain_byte <= {4{4'h0}, extended_chain_std_byte};
- chain_duration <= {4{4'h0}, extended_chain_std_duration};
+ chain_byte = {{4{4'h0}}, extended_chain_std_byte};
+ chain_duration = {{4{4'h0}}, extended_chain_std_duration};
end
end else begin
- chain_byte <= {5{4'h0}, basic_chain_byte};
- chain_duration <= {5{4'h0}, basic_chain_duration};
+ chain_byte = {{5{4'h0}}, basic_chain_byte};
+ chain_duration = {{5{4'h0}}, basic_chain_duration};
end
end
-always @(rst or posedge clk_i)
+always @(rst or posedge clk)
begin
if (rst | rst_tx_pointer)
+ begin
item_idx = 0;
item_cnt = 0;
- else if(~rx_data & ~rx_crc & ~finish_msg)
+ end
+ else if (~rx_data & ~rx_crc & ~finish_msg)
begin
if (item_cnt >= chain_duration[item_idx])
begin
end
end
-always @(rst or posedge clk_i)
+wire [2:0] data_byte_idx;
+assign data_byte_idx = tx_pointer[5:3];
+
+integer i;
+always @(rst or posedge clk)
begin
if (rst)
- tx_data_addr_o = 4'h0;
+ tx_data_addr_o <= 4'h0;
else
begin
if (rx_data) // data stage
if (extended_mode) // Extended mode
begin
if (tx_is_extended_frame) // Extended frame
- tx_data_addr_o = extended_chain_data_ext_byte[tx_pointer[5:3]];
+ for (i=0; i<=7; i=i+1)
+ tx_data_addr_o[i] <= extended_chain_data_ext_byte[data_byte_idx*8+i];
else
- tx_data_addr_o = extended_chain_data_std_byte[tx_pointer[5:3]];
+ for (i=0; i<=7; i=i+1)
+ tx_data_addr_o[i] <= extended_chain_data_std_byte[data_byte_idx*8+i];
+ end
else // Basic mode
- tx_data_addr_o = basic_chain_data_byte[tx_pointer[5:3]];
+ for (i=0; i<=7; i=i+1)
+ tx_data_addr_o[i] <= basic_chain_data_byte[data_byte_idx*8+i];
end
else if (rx_crc)
- tx_data_addr_o = 4'hx;
+ tx_data_addr_o <= 4'hx;
else if (finish_msg)
- tx_data_addr_o = 4'hx;
+ tx_data_addr_o <= 4'hx;
else
- tx_data_addr_o = chain_byte[item_idx];
- end
+ tx_data_addr_o <= chain_byte[item_idx];
end
end
*/
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
- r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
+ tx_is_extended_frame or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
finish_msg)
begin
if (extended_mode)
begin
if (rx_data) // data stage
- if (r_tx_data_0[0]) // Extended frame
- tx_bit = tx_data[tx_pointer[2:0]];
+ if (tx_is_extended_frame) // Extended frame
+ tx_bit = r_tx_data[tx_pointer[2:0]];
else
- tx_bit = tx_data[tx_pointer[2:0]];
+ tx_bit = r_tx_data[tx_pointer[2:0]];
else if (rx_crc)
tx_bit = r_calculated_crc[tx_pointer];
else if (finish_msg)
tx_bit = 1'b1;
else
begin
- if (r_tx_data_0[0]) // Extended frame
+ if (tx_is_extended_frame) // Extended frame
tx_bit = extended_chain_ext[tx_pointer];
else
tx_bit = extended_chain_std[tx_pointer];
end
// MJ: what is this? maybe total data length ?
-always @(rst or posedge clk_i)
+always @(rst or posedge clk)
begin
if (rst)
- limited_tx_cnt_ext = 0;
- limited_tx_cnt_std = 0;
- else begin
+ begin
+ limited_tx_cnt_ext <= 0;
+ limited_tx_cnt_std <= 0;
+ tx_is_extended_frame <= 1'b0;
+ end
+ else
+ begin
// there bytes are header; they are always read before the data bytes
if (tx_data_addr_o == 0)
- limited_tx_cnt_ext = tx_data[3] ? 6'h3f : ((tx_data[2:0] <<3) - 1'b1);
+ begin
+ limited_tx_cnt_ext <= tx_data_i[3] ? 6'h3f : ((tx_data_i[2:0] <<3) - 1'b1);
+ tx_is_extended_frame <= r_tx_data[0];
+ end
if (tx_data_addr_o == 1)
- limited_tx_cnt_ext = tx_data[3] ? 6'h3f : ((tx_data[2:0] <<3) - 1'b1);
+ limited_tx_cnt_ext <= tx_data_i[3] ? 6'h3f : ((tx_data_i[2:0] <<3) - 1'b1);
end
end
-assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 6'd38 ) | // arbitration + control for extended format
- ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 6'd18 ) | // arbitration + control for extended format
- ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 6'd18 ) | // arbitration + control for standard format
- ((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == limited_tx_cnt_ext) | // data (overflow is OK here)
- ((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == limited_tx_cnt_std) | // data (overflow is OK here)
+// TODO: !!!!! tx_is_extended_frame in header field !!!!!
+assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & tx_is_extended_frame & tx_pointer == 6'd38 ) | // arbitration + control for extended format
+ ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~tx_is_extended_frame) & tx_pointer == 6'd18 ) | // arbitration + control for extended format
+ ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 6'd18 ) | // arbitration + control for standard format
+ ((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == limited_tx_cnt_ext) | // data (overflow is OK here)
+ ((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == limited_tx_cnt_std) | // data (overflow is OK here)
( tx_point & rx_crc_lim ) | // crc
(go_rx_idle ) | // at the end
(reset_mode ) |
projects / fpga / zynq / canbench-sw.git / commitdiff