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(parent: 8a74eec) | patch
sja1000: synchronous with AXI, duplex register access (WIP)
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 12 May 2016 11:49:54 +0000 (13:49 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 12 May 2016 23:56:00 +0000 (01:56 +0200)
commit3a3155d08b2b359f32117faa35ba38f13d78c263
tree084991110b5de808c9768ebb7b9095789bffd65etree | snapshot
parent8a74eec78d9c75dac52446d98a484b774e85e2b9commit | diff
sja1000: synchronous with AXI, duplex register access (WIP)
system/ip/sja1000_1.0/component.xml diff | blob | history
system/ip/sja1000_1.0/hdl/can_bsp.v diff | blob | history
system/ip/sja1000_1.0/hdl/can_defines.v diff | blob | history
system/ip/sja1000_1.0/hdl/can_fifo.v diff | blob | history
system/ip/sja1000_1.0/hdl/can_ifc_axi.v diff | blob | history
system/ip/sja1000_1.0/hdl/can_ifc_axi_sync.v [new file with mode: 0644] blob
system/ip/sja1000_1.0/hdl/can_ifc_axi_sync_duplex.v [new file with mode: 0644] blob
system/ip/sja1000_1.0/hdl/can_registers.v diff | blob | history
system/ip/sja1000_1.0/hdl/can_top_raw.v diff | blob | history
system/ip/sja1000_1.0/hdl/rw_arbiter.v [new file with mode: 0644] blob
system/ip/sja1000_1.0/hdl/sja1000.v diff | blob | history
CAN benchmark FPGA design and software for MicroZed board